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| features ? incorporates the arm926ej-s? arm ? thumb ? processor ? dsp instruction extensions ? arm jazelle ? technology for java ? acceleration ? 16-kbyte data cache, 16-kbyte instruction cache, write buffer ? 200 mips at 180 mhz ? memory management unit ? embeddedice ? in-circuit emulation, debug communication channel support ? mid-level implementation embedded trace macrocell? additional embe dded memories ? 32k bytes of internal rom, single-cycle acce ss at maximum bus speed ? 160k bytes of internal sram, single-cyc le access at maximum processor or bus speed external bus interface (ebi) ? supports sdram, static memory , nand flash and compactflash ? lcd controller ? supports passive or active displays ? up to 16-bits per pixel in stn color mode ? up to 16m colors in tft mo de (24-bit per pixel), reso lution up to 2048 x 2048 usb ? usb 2.0 full speed (12 mbits per second) host double port dual on-chip transceivers integrated fifos and dedicated dma channels ? usb 2.0 full speed (12 mb its per second) device port on-chip transceiver, 2-kbyte co nfigurable integrated fifos bus matrix ? handles five masters and five slaves ? boot mode select option ? remap command fully featured system controller (sysc) fo r efficient system management, including ? reset controller, shutdown controller, fo ur 32-bit battery backup registers for a total of 16 bytes ? clock generator and power management controller ? advanced interrupt controller and debug unit ? periodic interval timer, watchdog timer and real-time timer ? three 32-bit pio controllers reset controller (rstc) ? based on power-on reset cells, reset source identification and reset output control shutdown controller (shdwc) ? programmable shutdown pin control and wake-up circuitry clock generator (ckgr) ? 32.768 khz low-power oscillator on battery backup power supply, providing a permanent slow clock ? 3 to 20 mhz on-chip oscillator and two plls power management controller (pmc) ? very slow clock operating mode, softw are programmable power optimization capabilities ? four programmable external clock signals arm926ej-s ? - based microcontroller at91sam9261 6062b?atarm?15-nov-05
2 6062b?atarm?15-nov-05 at91sam9261 advanced interrupt controller (aic) ? individually maskable, eight-level pr iority, vectored interrupt sources ? three external interrupt sources and one fast interrupt source, spurious interrupt protected debug unit (dbgu) ? 2-wire usart and support for de bug communication channel, programmable ice access prevention periodic interval timer (pit) ? 20-bit interval timer plus 12-bit interval counter watchdog timer (wdt) ? key protected, programmable only once, windowed 12-bit counter, running at slow clock real-time timer (rtt) ? 32-bit free-running backup counter running at slow clock three 32-bit parallel input/output controllers (pio) pioa, piob and pioc ? 96 programmable i/o lines multiplexed with up to two peripheral i/os ? input change interrupt ca pability on each i/o line ? individually programmable open-drain, pull-up resistor and synchronous output nineteen peripheral dma (pdc) channels multimedia card interface (mci) ? compliant with multimedia cards and sdcards ? automatic protocol control and fast automatic da ta transfers with pdc, mmc and sdcard compliant three synchronous serial controllers (ssc) ? independent clock and frame sync sign als for each receiver and transmitter ? i2s analog interface support, time division multiplex support ? high-speed continuous data stream ca pabilities with 32-bit data transfer three universal synchronous/asynchro nous receiver transmitters (usart) ? individual baud rate generator, ir da infrared modulation/demodulation ? support for iso7816 t0/t1 smart card, hardwa re and software handshaking, rs485 support two master/slave serial peripheral interface (spi) ? 8- to 16-bit programmable da ta length, four external peripheral chip selects one three-channel 16-bi t timer/counters (tc) ? three external clock inputs, two multi-purpose i/o pins per channel ? double pwm generation, capture/waveform mode, up/down capability two-wire interface (twi) ? master mode support, all tw o-wire atmel eeproms supported ieee 1149.1 jtag boundary scan on all digital pins required power supplies: ? 1.08v to 1.32v for vddcore and vddbu ? 2.7v to 3.6v for vddosc and for vddpll ? 2.7v to 3.6v for vddiop (peripheral i/os) and for vddiom (memory i/os) available in a 217-ball lfbga rohs-compliant package 3 6062b?atarm?15-nov-05 at91sam9261 1. description the at91sam9261 is a comp lete system-on-chip built around the arm926ej-s arm thumb processor with an extended dsp instruction set and jazelle java accelerator. it achieves 200 mips at 180 mhz. the at91sam9261 is an optimized host processor for applications with an lcd display. its integrated lcd controller supports bw and up to 16m color, active and passive lcd displays. the 160-kbyte integrated sram ca n be configured as a frame buffer minimiz- ing the impact for lcd refresh on the overall processor performance. the external bus interface incorporates controllers for synchronous dram (sdram) and static memo- ries and features specific interface circ uitry for compactflash and nand flash. the at91sam9261 integrates a rom-based boot loader supporting code shadowing from, for example, external dataflash ? into external sdram. the software controlled power management controller (pmc) keeps sy stem power consumption to a minimum by selectively enabling/disabling the proc essor and various peripherals and adjustment of the operating frequency. the at91sam9261 also benefits from the integration of a wide range of debug features including jtag-ice, a dedicated uart debug channel (dbgu) and an embedded real time trace. this enables the development a nd debug of all applications, especially those with real-time constraints. 4 6062b?atarm?15-nov-05 at91sam9261 2. block diagram figure 2-1. at91sam9261 block diagram pio id id ssc0 ssc1 ssc2 timer counter tc0 tc1 tc2 twi lcd controller dma fifo lut dma fifo usb host fifo usb device arm926ej-s core jtag boundary scan ice aic fast sram 160k bytes pio instruction cache 16k bytes fast rom 32k bytes peripheral bridge peripheral dma controller plla pllb itcm dtcm tcm interface pmc rstc osc pioa piob pioc rtt shdwc por osc wdt gpbreg pit por ebi static memory controller pio data cache 16k bytes mmu pio 5-layer matrix etm compactflash nand flash sdram controller biu pio pio transceiver transceiver pdc pdc pdc apb dbgu mci usart0 usart1 usart2 spi0 spi1 pdc pdc pdc pdc pdc pdc pdc system controller tf0 tk0 td0 rd0 rk0 rf0 tf1 tk1 td1 rd1 rk1 rf1 tf2 tk2 td2 rd2 rk2 rf2 tclk0 tclk1 tclk2 tioa0 tiob0 tioa1 tiob1 tioa2 tiob2 twd twck lcdd0-lcdd23 lcdvsync lcdhsync lcddotck lcdden lcdcc mcck mccda mcda0-mcda3 rxd0 txd0 sck0 rts0 cts0 rxd1 txd1 sck1 rts1 cts1 rxd2 txd2 sck2 rts2 cts2 spi0_npcs0 spi0_npcs1 spi0_npcs2 spi0_npcs3 spi0_miso spi0_mosi spi0_spck spi1_npcs10 spi1_npcs1 spi1_npcs12 spi1_npcs3 spi1_miso spi1_mosi spi1_spck d0-d15 a0/nbs0 a2-a15/a18-a21 a16/ba0 a17/ba1 ncs0 ncs1/sdcs ncs3/nandcs nrd/cfoe nwr0/nwe/cfwe nwr1/nbs1/cfior nwr3/nbs3/cfiow sdck sdcke ras-cas sdwe sda10 a23-a24 ncs5/cfcs1 bms ncs2 a25/cfrnw ncs4/cfcs0 ncs6/nandoe ncs7/nandwe tsync tclk tps0-tps2 tpk0-tpk15 d16-d31 a1/nbs2/nwr2 nwait hdma hdpb hdpa hdmb ddm ddp cfce1 cfce2 jtagsel tdi tdo rtck tms tck ntrst fiq irq0-irq2 pllrcb pllrca drxd dtxd xin32 xout32 nrst pck0-pck3 shdn wkup gndbu xin xout vddbu vddcore tst a22/reg 5 6062b?atarm?15-nov-05 at91sam9261 3. signal description table 3-1. signal description by peripheral signal name function type active level comments power vddiom ebi i/o lines power supply power 2.7v to 3.6v vddiop peripherals i/o lines power supply power 2.7v to 3.6v vddbu backup i/o lines power supply power 1.08v to 1.32v vddpll pll power supply power 2.7v to 3.6v vddosc oscillator power supply power 2.7v to 3.6v vddcore core chip power supply power 1.08v to 1.32v gnd ground ground gndpll pll ground ground gndosc oscillator ground ground gndbu backup ground ground clocks, oscillators and plls xin main oscillator input input xout main oscillator output output xin32 slow clock oscillator input input xout32 slow clock oscillator output output pllrca pll filter input pllrcb pll filter input pck0 - pck3 programmable clock output output shutdown, wakeup logic shdn shutdown control output driven at 0v only. do not tie over vddbu wkup wake-up input input accept between 0v and vddbu. ice and jtag tck test clock input no pull-up resistor. rtck returned test clock output no pull-up resistor. tdi test data in input no pull-up resistor. tdo test data out output tms test mode select input no pull-up resistor. ntrst test reset signal input low pull-up resistor. jtagsel jtag selection input pull-down resistor. etm tsync trace synchronization signal output tclk trace clock output tps0 - tps2 trace arm pipeline status output 6 6062b?atarm?15-nov-05 at91sam9261 tpk0 - tpk15 trace packet port output reset/test nrst microcontroller reset i/o low pull-up resistor tst test mode select input pull-down resistor. bms boot mode select input debug unit drxd debug receive data input dtxd debug transmit data output aic irq0 - irq2 external interrupt inputs input fiq fast interrupt input input pio pa0 - pa31 parallel io controller a i/o pulled-up input at reset pb0 - pb31 parallel io controller b i/o pulled-up input at reset pc0 - pc31 parallel io controller c i/o pulled-up input at reset ebi d0 - d31 data bus i/o pulled-up input at reset a0 - a25 address bus output 0 at reset nwait external wait signal input low smc ncs0 - ncs7 chip select lines output low nwr0 - nwr3 write signal output low nrd read signal output low nwe write enable output low nbs0 - nbs3 byte mask signal output low compactflash support cfce1 - cfce2 compactflash chip enable output low cfoe compactflash output enable output low cfwe compactflash write enable output low cfior compactflash io read output low cfiow compactflash io write output low cfrnw compactflash read not write output cfcs0 - cfcs1 compactflash ch ip select lines output low nand flash support nandoe nand flash output enable output low nandwe nand flash write enable output low table 3-1. signal description by peripheral (continued) signal name function type active level comments 7 6062b?atarm?15-nov-05 at91sam9261 nandcs nand flash chip select output low sdram controller sdck sdram clock output sdcke sdram clock enable output high sdcs sdram controller chip select output low ba0 - ba1 bank select output sdwe sdram write enable output low ras - cas row and column signal output low sda10 sdram address 10 line output multimedia card interface mcck multimedia card clock output mccda multimedia card a command i/o mcda0 - mcda3 multimedia card a data i/o usart sck0 - sck2 serial clock i/o txd0 - txd2 transmit data output rxd0 - rxd2 receive data input rts0 - rts2 request to send output cts0 - cts2 clear to send input synchronous serial controller td0 - td2 transmit data output rd0 - rd2 receive data input tk0 - tk2 transmit clock i/o rk0 - rk2 receive clock i/o tf0 - tf2 transmit frame sync i/o rf0 - rf2 receive frame sync i/o timer/counter tclk0 - tclk2 external clock input input tioa0 - tioa2 i/o line a i/o tiob0 - tiob2 i/o line b i/o spi spi0_miso - spi1_miso master in slave out i/o spi0_mosi - spi1_mosi master out slave in i/o spi0_spck - spi1_spck spi serial clock i/o table 3-1. signal description by peripheral (continued) signal name function type active level comments 8 6062b?atarm?15-nov-05 at91sam9261 spi0_npcs0, spi1_npcs0 spi peripheral chip select 0 i/o low spi0_npcs1 - spi0_npcs3 spi1_npcs1 - spi1_npcs3 spi peripheral chip select output low two-wire interface twd two-wire serial data i/o twck two-wire serial clock i/o lcd controller lcdd0 - lcdd23 lcd data bus output lcdvsync lcd vertical synchronization output lcdhsync lcd horizontal synchronization output lcddotck lcd dot clock output lcdden lcd data enable output lcdcc lcd contrast control output usb device port ddm usb device port data - analog ddp usb device port data + analog usb host port hdma usb host port a data - analog hdpa usb host port a data + analog hdmb usb host port b data - analog hdpb usb host port b data + analog table 3-1. signal description by peripheral (continued) signal name function type active level comments 9 6062b?atarm?15-nov-05 at91sam9261 4. package and pinout the atsam9261 is available in a 217-ball lfbga rohs-compliant package, 15 x 15 mm, 0.8 mm ball pitch 4.1 mechanical overview of t he 217-ball lfbga package figure 4-1 shows the orientation of the 217-ball lfbga package. a detailed mechanical description is given in the mechanical characteristics section of the product datasheet. figure 4-1. 217-ball lfbga pinout (top view) 4.2 217-ball lfbga package pinout a b c d e f g h j k l m n p r t u 1234567891011121314151617 table 4-1. at91sam9261 pinout for 217-ball lfbga package (1) pin signal name pin signal name pin signal name pin signal name a1 a19 d5 vddcore j14 vddiop p17 pa20 a2 a16/ba0 d6 a10 j15 pb9 r1 pc19 a3 a14 d7 a5 j16 pb6 r2 pc21 a4 a12 d8 a0/nbs0 j17 pb4 r3 gnd a5 a9 d9 shdw k1 d6 r4 pc27 a6 a6 d10 nc k2 d8 r5 pc29 a7 a3 d11 vddiop k3 d10 r6 pc4 a8 a2 d12 pb29 k4 d7 r7 pc8 a9 nc d13 pb28 k8 gnd r8 pc12 a10 xout32 d14 pb23 k9 gnd r9 pc14 a11 xin32 d15 pb20 k10 gnd r10 vddpll a12 ddp d16 pb17 k14 vddcore r11 pa0 a13 hdpb d17 tck k15 pb3/bms r12 pa7 a14 hdmb e1 nwr1/nbs1/cfior k16 pb1 r13 pa10 a15 pb27 e2 nwr0/nwe/cfwe k17 pb2 r14 pa13 a16 gnd e3 nrd/cfoe l1 d9 r15 pa17 a17 pb24 e4 sda10 l2 d11 r16 gnd b1 a20 e14 pb22 l3 d12 r17 pa18 b2 a18 e15 pb18 l4 vddiom t1 pc20 b3 a15 e16 pb15 l14 pa30 t2 pc23 b4 a13 e17 tdi l15 pa27 t3 pc26 10 6062b?atarm?15-nov-05 at91sam9261 note: 1. shaded cells define the pins powered by vddiom. b5 a11 f1 sdcke l16 pa31 t4 pc2 b6 a7 f2 ras l17 pb0 t5 vddiop b7 a4 f3 nwr3/nbs3/cfiow m1 d13 t6 pc5 b8 a1/nbs2/nwr2 f4 ncs0 m2 d15 t7 pc9 b9 vddbu f14 pb16 m3 pc18 t8 pc10 b10 jtagsel f15 nrst m4 vddcore t9 pc15 b11 wkup f16 tdo m14 pa25 t10 vddosc b12 ddm f17 ntrst m15 pa26 t11 gndosc b13 pb31 g1 d0 m16 pa28 t12 pa1 b14 hdma g2 d1 m17 pa29 t13 pa4 b15 pb26 g3 sdwe n1 d14 t14 pa6 b16 pb25 g4 ncs3/nandcs n2 pc17 t15 pa8 b17 pb19 g14 pb14 n3 pc31 t16 pa11 c1 a22 g15 pb12 n4 vddiom t17 pa14 c2 a21 g16 pb11 n14 pa22 u1 pc25 c3 vddiom g17 pb8 n15 pa21 u2 pc0 c4 a17/ba1 h1 d2 n16 pa23 u3 pc3 c5 vddiom h2 d3 n17 pa24 u4 gnd c6 a8 h3 vddiom p1 pc16 u5 pc6 c7 gnd h4 sdck p2 pc30 u6 vddiop c8 vddiom h8 gnd p3 pc22 u7 gnd c9 gndbu h9 gnd p4 pc24 u8 pc13 c10 tst h10 gnd p5 pc28 u9 pllrcb c11 gnd h14 pb10 p6 pc1 u10 pllrca c12 hdpa h15 pb13 p7 pc7 u11 xin c13 pb30 h16 pb7 p8 pc11 u12 xout c14 nc h17 pb5 p9 gndpll u13 pa2 c15 vddiop j1 d4 p10 pa3 u14 pa5 c16 pb21 j2 d5 p11 vddiop u15 pa12 c17 tms j3 gnd p12 vddcore u16 pa9 d1 ncs2 j4 cas p13 pa15 u17 rtck d2 ncs1/sdcs j8 gnd p14 pa16 d3 gnd j9 gnd p15 vddiop d4 vddiom j10 gnd p16 pa19 table 4-1. at91sam9261 pinout for 217-ball lfbga package (1) (continued) pin signal name pin signal name pin signal name pin signal name 11 6062b?atarm?15-nov-05 at91sam9261 5. power considerations 5.1 power supplies the at91sam9261 has six types of power supply pins: vddcore pins: power the core, including the processor, the memories and the peripherals; voltage ranges from 1.08v and 1.32v, 1.2v nominal. vddiom pins: power the external bus interf ace i/o lines; voltage ranges from 2.7v and 3.6v, 3.3v nominal. vddiop pins: power the peripheral i/o lines and the usb transceivers; voltage ranges from 2.7v and 3.6v, 3.3v nominal. vddbu pin: powers the slow clock oscilla tor and a part of the system controller; voltage ranges from 1.08v and 1.32v, 1.2v nominal. vddpll pin: powers the pll cells; voltage ranges from 2.7v and 3.6v, 3v or 3.3v nominal. vddosc pin: powers the main oscillator ce lls; voltage ranges from 2.7v and 3.6v, 3v or 3.3v nominal. the double power supplies vddiom and vddiop are identified in table 4-1 on page 9 . these supplies enable the user to power the device differently for interfacing with mem- ories and for interfacing with peripherals. ground pins gnd are commo n to vddcore, vddiom and vddiop pins power sup- plies. separated ground pins are provided for vddbu, vddosc and vddpll. the ground pins are respectively gndbu, gndosc and gndpll. 5.2 power consumption the at91sam9261 consumes about 550 a of static current on vddcore at 25c. this static current rises at up to 5.5 ma if the temperature increases to 85c. on vddbu, the current does not exceed 3 a @25c, but can rise at up to 20 a @85c. for dynamic power consumption, the at91sam9261 consumes a maximum of 50 ma on vddcore at maximum speed in typical conditions (1.2v, 25c), processor running full-performance algorithm. 6. i/o line considerations 6.1 jtag port pins tms, tdi and tck are schmitt trigger inputs and have no pull-up resistors. tdo and rtck are outputs, driven at up to vddiop, and have no pull-up resistor. the jtagsel pin is used to select the jtag boundary scan when asserted at a high level. it integrates a permanent pull-down resistor of about 15 k ? to gndbu, so that it can be left unconnected for normal operations. the ntrst pin is used to initialize the embedded ice tap controller when asserted at a low level. it integrates a permanent pull-up resistor of about 15 k ? to vddiop, so that it can be left unconnected for normal operations. 12 6062b?atarm?15-nov-05 at91sam9261 6.2 test pin the tst pin is used for manufacturing test pu rposes when asserted high. it integrates a permanent pull-down resistor of about 15 k ? to gndbu, so that it can be left uncon- nected for normal operations. driving this li ne at a high level leads to unpredictable results. 6.3 reset pin nrst is an open-drain output integrating a non-programmable pull-up resistor. it can be driven with voltage at up to vddiop. as the product integrates power-on reset cells, the nrst pin can be left unconnected in case no reset from the system needs to be applied to the product. the nrst pin integrates a permanent pull-up resistor of 100 k ? minimum to vddiop. the nrst signal is inserted in the boundary scan. 6.4 pio controller a, b and c lines all the i/o lines pa0 to pa31, pb0 to pb31, and pc0 to pc31 integrate a programmable pull-up resistor of 100 k ? . programming of this pull-up resistor is performed indepen- dently for each i/o line through the pio controllers. after reset, all the i/o lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the external bus interface signals that require to be enabled as peripherals at reset. this is explicitly indicated in the co lumn ?reset state? of the pio controller multiplexing tables. 6.5 shutdown logic pins the shdn pin is an output only, which is driv en by the product only at low level. it can be tied high with an external pull-up resistor at vddbu only. the pin wkup is an input-only. it can ac cept voltages only between 0v and vddbu. 13 6062b?atarm?15-nov-05 at91sam9261 7. processor and architecture 7.1 arm926ej-s processor risc processor based on arm v5tej archit ecture with jazelle technology for java acceleration two instruction sets ? arm high-performance 32-bit instruction set ? thumb high code density 16-bit instruction set dsp instruction extensions 5-stage pipeline architecture: ? instruction fetch (f) ? instruction decode (d) ? execute (e) ? data memory (m) ? register write (w) 16-kbyte data cache, 16-kbyte instruction cache ? virtually-addressed 4-way associative cache ? eight words per line ? write-through and write-back operation ? pseudo-random or round-robin replacement write buffer ? main write buffer with 16-word data buffer and 4-address buffer ? dcache write-back buffer with 8-word entries and a single address entry ? software control drain standard arm v4 and v5 memory management unit (mmu) ? access permission for sections ? access permission for large pages and small pages can be specified separately for each quarter of the page ? 16 embedded domains bus interface unit (biu) ? arbitrates and schedules ahb requests ? separate masters for both instruction and data access providing complete ahb system flexibility ? separate address and data buses for both the 32-bit instruction interface and the 32-bit data interface ? on address and data buses, data can be 8-bit (bytes), 16-bit (half-words) or 32-bit (words) 14 6062b?atarm?15-nov-05 at91sam9261 7.2 debug and test features integrated embedded in-circuit emulator real-time ? two real-time watchpoint units ? two independent registers: debug control register and debug status register ? test access port accessible through jtag protocol ? debug communications channel debug unit ?two-pin uart ? debug communication channel interrupt handling ? chip id register embedded trace macrocell: etm9 ? ? medium+ level implementation ? half-rate clock mode ? four pairs of address comparators ? two data comparators ? eight memory map decoder inputs ? two 16-bit counters ? one 3-stage sequencer ? one 45-byte fifo ieee1149.1 jtag boundary-scan on all digital pins 7.3 bus matrix five masters and five slaves handled ? handles requests from the arm926ej-s, usb host port, lcd controller and the peripheral dma controller to internal rom, internal sram, ebi, apb, lcd controller and usb host port. ? round-robin arbitration (three modes supported: no default master, last accessed default master, fixed default master) ? burst breaking with slot cycle limit one address decoder provided per master ? three different slaves may be assigned to each decoded memory area: one for internal boot, one for external boot, one after remap. boot mode select option ? non-volatile boot memory can be internal or external. ? selection is made by bms pin sampled at reset. remap command ? allows remapping of an internal sram in place of the boot non-volatile memory ? allows handling of dynamic exception vectors 15 6062b?atarm?15-nov-05 at91sam9261 7.4 peripheral dma controller transfers from/to peripheral to/from any memory space without intervention of the processor. next pointer support, forbids strong real-time constraints on buffer management. nineteen channels ? two for each usart ? two for the debug unit ? two for each serial synchronous controller ? two for each serial peripheral interface ? one for the multimedia card interface 8. memories 8.1 embedded memories 32k-byte rom ? single cycle access at full bus speed 160k-byte fast sram ? single cycle access at full bus speed ? supports arm926ej-s tcm interface at full processor speed 8.2 memory mapping a first level of address decoding is performed by the bus matrix, i.e., the implementation of the advanced high performance bus (ahb) for its master and slave interfaces with additional features. decoding breaks up the 4g bytes of address space into 16 areas of 256m bytes. the areas 1 to 8 are directed to the ebi that associates these areas to the external chip selects ncs0 to ncs7. the area 0 is reserved for the addressing of the internal memo- ries, and a second level of decoding provides 1m byte of internal memory area. the area 15 is reserved for the peripherals and provides access to the advanced peripheral bus (apb). other areas are unused and performing an access within them provides an abort to the master requesting such an access. figure 8-1. product memory mapping 0x0000 0000 0x0fff ffff 0x1000 0000 0x8fff ffff 0xefff ffff 0xf000 0000 0xffff ffff 256m bytes 8 x 256m bytes 2,048m bytes 256m bytes 6 x 256m bytes 1,536m bytes internal memories external bus interface chip select 0 to 7 undefined (abort) internal peripherals 0x9000 0000 16 6062b?atarm?15-nov-05 at91sam9261 the bus matrix manages five masters and five slaves. each master has its own bus and its own decoder, thus allowing a different memory mapping per master. regarding master 0 and master 1 (arm926 instruction and data), three different slaves are assigned to the memory space decoded at address 0x0: one for internal boot, one for external boot, one after remap, refer to table 8-3 for details. each slave has its own arbiter, thus allowing a different arbitration per slave. 8.2.1 external memory mapping the external memories are accessed through the external bus interface (bus matrix slave 3). figure 8-2. external memory mapping table 8-1. list of bus matrix masters master 0 arm9 26 instruction master 1 arm926 data master 2 pdc master 3 lcd controller master 4 usb host table 8-2. list of bus matrix slaves slave 0 internal sram slave 1 internal rom slave 2 lcd controller and usb host port interfaces slave 3 external bus interface slave 4 internal peripherals 0x1000 0000 0x1fff ffff 0x2000 0000 0x2fff ffff 0x3000 0000 0x3fff ffff 0x4000 0000 0x4fff ffff 0x5000 0000 0x5fff ffff 0x6000 0000 0x6fff ffff 0x7000 0000 0x7fff ffff 0x8000 0000 0x8fff ffff 256m bytes 256m bytes 256m bytes 256m bytes 256m bytes 256m bytes 256m bytes 256m bytes chip select 0 chip select 1 chip select 2 chip select 3 chip select 4 chip select 5 chip select 6 chip select 7 smc smc or sdramc smc smc smc smc smc smc compactflash slot 0 nand flash compactflash slot 1 17 6062b?atarm?15-nov-05 at91sam9261 8.2.2 internal memory mapping table 8-3 summarizes the internal memory mapping for each master, depending on the remap status and the bms state at reset. 8.2.2.1 internal sram the at91sam9261 embeds a high-speed 160-kbyte sram. this internal sram is split into three areas. its memory mapping is detailed in table 8-3 above. internal sram a is the arm926ej-s inst ruction tcm and the user can map this sram block anywhere in the arm926 instruction memory space using cp15 instructions. this sram block is also acce ssible by the arm926 data master and by the ahb masters through the ahb bus at address 0x0010 0000. internal sram b is the arm926ej-s data tcm and the user can map this sram block anywhere in the arm926 data memory space using cp15 instructions. this sram block is also accessible by the ar m926 data master and by the ahb masters through the ahb bus at address 0x0020 0000. internal sram c is only accessible by all the ahb masters. after reset and until the remap command is performed, this sram block is accessible through the ahb bus at address 0x0030 0000 by all the ahb masters. after remap, this sram block also becomes accessible through the ahb bus at address 0x0 by the arm926 instruction and the arm926 data masters. within the 160-kbyte sram size available, the amount of memory assigned to each block is software programmable as a multiple of 16k bytes according to table 8-4 . this table 8-3. internal memory mapping address master 0: arm926 instruction master 1: arm926 data master 2: pdc master 3: lcd controller master 4: usb host remap (rcb0) = 0 remap (rcb0) = 1 remap (rcb1) = 0 remap (rcb1) = 1 bms = 1 bms = 0 bms = 1 bms = 0 0x0000 0000 int. rom ebi ncs0 int. ram c int. rom ebi ncs0 int. ram c 0x0010 0000 int. ram a int. ram a int. ram a int. ram a int. ram a int. ram a int. ram a int. ram a int. ram a 0x0020 0000 int. ram b int. ram b int. ram b int. ram b int. ram b int. ram b int. ram b int. ram b int. ram b 0x0030 0000 int. ram c int. ram c int. ram c int. ram c int. ram c int. ram c int. ram c int. ram c int. ram c 0x0040 0000 int. rom int. rom int. rom int. rom int. rom int. rom int. rom int. rom int. rom 0x0050 0000 - - - uhp i/f uhp i/f uhp i/f - - - 0x0060 0000 - - - lcd i/f lcd i/f lcd i/f - - - 18 6062b?atarm?15-nov-05 at91sam9261 table provides the size of the internal sram c according to the size of the internal sram a and the internal sram b. note that among the ten 16-kbyte blocks making up the internal sram, two are perma- nently assigned to internal sram c. at reset, the whole memory (160k bytes) is assigned to internal sram c. the memory blocks assigned to sram a, sram b and sram c areas are not contigu- ous and when the user dynamically changes the internal sram configuration, the new 16-kbyte block organization may affect the previous configuration from a software point of view. table 8-5 illustrates different configurations and the related 16-kbyte blocks (rb0 to rb9) assignments. table 8-4. internal sram block size internal sram c intern al sram a (itcm) size 0 16k bytes 32k bytes 64k bytes internal sram b (dtcm) size 0 160k bytes 144k bytes 128k bytes 96k bytes 16k bytes 144k bytes 128k bytes 112k bytes 80k bytes 32k bytes 128k bytes 112k bytes 96k bytes 64k bytes 64k bytes 96k bytes 80k bytes 64k bytes 32k bytes table 8-5. 16-kbyte block allocation decoded area address configuration examples and rela ted 16-kbyte block assignments itcm = 0 kbyte dtcm = 0 kbyte ahb = 160k bytes (1) itcm = 64k bytes dtcm = 64k bytes ahb = 32k bytes itcm = 32k bytes dtcm = 64k bytes ahb = 64k bytes itcm = 32k bytes dtcm = 16k bytes ahb = 112k bytes internal sram a (itcm) 0x0010 0000 rb3 rb3 rb3 0x0010 4000 rb2 rb2 rb2 0x0010 8000 rb1 0x0010 c000 rb0 internal sram b (dtcm) 0x0020 0000 rb7 rb7 rb7 0x0020 4000 rb6 rb6 0x0020 8000 rb5 rb5 0x0020 c000 rb4 rb4 19 6062b?atarm?15-nov-05 at91sam9261 note: 1. configuration after reset. 8.2.2.2 internal rom the at91sam9261 integrates 32-kbyte internal rom mapped at address 0x0040 0000. it is also accessible at address 0x0 after reset and before remap if the bms is tied high during reset. 8.2.2.3 usb host port the at91sam9261 integrates a usb host port open host controller interface (ohci). the registers of this interface are directly accessible on the ahb bus and are mapped like a standard internal memory at address 0x0050 0000. 8.2.2.4 lcd controller the at91sam9261 integrates an lcd controller. the interface is directly accessible on the ahb bus and is mapped like a standard internal memory at address 0x0060 0000. 8.2.3 boot program dataflash boot ? downloads and runs an application from spi dataflash into internal sram ? downloaded code size from spi dataflash depends on embedded sram size ? automatic detection of valid application ? spi dataflash connected to spi npcs0 boot uploader in case no valid program is detected in external spi dataflash ? small monitor functionalities (r ead/write/run) interface with samba application ? automatic detection of the communication link serial communication on a dbgu (xmodem protocol) usb device port (cdc protocol) internal sram c (ahb) 0x0030 0000 rb9 rb9 rb9 rb9 0x0030 4000 rb8 rb8 rb8 rb8 0x0030 8000 rb7 rb1 rb6 0x0030 c000 rb6 rb0 rb5 0x0031 0000 rb5 rb4 0x0031 4000 rb4 rb1 0x0031 8000 rb3 rb0 0x0031 c000 rb2 0x0032 0000 rb1 0x0032 4000 rb0 table 8-5. 16-kbyte block allocation (continued) decoded area address configuration examples and rela ted 16-kbyte block assignments itcm = 0 kbyte dtcm = 0 kbyte ahb = 160k bytes (1) itcm = 64k bytes dtcm = 64k bytes ahb = 32k bytes itcm = 32k bytes dtcm = 64k bytes ahb = 64k bytes itcm = 32k bytes dtcm = 16k bytes ahb = 112k bytes 20 6062b?atarm?15-nov-05 at91sam9261 8.2.4 etm memories the eight etm9 medium+ memory map decoder inputs are connected to custom address decoders and the resulting memory mapping is summarized in table 8-6 . table 8-6. etm9 memory mapping product resource area access type start address end address sram internal data 0x0000 0000 0x002f ffff sram internal fetch 0x0000 0000 0x002f ffff rom internal data 0x0040 0000 0x004f ffff rom internal fetch 0x0040 0000 0x004f ffff external bus interface external data 0x1000 0000 0x8fff ffff external bus interface external fetch 0x1000 0000 0x8fff ffff user peripherals internal d ata 0xf000 0000 0xffff bfff system peripherals internal data 0xffff c000 0xffff ffff 21 6062b?atarm?15-nov-05 at91sam9261 9. system controller the system controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. 9.1 block diagram figure 9-1. system controller block diagram nrst slck advanced interrupt controller real-time timer periodic interval timer reset controller pa0-pa31 periph_nreset system controller watchdog timer wdt_fault wdrproc pio controllers power management controller xin xout pllrca mainck pllack pit_irq mck proc_nreset wdt_irq periph_irq{2..4] periph_nreset periph_clk[2..21] pck mck pmc_irq udpck nirq nfiq rtt_irq embedded peripherals periph_clk[2..4] pck[0-3] in out enable arm926ej-s slck slck irq0-irq2 fiq irq0-irq2 fiq periph_irq[6..21] periph_irq[2..21] int int periph_nreset periph_clk[6..21] jtag_nreset ice_nreset proc_nreset periph_nreset dbgu_txd dbgu_rxd pit_irq rtt_irq dbgu_irq pmc_irq rstc_irq wdt_irq rstc_irq slck boundary scan tap controller jtag_nreset debug pck debug idle debug bus matrix mck periph_nreset proc_nreset backup_nreset periph_nreset idle debug unit dbgu_irq mck dbgu_rxd periph_nreset force_ntrst dbgu_txd usb device port udpck periph_nreset periph_clk[10] periph_irq[10] usb_suspend usb_suspend rtt_alarm shutdown controller slck rtt_alarm backup_nreset shdn wkup 4 general-purpose backup registers backup_nreset xin32 xout32 lcdck pllrcb pllbck uhpck pb0-pb31 pc0-pc31 usb host port uhpck periph_nreset periph_clk[20] periph_irq[20] lcd controller lcdck periph_nreset periph_clk[21] periph_irq[21] vddbu powered vddcore powered force_ntrst ntrst vddcore por main osc plla vddbu por slow clock osc pllb ice_nreset 22 6062b?atarm?15-nov-05 at91sam9261 9.1.1 system controller mapping the system peripherals are all mapped within the highest 6k bytes of address space, between addresses 0xffff ea00 and 0xffff ffff. each peripheral has an address space of 256 or 512 bytes, representing 64 or 128 registers. figure 9-2 shows the mapping of the ebi peripherals, the matrix and the system controller. figure 9-2. system controller mapping 0xffff ffff 0xffff ff00 256 bytes/64 words peripheral name size 0xffff feff 0xffff fe00 0xffff fdff 0xffff fd00 0xffff fcff 0xffff fc00 0xffff fa00 0xffff f800 0xffff f600 0xffff f400 0xffff f200 0xffff f000 0xffff fbff 0xffff f9ff 0xffff f7ff 0xffff f5ff 0xffff f3ff 0xffff f1ff 256 bytes/64 words 16 bytes/4 words 256 bytes/64 words reset controller power management controller parallel i/o controller c parallel i/o controller b parallel i/o controller a debug unit advanced interrupt controller 512 bytes/128 words 512 bytes/128 words 512 bytes/128 words 512 bytes/128 words 512 bytes/128 words 512 bytes/128 words pmc reserved pioc piob pioa dbgu aic rstc reserved reserved 0xffff ee00 0xffff efff bus matrix 512 bytes/128 words matrix 0xffff ec00 0xffff edff static memory controller 512 bytes/128 words smc 0xffff ea00 0xffff ebff sdram controller 512 bytes/128 words sdramc 0xffff fd0f 0xffff fd10 16 bytes/4 words shutdown controller shdc 0xffff fd1f 0xffff fd20 16 bytes/4 words real-time timer controller rttc 0xffff fd2f 0xffff fd30 16 bytes/4 words periodic interval timer controller pitc 0xffff fd3f 0xffff fd40 16 bytes/4 words watchdog timer controller wdtc 0xffff fd4f 0xffff fd50 16 bytes/4 words general-purpose backup registers gpbr 0xffff fd5f 0xffff fd60 reserved 23 6062b?atarm?15-nov-05 at91sam9261 9.2 reset controller based on two power-on-reset cells status of the last reset ? either cold reset, first reset, soft reset, user reset, watchdog reset, wake-up reset controls the internal resets and the nrst pin output. 9.3 shutdown controller shutdown and wake-up logic: ? software programmable assertion of the shdn open-drain pin. ? deassertion programmable on a wkup pin level change or on alarm. 9.4 general-purpose backup registers four 32-bit general-purpose backup registers 9.5 clock generator embeds the low-power 32768 hz slow clock oscillator ? provides the permanent slow clock to the system embeds the main oscillator ? oscillator bypass feature ? supports 3 to 20 mhz crystals embeds two plls ? outputs 80 to 240 mhz clocks ? integrates an input divider to increase output accuracy ? 1 mhz minimum input frequency provides slck, mainck, pllack and pllbck. figure 9-3. clock generator block diagram power management controller xin xout pllrca slow clock slck main clock mainck plla clock pllack control status pll and divider b pllrcb pllb clock pllbck xin32 xout32 slow clock oscillator main oscillator pll and divider a clock generator 24 6062b?atarm?15-nov-05 at91sam9261 9.6 power management controller the power management controller provides: ? the processor clock pck ? the master clock mck ? the usb clock usbck ? the lcd controller clock lcdck ? up to thirty peripheral clocks ? four programmable clock outputs: pck0 to pck3 figure 9-4. power management co ntroller block diagram 9.7 periodic interval timer includes a 20-bit periodic counter with less than 1 s accuracy includes a 12-bit interval overlay counter real time os or linux ? /windows ce ? compliant tick generator 9.8 watchdog timer 12-bit key-protected only-once programmable counter windowed, prevents the processor to be in a dead-lock on the watchdog access. 9.9 real-time timer 32-bit free-running backup counter alarm register capable to generate a wake-up of the system mck periph_clk[2..21] int udpck usb_suspend slck mainck pllack prescaler /1,/2,/4,...,/64 pck processor clock controller idle mode master clock controller apb peripherals clock controller on/off usb clock controller on/off slck mainck pllack prescaler /1,/2,/4,...,/64 programmable clock controller pllbck divider /1,/2,/4 pck[0..3] pllbck pllbck uhpck divider /1,/2,/3,/4 lcdck ahb peripherals clock controller on/off 25 6062b?atarm?15-nov-05 at91sam9261 9.10 advanced interrupt controller controls the interrupt lines (nirq and nfiq) of an arm processor thirty-two individually maskable and vectored interrupt sources ? source 0 is reserved for the fast interrupt input (fiq) ? source 1 is reserved for system peripherals (pit, rtt, pmc, dbgu, etc.) ? source 2 to source 31 control up to thirty embedded peripheral interrupts or external interrupts ? programmable edge-triggered or level-sensitive internal sources ? programmable positive/negative edge-triggered or high/low level- sensitive four external sources 8-level priority controller ? drives the normal interrupt of the processor ? handles priority of the interrupt sources 1 to 31 ? higher priority interrupts can be served during service of lower priority interrupt vectoring ? optimizes interrupt service routine branch and execution ? one 32-bit vector register per interrupt source ? interrupt vector register reads the corresponding current interrupt vector protect mode ? easy debugging by preventing automatic operations when protect mode is enabled fast forcing ? permits redirecting any normal interrupt source on the fast interrupt of the processor general interrupt mask ? provides processor synchronization on events without triggering an interrupt 9.11 debug unit composed of four functions ?two-pin uart ? debug communication channel (dcc) support ? chip id registers ? ice access prevention two-pin uart ? implemented features are 100% compatible with the standard atmel usart ? independent receiver and transmitter with a common programmable baud rate generator ? even, odd, mark or space parity generation ? parity, framing and overrun error detection ? automatic echo, local loopback and remote loopback channel modes 26 6062b?atarm?15-nov-05 at91sam9261 ? support for two pdc channels with connection to receiver and transmitter debug communication channel support ? offers visibility of commrx and comm tx signals from the arm processor chip id registers ? identification of the device revision, sizes of the embedded memories, set of peripherals ice access prevention ? enables software to prevent system access through the arm processor?s ice ? prevention is made by asserting the ntrst line of the arm processor?s ice 9.12 pio controllers three pio controllers, each controlling up to 32 programmable i/o lines ? pioa has 32 i/o lines ? piob has 32 i/o lines ? pioc has 32 i/o lines fully programmable through set/clear registers multiplexing of two peripheral functions per i/o line for each i/o line (whether assigned to a peripheral or used as general-purpose i/o) ? input change interrupt ? glitch filter ? multi-drive option enables driving in open drain ? programmable pull up on each i/o line ? pin data status register, supplies visib ility of the level on the pin at any time synchronous output, provides set and clear of several i/o lines in a single write 27 6062b?atarm?15-nov-05 at91sam9261 10. peripherals 10.1 peripheral mapping 10.1.1 user peripheral mapping the user peripherals are mapped in the upper 256m bytes of the address space between the addresses 0xfffa 0000 and 0xfffc ffff. each user peripheral is allo- cated 16k bytes of address space. figure 10-1. user peripheral mapping peripheral name size 16k bytes 16k bytes 16k bytes 16k bytes 0xfffa 0000 0xfffa 3fff tc0, tc1, tc2 timer/counter 0, 1 and 2 16k bytes 16k bytes 16k bytes 16k bytes 0xfffa 4000 0xfffa 7fff mci multimedia card interface 0xfffb 4000 0xfffb 7fff twi two-wire interface 0xfffb 8000 0xfffb bfff usart0 universal synchronous asynchronous receiver transmitter 0 0xfffc 0000 0xfffc 3fff usart1 universal synchronous asynchronous receiver transmitter 1 0xfffc 4000 0xfffc 7fff ssc0 serial synchronous controller 0 0xfffc c000 0xfffc ffff ssc1 serial synchronous controller 1 spi0 serial peripheral interface 0 0xfffb 3fff 0xfffa c000 0xfffa ffff 0xfffb c000 0xfffb ffff 0xfffc bfff ssc2 serial synchronous controller 2 16k bytes usart2 16k bytes universal synchronous asynchronous receiver transmitter 2 16k bytes 0xfffa 8000 0xfffa bfff udp usb device port 16k bytes spi1 serial peripheral interface 1 0xfffb 0000 0xfffc 8000 28 6062b?atarm?15-nov-05 at91sam9261 10.2 peripheral multiplexing on pio lines the at91sam9261 features three pio controllers, pioa, piob and pioc, that multi- plex the i/o lines of the peripheral set. each pio controller controls up to thirty-t wo lines. each line can be assigned to one of two peripheral functions, a or b. the tables in the following pages define how the i/o lines of the peripherals a and b are multiple xed on the pio controllers. the two col- umns ?function? and ?comments? have been inserted for the user?s own comments; they may be used to track how pins are defined in an application. note that some output only peripheral func tions might be duplicated within the tables. the column ?reset state? indicates whether the pio line resets in i/o mode or in peripheral mode. if i/o is mentioned, the pio line resets in input with the pull-up enabled, so that the device is maintained in a static state as soon as the reset is released. as a result, the bit corresponding to the pio line in the register pio_psr (peripheral status register) resets low. if a signal name is mentioned in the ?reset state? column, the pio line is assigned to this function and the corresponding bit in pio_ psr resets high. this is the case of pins controlling memories, in particular the addre ss lines, which require the pin to be driven as soon as the reset is released. note that the pull-up resistor is also enabled in this case. 10.2.1 resource multiplexing 10.2.1.1 lcd controller the lcd controller can interface with several lcd panels. it supports 4, 8 or 16 bit-per- pixel without any limitation. interfacing 24 bit-per-pixel tfts panel prevents using the ssc0 and using the chip select line 0 of the spi1. 16 bit-per-pixel tft panels are interfaced through peripheral b functions, as colors data are output on lcdd3 to lcdd7, lcdd11 to lcdd15 and lcdd19 to lcdd23. inten- sity bit is output on lcdd2, lcdd10 and lcdd18. using the peripheral b does not prevents using the ssc0 and the spi1 lines. 10.2.1.2 etm using the etm prevents: using the usart1 and usart2 control signals, in particular the sck lines which are required to use the usart as iso7816 and the rts and cts to handle hardware handshaking on the serial lines. in case the etm and an iso7816 connection are both required, the usart0 has to be used as smart card interface. using the ssc1 addressing a more than 8-mbyte static memory, which requires the a23 and a24 address lines using the chip select lines 1 to 3 of spi0 and spi1 10.2.1.3 ebi if not required, the nwait function (external wait request) can be deactivated by soft- ware allowing this pin to be used as a pio. 29 6062b?atarm?15-nov-05 at91sam9261 10.2.1.4 32-bit data bus using a 32-bit data bus prevents: using the three timer counter channels? outputs and trigger inputs using the ssc2 10.2.1.5 nand flash interface using the nand flash interface prevents: using ncs3, ncs6 and ncs7 to access other parallel devices 10.2.1.6 compact flash interface using the compactflash interface prevents: using ncs4 and/or ncs5 to access other parallel devices 10.2.1.7 spi0 and the multimedia card interface as the dataflash card is compatible with th e sdcard, it is useful to multiplex spi and mci. here, the spi0 signal is multiplexed with the mci. 10.2.1.8 usarts using the usart1 and usart2 control signals prevents using the etm. alternatively, using usart0 with its control signals prevents using some clock outputs and interrupt lines. 10.2.1.9 clock outputs using the clock outputs multiplexed with the pio a prevents using the debug unit and/or the two wire interface. alternatively, using the second implementation of the clock outputs prevents using the lcd controller interface and/or usart0. 10.2.1.10 interrupt lines using fiq prevents using the usart0 control signals. using irq0 prevents using the nwait ebi signal. using the irq1 and/or irq2 prevents using the spi1. 30 6062b?atarm?15-nov-05 at91sam9261 10.2.2 pio controller a multiplexing table 10-1. multiplexing on pio controller a pio controller a application usage i/o line peripheral a peripheral b reset state function comments pa0 spi0_miso mcda0 i/o pa1 spi0_mosi mccda i/o pa2 spi0_spck mcck i/o pa3 spi0_npcs0 i/o pa4 spi0_npcs1 mcda1 i/o pa5 spi0_npcs2 mcda2 i/o pa6 spi0_npcs3 mcda3 i/o pa7 twd pck0 i/o pa 8 t w c k p c k 1 i / o pa9 drxd pck2 i/o pa10 dtxd pck3 i/o pa11 tsync sck1 i/o pa12 tclk rts1 i/o pa13 tps0 cts1 i/o pa14 tps1 sck2 i/o pa15 tps2 rts2 i/o pa16 tpk0 cts2 i/o pa17 tpk1 tf1 i/o pa18 tpk2 tk1 i/o pa19 tpk3 td1 i/o pa20 tpk4 rd1 i/o pa21 tpk5 rk1 i/o pa22 tpk6 rf1 i/o pa23 tpk7 rts0 i/o pa24 tpk8 spi1_npcs1 i/o pa25 tpk9 spi1_npcs2 i/o pa26 tpk10 spi1_npcs3 i/o pa27 tpk11 spi0_npcs1 i/o pa28 tpk12 spi0_npcs2 i/o pa29 tpk13 spi0_npcs3 i/o pa30 tpk14 a23 a23 pa31 tpk15 a24 a24 31 6062b?atarm?15-nov-05 at91sam9261 10.2.3 pio controller b multiplexing table 10-2. multiplexing on pio controller b pio controller b application usage i/o line peripheral a peripheral b reset state function comments pb0 lcdvsync i/o pb1 lcdhsync i/o pb2 lcddotck pck0 i/o pb3 lcdden i/o pb4 lcdcc lcdd2 i/o pb5 lcdd0 lcdd3 i/o pb6 lcdd1 lcdd4 i/o pb7 lcdd2 lcdd5 i/o pb8 lcdd3 lcdd6 i/o pb9 lcdd4 lcdd7 i/o pb10 lcdd5 lcdd10 i/o pb11 lcdd6 lcdd11 i/o pb12 lcdd7 lcdd12 i/o pb13 lcdd8 lcdd13 i/o pb14 lcdd9 lcdd14 i/o pb15 lcdd10 lcdd15 i/o pb16 lcdd11 lcdd19 i/o pb17 lcdd12 lcdd20 i/o pb18 lcdd13 lcdd21 i/o pb19 lcdd14 lcdd22 i/o pb20 lcdd15 lcdd23 i/o pb21 tf0 lcdd16 i/o pb22 tk0 lcdd17 i/o pb23 td0 lcdd18 i/o pb24 rd0 lcdd19 i/o pb25 rk0 lcdd20 i/o pb26 rf0 lcdd21 i/o pb27 spi1_npcs1 lcdd22 i/o pb28 spi1_npcs0 lcdd23 i/o pb29 spi1_spck irq2 i/o pb30 spi1_miso irq1 i/o pb31 spi1_mosi pck2 i/o 32 6062b?atarm?15-nov-05 at91sam9261 10.2.4 pio controller c multiplexing table 10-3. multiplexing on pio controller c pio controller c application usage i/o line peripheral a peripheral b reset state function comments pc0 nandoe ncs6 i/o pc1 nandwe ncs7 i/o pc2 nwait irq0 i/o pc3 a25/cfrnw a25 pc4 ncs4/cfcs0 i/o pc5 ncs5/cfcs1 i/o pc6 cfce1 i/o pc7 cfce2 i/o pc8 txd0 pck2 i/o pc9 rxd0 pck3 i/o pc10 rts0 sck0 i/o pc11 cts0 fiq i/o pc12 txd1 ncs6 i/o pc13 rxd1 ncs7 i/o pc14 txd2 spi1_npcs2 i/o pc15 rxd2 spi1_npcs3 i/o pc16 d16 tclk0 i/o pc17 d17 tclk1 i/o pc18 d18 tclk2 i/o pc19 d19 tioa0 i/o pc20 d20 tiob0 i/o pc21 d21 tioa1 i/o pc22 d22 tiob1 i/o pc23 d23 tioa2 i/o pc24 d24 tiob2 i/o pc25 d25 tf2 i/o pc26 d26 tk2 i/o pc27 d27 td2 i/o pc28 d28 rd2 i/o pc29 d29 rk2 i/o pc30 d30 rf2 i/o pc31 d31 pck1 i/o 33 6062b?atarm?15-nov-05 at91sam9261 10.3 peripheral identifiers the at91sam9261 embeds a wide range of peripherals. table 10-4 defines the periph- eral identifiers of the at91sam9261. a peripheral identifier is required for the control of the peripheral interrupt with the advanced interrupt controller and for the control of the peripheral clock with the power management controller. table 10-4. peripheral identifiers peripheral id peripheral mnemonic peripheral name external interrupt 0 aic advanced interrupt controller fiq 1 sysirq system interrupt 2 pioa parallel i/o controller a 3 piob parallel i/o controller b 4 pioc parallel i/o controller c 5-reserved 6 us0 usart 0 7 us1 usart 1 8 us2 usart 2 9 mci multimedia card interface 10 udp usb device port 11 twi two-wire interface 12 spi0 serial peripheral interface 0 13 spi1 serial peripheral interface 1 14 ssc0 synchronous serial controller 0 15 ssc1 synchronous serial controller 1 16 ssc2 synchronous serial controller 2 17 tc0 timer/counter 0 18 tc1 timer/counter 1 19 tc2 timer/counter 2 20 uhp usb host port 21 lcdc lcd controller 22 - 28 - reserved 29 aic advanced interrupt controller irq0 30 aic advanced interrupt controller irq1 31 aic advanced interrupt controller irq2 34 6062b?atarm?15-nov-05 at91sam9261 10.3.1 system interrupt the system interrupt in source 1 is the wired-or of the interrupt signals coming from: the sdram controller the debug unit the periodic interval timer the real-time timer the watchdog timer the reset controller the power management controller the clock of these peripherals cannot be deac tivated and peripheral id 1 can only be used within the advanced interrupt controller. 10.3.2 external interrupts all external interrupt signals, i.e., the fast interrupt signal fiq or the interrupt signals irq0 to irq2, use a dedicated peripheral id. however, there is no clock control associ- ated with these peripheral ids. 10.4 external bus interface integrates two external memory controllers: ? static memory controller ? sdram controller additional logic for nand flash and compactflash support ? nand flash support: 8-bit as well as 16-bit devices are supported ? compactflash support: all modes (attribute memory, common memory, i/o, true ide) are supported but the signals -iois16 (i/o and true ide modes) and -ata sel (true ide mode) are not handled. optimized external bus: ? 16- or 32-bit data bus ? up to 26-bit address bus, up to 64-mbytes addressable ? eight chip selects, each reserved to one of the eight memory areas ? optimized pin multiplexing to redu ce latencies on external memories configurable chip select assignment managed by ebi_csa register located in the matrix user interface: ? static memory controller on ncs0 ? sdram controller or static memory controller on ncs1 ? static memory controller on ncs2 ? static memory controller on ncs3, optional nand flash support ? static memory controller on ncs4 - ncs5, optional compactflash support ? static memory controller on ncs6 - ncs7 35 6062b?atarm?15-nov-05 at91sam9261 10.5 static memory controller external memory mapping, 256-mbyte address space per chip select line up to eight chip select lines 8-, 16- or 32-bit data bus multiple access modes supported ? byte write or byte select lines ? asynchronous read in page mode supported (4- up to 32-byte page size) multiple device adaptability ? compliant with lcd module ? control signal programmable setup, pulse and hold time for each memory bank multiple wait state management ? programmable wait state generation ? external wait request ? programmable data float time slow clock mode supported 10.6 sdram controller supported devices: ? standard and low power sdram (mobile sdram) numerous configurations supported ? 2k, 4k, 8k row address memory parts ? sdram with two or four internal banks ? sdram with 16- or 32-bit data path programming facilities ? word, half-word, byte access ? automatic page break when memory boundary has been reached ? multibank ping-pong access ? timing parameters specified by software ? automatic refresh operation, refresh rate is programmable energy-saving capabilities ? self-refresh, power down and deep power down modes supported error detection ? refresh error interrupt sdram power-up initialization by software cas latency of 1, 2 and 3 supported auto precharge command not used 36 6062b?atarm?15-nov-05 at91sam9261 10.7 serial peripheral interface supports communication with serial external devices ? four chip selects with external decoder support allow communication with up to fifteen peripherals ? serial memories, such as dataflash and 3-wire eeproms ? serial peripherals, such as adcs, dacs, lcd controllers, can controllers and sensors ? external co-processors master or slave serial peripheral bus interface ? 8- to 16-bit programmable data length per chip select ? programmable phase and polarity per chip select ? programmable transfer delays between consecutive transfers and between clock and data per chip select ? programmable delay between consecutive transfers ? selectable mode fault detection very fast transfers supported ? transfers with baud rates up to mck ? the chip select line may be left active to speed up transfers on the same device 10.8 two-wire interface compatibility with standard two-wire serial memory one, two or three bytes for slave address sequential read/write operations 10.9 usart programmable baud rate generator 5- to 9-bit full-duplex synchronous or asynchronous serial communications ? 1, 1.5 or 2 stop bits in asynchronous mode or 1 or 2 stop bits in synchronous mode ? parity generation and error detection ? framing error detection, overrun error detection ? msb- or lsb-first ? optional break generation and detection ? by-8 or by-16 over-sampling receiver frequency ? hardware handshaking rts-cts ? receiver time-out and transmitter timeguard ? optional multi-drop mode with address generation and detection ? optional manchester encoding rs485 with driver control signal iso7816, t = 0 or t = 1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit 37 6062b?atarm?15-nov-05 at91sam9261 irda modulation and demodulation ? communication at up to 115.2 kbps test modes ? remote loopback, local loopback, automatic echo 10.10 synchronous serial controller provides serial synchronous communication links used in audio and telecom applications (with codecs in master or slave modes, i 2 s, tdm buses, magnetic card reader and more). contains an independent receiver and transmitter and a common clock divider. offers a configurable frame sync and data length. receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal. receiver and transmitter include a data signal, a clock signal and a frame synchronization signal. 10.11 timer counter three 16-bit timer counter channels wide range of functions including: ? frequency measurement ? event counting ? interval measurement ? pulse generation ?delay timing ? pulse width modulation ? up/down capabilities each channel is user-configurable and contains: ? three external clock inputs ? five internal clock inputs ? two multi-purpose input/output signals two global registers that act on all three tc channels as mentioned above, the three timer counter channels (0 to 2) are described with five generic clock inputs, named timer_clock1 to timer_clock5. in the at91sam9261, these clock inputs are connected to the master clock (mck), to the slow clock (slck) and to divisions of the master clock. table 10-5 gives the assignment of these timer counter clock inputs in the at91sam9261, which is common to the timer counter 0 to 2. 38 6062b?atarm?15-nov-05 at91sam9261 10.12 multimedia card interface compatibility with multimedia ca rd specification version 2.2 compatibility with sd memory ca rd specification version 1.0 compatibility with sdio sp ecification version v1.0 cards clock rate up to master clock divided by 2 embedded power management to slow down clock rate when not used each mci has two slots, each supporting ? one slot for one multimedia card bus (up to 30 cards) or ? one sd memory card support for stream, block and multi-block data read and write 10.13 usb usb host port: ? compliance with open hci rev 1.0 specification ? compliance with usb v2.0 full-speed and low-speed specification ? supports both low-speed 1.5 mbps and full-speed 12 mbps usb devices ? root hub integrated with two downstream usb ports ? two embedded usb transceivers ? no overcurrent detection ? supports power management ? operates as a master on the bus matrix usb device port: ? usb v2.0 full-speed compliant, 12 mbits per second ? embedded usb v2.0 full-speed transceiver ? embedded dual-port ram for endpoints ? suspend/resume logic ? ping-pong mode (two memory banks) for isochronous and bulk endpoints. table 10-5. timer counter clock assignment tc clock input clock timer_clock1 mck/2 timer_clock2 mck/8 timer_clock3 mck/32 timer_clock4 mck/128 timer_clock5 slck 39 6062b?atarm?15-nov-05 at91sam9261 ? six general-purpose endpoints: endpoint 0: 8 bytes, no ping-pong mode endpoint 1, endpoint 2: 64 bytes, ping-pong mode endpoint 3: 64 bytes, no ping-pong mode endpoint 4, endpoint 5: 256 bytes, ping-pong mode embedded pad pull-up configurable via u sb_pucr register loca ted in the matrix user interface 10.14 lcd controller single and dual scan color and monochrome passive stn lcd panels supported single scan active tft lcd panels supported. 4-bit single scan, 8-bit single or dual scan , 16-bit dual scan stn interfaces supported up to 24-bit single scan tft interfaces supported up to 16 gray levels for mono stn and up to 4096 colors for color stn displays 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono stn 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color stn 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for tft single clock domain architecture resolution supported up to 2048 x 2048 40 6062b?atarm?15-nov-05 at91sam9261 11. arm926ej-s processor overview 11.1 overview the arm926ej-s processor is a member of the arm9 ? family of general-purpose micropro- cessors. the arm926ej-s implements arm architecture version 5tej and is targeted at multi-tasking applications where full memory management, high performance, low die size and low power are all important features. the arm926ej-s processor supports the 32-b it arm and 16-bit thumb instruction sets, enabling the user to trade off between high performance and high code density. it also sup- ports 8-bit java instruction set and includes featur es for efficient execut ion of java bytecode, providing a java performance similar to a jit (just-in-time compilers), for the next generation of java-powered wireless and embedded device s. it includes an enhanced multiplier design for improved dsp performance. the arm926ej-s processor supports the arm debug architecture and includes logic to assist in both hardware and software debug. the arm926ej-s provides a complete high performance processor subsystem, including: an arm9ej-s integer core a memory management unit (mmu) separate instruction and data amba ? ahb bus interfaces separate instruction and data tcm interfaces 41 6062b?atarm?15-nov-05 at91sam9261 11.2 block diagram figure 11-1. arm926ej-s internal functional block diagram 11.3 arm9ej-s processor 11.3.1 arm9ej-s ? operating states the arm9ej-s processor can operate in three different states, each with a specific instruction set: arm state: 32-bit, word-aligned arm instructions. thumb state: 16-bit, halfword-aligned thumb instructions. jazelle state: variable length, byte-aligned jazelle instructions. in jazelle state, all instru ction fetches are in words. 11.3.2 switching state the operating state of the arm9ej-s core can be switched between: arm state and thumb state using the bx and blx instructions, and loads to the pc arm9ej-s ice interface arm926ej-s embeddedice -rt processor etm interface coprocessor interface droute iroute iext icache mmu dcache dext ia tcm interface bus interface unit ahb ahb data ahb interface instruction ahb interface instr r data w data da 42 6062b?atarm?15-nov-05 at91sam9261 arm state and jazelle state using the bxj instruction all exceptions are entered, handled and exited in arm state. if an exception occurs in thumb or jazelle states, the processor reverts to arm state. the transi tion back to thumb or jazelle states occurs automatically on return from the exception handler. 11.3.3 instruction pipelines the arm9ej-s core uses two kinds of pipelines to increase the speed of the flow of instruc- tions to the processor. a five-stage (five clock cycles) pipeline is us ed for arm and thumb st ates. it consists of fetch, decode, execute, me mory and writeback stages. a six-stage (six clock cycles) pipeline is used for jazelle state it consists of fetch, jazelle/decode (two clock cycles), execute, memory and writeback stages. 11.3.4 memory access the arm9ej-s core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. words must be aligned to four-byte boundaries, half-words must be aligned to two-byte boundaries and bytes can be placed on any byte boundary. because of the nature of the pipelines, it is possible for a value to be required for use before it has been placed in the register bank by the actions of an earlier instruction. the arm9ej-s control logic automatically detects these cases and stalls the core or forward data. 11.3.5 jazelle technology the jazelle technology enables direct and efficient execution of java byte codes on arm pro- cessors, providing high performance for the next generation of java-powered wireless and embedded devices. the new java feature of arm9ej-s can be described as a hardware emulation of a jvm (java virtual machine). java mode will appear as another state: instead of executing arm or thumb instructions, it executes java byte codes. the java byte code decoder logic imple- mented in arm9ej-s decodes 95% of execut ed byte codes and turns them into arm instructions without any overhead, while less frequently used byte codes are broken down into optimized sequences of arm instructions. the hardw are/software split is invisible to the pro- grammer, invisible to the application and invisi ble to the operating system. all existing arm registers are re-used in jazelle state and all registers then have particular functions in this mode. minimum interrupt latency is ma intained across both arm state and java state. since byte codes execution can be restarted, an interrupt aut omatically triggers the core to switch from java state to arm state for the execution of the interrupt handler. this means that no special provision has to be made for handling interrupts while executing byte codes, whether in hard- ware or in software. 11.3.6 arm9ej-s operating modes in all states, there are seven operation modes: user mode is the usual arm program executio n state. it is used for executing most application programs fast interrupt (fiq) mode is used for handling fast interrupts. it is suitable for high-speed data transfer or channel process 43 6062b?atarm?15-nov-05 at91sam9261 interrupt (irq) mode is used for general-purpose interrupt handling supervisor mode is a protected mode for the operating system abort mode is entered after a data or instruction prefetch abort system mode is a privileged user mode for the operating system undefined mode is entered when an undefined instruction exception occurs mode changes may be made under software control, or may be brought about by external interrupts or exception processing. most application programs execute in user mode. the non-user modes, known as privileged modes, are entered in order to service interrupts or exceptions or to acce ss protected resources. 11.3.7 arm9ej-s registers the arm9ej-s core has a total of 37 registers. 31 general-purpose 32-bit registers 6 32-bit status registers table 11-1 shows all the registers in all modes. table 11-1. arm9ej-s ? modes and registers layout user and system mode supervisor mode abort mode undefined mode interrupt mode fast interrupt mode r0 r0 r0 r0 r0 r0 r1 r1 r1 r1 r1 r1 r2 r2 r2 r2 r2 r2 r3 r3 r3 r3 r3 r3 r4 r4 r4 r4 r4 r4 r5 r5 r5 r5 r5 r5 r6 r6 r6 r6 r6 r6 r7 r7 r7 r7 r7 r7 r8 r8 r8 r8 r8 r8_fiq r9 r9 r9 r9 r9 r9_fiq r10 r10 r10 r10 r10 r10_fiq r11 r11 r11 r11 r11 r11_fiq r12 r12 r12 r12 r12 r12_fiq r13 r13_svc r13_abort r13_undef r13_irq r13_fiq r14 r14_svc r14_abort r14_undef r14_irq r14_fiq pc pc pc pc pc pc cpsr cpsr cpsr cpsr cpsr cpsr 44 6062b?atarm?15-nov-05 at91sam9261 the arm state register set contains 16 directly -accessible registers, r0 to r15, and an addi- tional register, the current program status regi ster (cpsr). registers r0 to r13 are general- purpose registers used to hold either data or addr ess values. register r 14 is used as a link register that holds a value (return address) of r15 when bl or blx is executed. register r15 is used as a program counter (pc), whereas the current program status register (cpsr) con- tains condition code flags and the current mode bits. in privileged modes (fiq, supervisor, abort, irq, undefined), mode-specific banked registers (r8 to r14 in fiq mode or r13 to r14 in the other modes) become available. the corresponding banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und are similarly used to hold the val- ues (return address for each mode) of r15 (pc) when interrupts and exceptions arise, or when bl or blx instructions are executed within interrupt or exception routines. there is another register called saved program status register (spsr) that becomes available in privileged modes instead of cpsr. this register contains condition code flags and the current mode bits saved as a result of the exception that caused entry to the current (privileged) mode. in all modes and due to a software agreement, register r13 is used as stack pointer. the use and the function of all the register s described above should obey arm procedure call standard (apcs) which defines: constraints on the use of registers stack conventions argument passing and result return the thumb state register set is a subset of the arm state set. the programmer has direct access to: eight general-purpose registers r0-r7 stack pointer, sp link register, lr (arm r14) pc cpsr there are banked registers sps, lrs and spsrs for each privileged mo de (for more details see the arm9ej-s technical reference manual, ref. ddi0222b, revision r1p2 page 2-12). 11.3.7.1 status registers the arm9ej-s core contains one cpsr, and five spsrs for ex ception handlers to use. the program status registers: hold information about the most recently performed alu operation spsr_svc spsr_abo rt spsr_und ef spsr_irq spsr_fiq mode-specific banked registers table 11-1. arm9ej-s ? modes and registers layout user and system mode supervisor mode abort mode undefined mode interrupt mode fast interrupt mode 45 6062b?atarm?15-nov-05 at91sam9261 control the enabling and disabling of interrupts set the processor operation mode figure 11-2. status register format figure 11-2 shows the status register format, where: n: negative, z: zero, c: carry, and v: overflow are the four alu flags the sticky overflow (q) flag can be set by certain multiply and fractional arithmetic instructions like qadd, qdadd, qsub, qdsub, smlaxy, and smlawy needed to achieve dsp operations. the q flag is sticky in that, when set by an in struction, it re mains set until explicitly cleared by an msr instruction writing to the cpsr. instructions cannot execute conditionally on the status of the q flag. the j bit in the cpsr indicates when the ar m9ej-s core is in jazelle state, where: ? j = 0: the processor is in arm or thumb state, depending on the t bit ? j = 1: the processor is in jazelle state. mode: five bits to encode the current processor mode 11.3.7.2 exceptions exception types and priorities the arm9ej-s supports five types of exceptions. each type drives the arm9ej-s in a privi- leged mode. the types of exceptions are: fast interrupt (fiq) normal interrupt (irq) data and prefetched aborts (abort) undefined instruction (undefined) software interrupt and reset (supervisor) when an exception occurs, th e banked version of r14 and th e spsr for the exception mode are used to save the state. more than one exception can happen at a time, therefore the arm9ej-s takes the arisen exceptions according to the following priority order: reset (highest priority) data abort fiq irq nz cv q jift mode reserved mode bits thumb state bit fiq disable irq disable jazelle state bit reserved sticky overflow overflow carry/borrow/extend zero negative/less than 31 30 29 28 27 24 7 6 5 0 46 6062b?atarm?15-nov-05 at91sam9261 prefetch abort bkpt, undefined instruction, and softwa re interrupt (swi) (lowest priority) the bkpt, or undefined instruction, and swi exceptions are mutually exclusive. there is one exception in the priority scheme though, when fiqs are enabled and a data abort occurs at the same time as an fiq, the arm9ej-s core enters the data abort handler, and proceeds immediately to fiq vector. a normal return from the fiq causes the data abort handler to resume execution. data aborts must have higher priority than fiqs to ensure that the transfer error does not escape detection. exception modes and handling exceptions arise whenever the normal flow of a program must be halted temporarily, for exam- ple, to service an interrupt from a peripheral. when handling an arm exception, the arm9ej-s core performs the following operations: 1. preserves the address of the next instruction in the appropriate link register that corresponds to the new mode that has been entered. when the exception entry is from: ? arm and jazelle states, the arm9ej-s copies the address of the next instruction into lr (current pc(r15) + 4 or pc + 8 depending on the exception). ? thumb state, the arm9ej-s writes the value of the pc into lr, offset by a value (current pc + 2, pc + 4 or pc + 8 depending on the exception) that causes the program to resume from the correct place on return. 2. copies the cpsr into the appropr iate spsr. 3. forces the cpsr mode bits to a value that depends on the exception. 4. forces the pc to fetch the next instruction from the relevant exception vector. the register r13 is also banked across exception modes to provide each exception handler with private stack pointer. the arm9ej-s can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. when an exception has completed, the exception handler must move both the return value in the banked lr minu s an offset to the pc and the spsr to the cpsr. the offset value varies according to the type of exception. this action restores both pc and the cpsr. the fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the requirement for register saving which minimizes the overhead of context switching. the prefetch abort is one of the aborts that indicates that the current memory access cannot be completed. when a prefetch abort occurs, the arm9ej-s marks the prefetched instruction as invalid, but does not take the exception unt il the instruction reaches the execute stage in the pipeline. if the instruction is not executed, for example because a branch occurs while it is in the pipeline, the abort does not take place. the breakpoint (bkpt) instruction is a new feature of arm9ej-s that is destined to solve the problem of the prefetch abort. a breakpoint instruction operates as though the instruction caused a prefetch abort. a breakpoint instruction does not cause the arm9ej-s to take the prefetch abort exception until the instruction reaches the execute stage of the pipeline. if the instruction is not exe- cuted, for example because a branch occurs while it is in the pipeline, the breakpoint does not take place. 47 6062b?atarm?15-nov-05 at91sam9261 11.3.8 arm instruction set overview the arm instruction set is divided into: branch instructions data processing instructions status register transfer instructions load and store instructions coprocessor instructions exception-generating instructions arm instructions can be executed conditionally. every instruction contains a 4-bit condition code field (bits[31:28]). table 11-2 gives the arm instruction mnemonic list. table 11-2. arm instruction mnemonic list mnemonic operation mnemonic operation mov move mvn move not add add adc add with carry sub subtract sbc subtract with carry rsb reverse subtract rsc reverse subtract with carry cmp compare cmn compare negated tst test teq test equivalence and logical and bic bit clear eor logical exclusive or orr logical (inclusive) or mul multiply mla multiply accumulate smull sign long multiply umull unsigned long multiply smlal signed long multiply accumulate umlal unsigned long multiply accumulate msr move to status register mrs move from status register b branch bl branch and link bx branch and exchange swi software interrupt ldr load word str store word ldrsh load signed halfword ldrsb load signed byte ldrh load half word strh store half word ldrb load byte strb store byte ldrbt load register byte with translation strbt store register byte with tr a n s l a t i o n ldrt load register with translation strt store register with tr a n s l a t i o n ldm load multiple stm store multiple swp swap word swpb swap byte 48 6062b?atarm?15-nov-05 at91sam9261 11.3.9 new arm instruction set . notes: 1. a thumb blx contains two consecutiv e thumb instructions, and takes four cycles. 11.3.10 thumb instruction set overview the thumb instruction set is a re-encoded subset of the arm instruction set. the thumb instruction set is divided into: branch instructions data processing instructions load and store instructions load and store multiple instructions exception-generating instruction mcr move to coprocessor mrc move from coprocessor ldc load to coprocessor stc store from coprocessor cdp coprocessor data processing table 11-2. arm instruction mnemonic list (continued) mnemonic operation mnemonic operation table 11-3. new arm instruction mnemonic list mnemonic operation mnemonic operation bxj branch and exchange to java mrrc move double from coprocessor blx (1) branch, link and exchange mcr2 alternative move of arm reg to coprocessor smlaxy signed multiply accumulate 16 * 16 bit mcrr move double to coprocessor smlal signed multiply accumulate long cdp2 alternative coprocessor data processing smlawy signed multiply accumulate 32 * 16 bit bkpt breakpoint smulxy signed multiply 16 * 16 bit pld soft preload, memory prepare to load from address smulwy signed multiply 32 * 16 bit strd store double qadd saturated add stc2 alternative store from coprocessor qdadd saturated add with double ldrd load double qsub saturated subtract ldc2 alternative load to coprocessor qdsub saturated subtract with double clz count leading zeroes 49 6062b?atarm?15-nov-05 at91sam9261 table 5 shows the thumb instruction set. table 11-4 gives the thumb instruction mnemonic list. 11.4 cp15 coprocessor coprocessor 15, or system control coprocessor cp15, is used to configure and control all the items in the list below: arm9ej-s caches (icache, dcache and write buffer) tcm mmu other system options to control these features, cp15 provides 16 additional registers. see table 11-5 . table 11-4. thumb instruction mnemonic list mnemonic operation mnemonic operation mov move mvn move not add add adc add with carry sub subtract sbc subtract with carry cmp compare cmn compare negated tst test neg negate and logical and bic bit clear eor logical exclusive or or r logical (inclusive) or lsl logical shift left lsr logical shift right asr arithmetic shift right ror rotate right mul multiply blx branch, link, and exchange b branch bl branch and link bx branch and exchange swi software interrupt ldr load word str store word ldrh load half word strh store half word ldrb load byte strb store byte ldrsh load signed halfword ldrsb load signed byte ldmia load multiple stmia store multiple push push register to stack pop pop register from stack bcc conditional branch bkpt breakpoint 50 6062b?atarm?15-nov-05 at91sam9261 notes: 1. register locations 0,5, and 13 each provide access to more than one register. the register accessed depends on the value of the opcode_2 field. 2. register location 9 provides access to mo re than one register. the register accessed depends on the value of the crm field. table 11-5. cp15 registers register name read/write 0 id code (1) read/unpredictable 0 cache type (1) read/unpredictable 0 tcm status (1) read/unpredictable 1 control read/write 2 translation table base read/write 3 domain access control read/write 4 reserved none 5 data fault status (1) read/write 5 instruction fault status (1) read/write 6 fault address read/write 7 cache operations read/write 8 tlb operations unpredictable/write 9 cache lockdown (2) read/write 9 tcm region read/write 10 tlb lockdown read/write 11 reserved none 12 reserved none 13 fcse pid (1) read/write 13 context id (1) read/write 14 reserved none 15 test configuration read/write 51 6062b?atarm?15-nov-05 at91sam9261 11.4.1 cp15 registers access cp15 registers can only be accessed in privileged mode by: mcr (move to coprocessor from arm register) instruction is used to write an arm register to cp15. mrc (move to arm register from coprocessor) instruction is used to read the value of cp15 to an arm register. other instructions like cdp, ldc, stc can cause an undefined instruction exception. the assembler code for these instructions is: mcr/mrc{cond} p15, opcode_1, rd, crn, crm, opcode_2. the mcr, mrc instructions bit pattern is shown below: crm[3:0]: specified coprocessor action determines specific coprocessor action. its value is dependen t on the cp15 register used. for details, refer to cp15 spe- cific register behavior. opcode_2[7:5] determines specific coprocessor operation code. by default, set to 0. rd[15:12]: arm register defines the arm register whose value is transferred to the co processor. if r15 is chosen, the result is unpredictable. crn[19:16]: coprocessor register determines the destination coprocessor register. l: instruction bit 0 = mcr instruction 1 = mrc instruction opcode_1[23:20]: coprocessor code defines the coprocessor specific code. value is c15 for cp15. cond [31:28]: condition for more details, see chapter 2 in arm926ej-s trm, ref. ddi0198b. 31 30 29 28 27 26 25 24 cond 1110 23 22 21 20 19 18 17 16 opcode_1 l crn 15 14 13 12 11 10 9 8 rd 1111 76543210 opcode_2 1 crm 52 6062b?atarm?15-nov-05 at91sam9261 11.5 memory management unit (mmu) the arm926ej-s processor implements an enhanced arm architecture v5 mmu to provide virtual memory features required by operat ing systems like symbi an os, windowsce, and linux. these virtual memory features are memo ry access permission controls and virtual to physical address translations. the virtual address generated by the cpu core is converted to a modified virtual address (mva) by the fcse (fast context switch extension) using the value in cp15 register13. the mmu translates modified virtual addresses to ph ysical addresses by using a single, two-level page table set stored in physical memory. each entry in the set contains the access permis- sions and the physical address that correspond to the virtual address. the first level translation tables contain 4096 entries indexed by bits [31:20] of the mva. these entries contain a pointer to either a 1 mb section of physical memory along with attribute information (access permissions, domain, etc.) or an entry in the second level transla- tion tables; coarse table and fine table. the second level translation tables contain two subtables, coarse table and fine table. an entry in the coarse table contains a pointer to both large pages and small pages along with access permissions. an entry in the fine table contains a pointer to large, small and tiny pages. table 7 shows the different attributes of each page in the physical memory. the mmu consists of: access control logic translation look-aside buffer (tlb) translation table walk hardware 11.5.1 access control logic the access control logic controls access information for every entry in the translation table. the access control logic checks two pieces of access information: domain and access permis- sions. the domain is the primary access control mechanism for a memory region; there are 16 of them. it defines the conditions necessary for an access to proceed. the domain determines whether the access permissions are used to qualify the access or whether they should be ignored. the second access control mec hanism is access permissions that are defined for sections and for large, small and tiny pages. sections and tiny pages have a single set of access per- missions whereas large and small pages can be a ssociated with 4 sets of access permissions, one for each subpage (quarter of a page). table 11-6. mapping details mapping name mapping size access permission by subpage size section 1m byte section - large page 64k bytes 4 separated subpages 16k bytes small page 4k bytes 4 separated subpages 1k byte tiny page 1k byte tiny page - 53 6062b?atarm?15-nov-05 at91sam9261 11.5.2 translation look-aside buffer (tlb) the translation look-aside buffer (tlb) caches translated entries and thus avoids going through the translation process every time. when the tlb contains an entry for the mva (modified virtual address), the access control logic determines if the access is permitted and outputs the appropriate physical address corresponding to the mva. if access is not permitted, the mmu signals the cpu core to abort. if the tlb does not contain an entry for the mva, the translation table walk hardware is invoked to retrieve the translation information from the translation table in physical memory. 11.5.3 translation table walk hardware the translation table walk hardwar e is a logic that traverses t he translation tables located in physical memory, gets the ph ysical address and access permissions and updates the tlb. the number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access or a page-mapped access. there are three sizes of page-mapped accesses and one size of section-mapped access. page-mapped accesses are for large pages, small pages and tiny pages. the translation pro- cess always begins with a level one fetch. a section-mapped access requires only a level one fetch, but a page-mapped access requires an additional level two fetch. for further details on the mmu, please refer to chapter 3 in arm926ej-s technical reference manual, ref. ddi0198b. 11.5.4 mmu faults the mmu generates an abort on the following types of faults: alignment faults (for data accesses only) translation faults domain faults permission faults the access control mechanism of the mmu detects the conditions that produce these faults. if the fault is a result of memory access, the mmu aborts the access and signals the fault to the cpu core.the mmu retains status and address information about faults generated by the data accesses in the data fault status register and fault address register. it also retains the status of faults generated by instruction fetches in the instruction fault status register. the fault status register (register 5 in cp15) indicates the cause of a data or prefetch abort, and the domain number of the aborted access when it happens. the fault address register (register 6 in cp15) holds the mva associated with the access that caused the data abort. for further details on mmu faults, please refer to chapter 3 in arm926ej-s technical reference manual, ref. ddi0198b. 11.6 caches and write buffer the arm926ej-s contains a 16 kb instruction cache (icache), a 16 kb data cache (dcache), and a write buffer. although the icache and dcache share common features, each still has some specific mechanisms. the caches (icache and dcache) are four-w ay set associative, addressed, indexed and tagged using the modified virtual address (mva), with a cache line length of eight words with two dirty bits for the dcache. the icache and dcache provide mechanisms for cache lock- down, cache pollution control, and line replacement. 54 6062b?atarm?15-nov-05 at91sam9261 a new feature is now supported by arm926ej- s caches called allocate on read-miss com- monly known as wrapping. this feature enables th e caches to perform crit ical word first cache refilling. this means that when a request for a word causes a read-miss, the cache performs an ahb access. instead of loading the whole line (eight words), the cache loads the critical word first, so the processor can reach it quickly, and then the remaining words, no matter where the word is located in the line. the caches and the write buffer are controlled by the cp15 register 1 (control), cp15 register 7 (cache operations) and cp15 register 9 (cache lockdown). 11.6.1 instruction cache (icache) the icache caches fetched instru ctions to be executed by the processor. the icache can be enabled by writing 1 to i bit of the cp15 register 1 and disabled by writing 0 to this same bit. when the mmu is enabled, all instruction fetche s are subject to translation and permission checks. if the mmu is disabled, all instructions fetches are cachable, no protection checks are made and the physical address is flat-mapped to the modified virtual address. with the mva use disabled, context switching incurs icache cleaning and/or invalidating. when the icache is disabled, all instructi on fetches appear on external memory (ahb) (see tables 4-1 and 4-2 in page 4-4 in arm926ej-s trm, ref. ddi0198b). on reset, the icache entries are invalidated and the icache is disabled. for best performance, icache should be enabled as soon as possible after reset. 11.6.2 data cache (dcache) and write buffer arm926ej-s includes a dcache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance. the operations of dcache and write buffer are closely connected. 11.6.2.1 dcache the dcache needs the mmu to be enabled. all da ta accesses are subject to mmu permission and translation checks. data accesses that are aborted by the mmu do not cause linefills or data accesses to appear on the amba asb interf ace. if the mmu is disabled, all data accesses are noncachable, nonbufferable, with no protection checks, and appear on the ahb bus. all addresses are flat-mapped, va = mva = pa, which incurs dcache cleaning and/or invalidating every time a context switch occurs. the dcache stores the physical address tag ( pa tag) from which every line was loaded and uses it when writing modified lines back to external memory. this means that the mmu is not involved in write-back operations. each line (8 words) in the dcache has two dirty bits, one for the first four words and the other one for the second four words. these bits, if set, mark the associated half-lines as dirty. if the cache line is replaced due to a linefill or a ca che clean operation, the dirty bits are used to decide whether all, half or none is written back to memory. dcache can be enabled or disabled by writing either 1 or 0 to bit c in register 1 of cp15 (see tables 4-3 and 4-4 on page 4-5 in arm926ej-s trm, ref. ddi0222b). the dcache supports write-through and write-back cache operations, selected by memory region using the c and b bits in the mmu translation tables. 55 6062b?atarm?15-nov-05 at91sam9261 the dcache contains an eight data word entry, single address entry write-back buffer used to hold write-back data for cache line eviction or cleaning of dirty cache lines. the write buffer can hold up to 16 words of data and four separate addresses. dcache and write buffer operations are closely connected as their configuration is set in each section by the page descriptor in the mmu translation table. 11.6.2.2 write buffer the arm926ej-s contains a write buffer that has a 16-word data buffer and a four- address buffer. the write buffer is used for all writes to a bufferable region, write-through region and write-back region. it also allows to avoid stalling the processor when writes to ex ternal memory are performed. when a store occurs, data is written to the write buffer at core speed (high speed). the write buffer then completes the store to external memory at bus speed (typically slower than the core speed). during this time , the arm9ej-s processor can preform other tasks. dcache and write buffer support write-back and write-through memory regions, controlled by c and b bits in each section and page descriptor within the mmu translation tables. write-though operation when a cache write hit occurs, the dcache line is updated. the updated data is then written to the write buffer which transfers it to external memory. when a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. write-back operation when a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-to-date with those in the external memory. when a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 11.7 tightly-coupled memory interface 11.7.1 tcm description the arm926ej-s processor features a tightly-coupled memory (tcm) interface, which enables separate instruction and data tcms (i tcm and dtcm) to be directly reached by the processor. tcms are used to store real-time and performance critical code, they also provide a dma support mechanism. unlike ahb accesses to external memories , accesses to tcms are fast and deterministic and do not incur bus penalties. the user has the possibility to independently conf igure each tcm size with values within the following ranges, [0kb, 64 kb] for itcm size and [0kb, 64 kb] for dtcm size. tcms can be configured by two means: the bus matrix tcm register and tcm region register (register 9) in cp15 and both steps should be performed. the bus matrix tcm register sets tcm size whereas tcm region register (register 9) in cp15 maps tcms and enables them. the data side of the arm9ej-s core is able to access the itcm. this is necessary to enable code to be loaded into the itcm, for swi and emulated instruction handlers, and for accesses to pc-relative literal pools. 56 6062b?atarm?15-nov-05 at91sam9261 11.7.2 enabling and disabling tcms prior to any enabling step, the user should configure the tcm sizes in the bus matrix tcm register. then enabling tcms is performed by using tcm region register (register 9) in cp15. the user should use the same sizes as those put in the bus matrix tcm register. for further details and programming tips, please refer to chapter 2.3 in arm926ej-s trm, ref. ddi0222b. 11.7.3 tcm mapping the tcms can be located anywhere in the memory map, with a single region available for itcm and a separate region available for dt cm. the tcms are physically addressed and can be placed anywhere in physical address space. however, the base address of a tcm must be aligned to its size, and the dtcm and itcm regions must not overlap. tcm mapping is per- formed by using tcm region register (register 9) in cp15. the user should input the right mapping address for tcms. 11.8 bus interface unit the arm926ej-s features a bus interface unit (biu) that arbitrates and schedules ahb requests. the biu implements a multi-layer ahb, based on the ahb-lite protocol, that enables parallel access paths between multiple ah b masters and slaves in a system. this is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. the multi-master bus architecture has a number of benefits: it allows the development of multi-master systems with an increased bus bandwidth and a flexible architecture. each ahb layer becomes simple because it only has one master, so no arbitration or master-to-slave muxing is required. ahb layers, implementing ahb-lite protocol, do not have to support request and grant, nor do they have to support retry and split transactions. the arbitration becomes effective when more than one master wants to access the same slave simultaneously. 11.8.1 supported transfers the arm926ej-s processor performs all ahb access es as single word, bursts of four words, or bursts of eight words. any arm9ej-s core request that is not 1, 4, 8 words in size is split into packets of these sizes. note that the atmel bus is ahb-lite protocol compliant, hence it does not support split and retry requests. 57 6062b?atarm?15-nov-05 at91sam9261 table 8 gives an overview of the supported transfers and different kinds of transactions they are used for. 11.8.2 thumb instruction fetches all instructions fetches, regardless of the state of arm9ej-s core, are made as 32-bit accesses on the ahb. if the arm9ej-s is in thumb state, then two instructions can be fetched at a time. 11.8.3 address alignment the arm926ej-s biu performs address alignment checking and aligns ahb addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries. table 11-7. supported transfers hburst[2:0] description single single transfer single transfer of word, half word, or byte: data write (ncnb, ncb, wt, or wb that has missed in dcache) data read (ncnb or ncb) nc instruction fetch (prefetched and non-prefetched) page table walk read incr4 four-word incrementing burst half-line cache write-back, instruction pr efetch, if enabled. four-word burst ncnb, ncb, wt, or wb write. incr8 eight-word incrementing burst full-line cache writ e-back, eight-word burst ncnb, ncb, wt, or wb write. wrap8 eight-word wrapping burst cache linefill 58 6062b?atarm?15-nov-05 at91sam9261 12. at91sam9261 debug and test 12.1 overview the at91sam9261 featur es a number of comple mentary debug and test capabilities. a com- mon jtag/ice (in-circuit emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. an etm (embedded trace macro- cell) provides more sophisticated debug features such as address and data comparators, half- rate clock mode, counters, sequencer and fifo. the debug unit provides a two-pin uart that can be used to upload an application into internal sram. it manages the interrupt han- dling of the internal commtx and commrx signa ls that trace the activity of the debug communication channel. a set of dedicated debug and test input/output pins gives direct access to these capabilities from a pc-based test environment. 12.2 block diagram figure 12-1. debug and test block diagram 2 etm ice-rt arm9ej-s pdc dbgu pio drxd dtxd tpk0-tpk15 tps0-tps2 tsync tclk tms tck tdi jtagsel tdo tst reset and test tap: test access port boundary port ice/jtag tap arm926ej-s por rtck ntrst 59 6062b?atarm?15-nov-05 at91sam9261 12.3 application examples 12.3.1 debug environment figure 12-2 on page 59 shows a complete debug environment example. the ice/jtag inter- face is used for standard debugging functions, such as downloading code and single-stepping through the program. the trace port interface is used for tracing information. a software debugger running on a personal computer provides the user interface for configuring a trace port interface utilizing the ice/jtag interface. figure 12-2. application debug and trace environment example at91sam9261-based application board ice/jtag interface host debugger ice/jtag connector at91sam9261 terminal rs232 connector trace port interface trace connector 60 6062b?atarm?15-nov-05 at91sam9261 12.3.2 test environment figure 12-3 on page 60 shows a test environment example. test vectors are sent and inter- preted by the tester. in this example, the ?board in test? is designed using a number of jtag- compliant devices. these devi ces can be connected to form a single scan chain. figure 12-3. application test environment example 12.4 debug and test pin description tester jtag interface ice/jtag connector at91sam9261-based application board in test at91sam9261 test adaptor chip 2 chip n chip 1 table 12-1. debug and test pin list pin name function type active level reset/test nrst microcontroller reset input/output low tst test mode select input high ice and jtag tck test clock input tdi test data in input tdo test data out output tms test mode select input ntrst test reset signal input low rtck returned test clock output jtagsel jtag selection input etm tsync trace synchronization signal output tclk trace clock output tps0 - tps2 trace arm pipeline status output tpk0 - tpk15 trace packet port output 61 6062b?atarm?15-nov-05 at91sam9261 12.5 functional description 12.5.1 test pin one dedicated pin, tst, is used to define the device operating mode. the user must make sure that this pin is tied at low level to ensure normal operating conditions. other values asso- ciated with this pin are reserved for manufacturing test. 12.5.2 embedded in-circuit emulator the arm9ej-s embedded in-circuit emulator-rt is supported via the ice/jtag port. it is connected to a host computer via an ice in terface. debug support is implemented using an arm9ej-s core embedded within the arm926ej-s. the internal state of the arm926ej-s is examined through an ice/jtag port which allows instructions to be serially inserted into the pipeline of the core without using the external data bus. therefore, when in debug state, a store-multiple (stm) can be inse rted into the instruction pipeline. this exports the contents of the arm9ej-s registers. this data can be seria lly shifted out without affecting the rest of the system. there are two scan chains inside the arm9ej-s processor which support testing, debugging, and programming of the embedded ice-rt. the sc an chains are controlled by the ice/jtag port. embedded ice mode is selected when jtagsel is low. it is not possible to switch directly between ice and jtag operations. a chip reset must be performed after jtagsel is changed. for further details on the embedded in-circuit-emulator-rt, see the arm document: arm9ej-s technical reference manual ( ddi 0222a ). 12.5.3 debug unit the debug unit provides a two-pin (dxrd and txrd) usart that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. moreover, the association with two peripheral dma controller channels permits packet handling of these tasks with processor time reduced to a minimum. the debug unit also manages the interrupt handling of the commtx and commrx signals that come from the ice and that trace the activity of the debug communication channel.the debug unit allows blockage of access to the system through the ice interface. a specific register, the debug unit chip id register, gives information about the product ver- sion and its internal configuration. the at91sam9261 debug unit chip id value is 0x0197 03a0 on 32-bit width. 12.5.4 embedded trace macrocell the at91sam9261 features an embedded trace macrocell (etm), which is closely con- nected to the arm926ej-s processor. the embedded trace is a standard medium+ level implementation and contains the following resources: debug unit drxd debug receive data input dtxd debug transmit data output table 12-1. debug and test pin list 62 6062b?atarm?15-nov-05 at91sam9261 four pairs of address comparators two data comparators eight memory map decoder inputs two 16-bit counters one 3-stage sequencer four external inputs one external output one 45-byte fifo the embedded trace macrocell of the at91sam9261 works in half-rate clock mode and thus integrates a clock divider. thus the maximu m frequency of all the trace port signals does not exceed one half of the arm926ej-s clock speed. the embedded trace macrocell input and output resources are not used in the at91sam9261. the embedded trace is a real-time trace module with the capability of tracing the arm9ej-s instructions and data. for further details on embedded trace macrocell, see the arm documents: etm9 (rev2p2) technical reference manual ( ddi 0157f ) embedded trace macrocell specification (ihi 0014j) 12.5.4.1 trace port the trace port is made up of the following pins: tsync - the synchronization signal (indicates the start of a branch sequence on the trace packet port.) tclk - the trace port clock, half-rate of the arm926ej-s processor clock. tps0 to tps2 - indicate the processor state at each trace clock edge. tpk0 to tpk15 - the trace packet data value. the trace packet information (address, data) is associated with the processor state indicated by tps. some processor states have no additional data associated with the trace packet port (i.e., failed condition code of an instruction). th e packet is 8 bits wide, and up to two packets can be output per cycle. 63 6062b?atarm?15-nov-05 at91sam9261 figure 12-4. etm9 block 12.5.4.2 implementation details this section gives an overview of the embedded trace resources. three-state sequencer the sequencer has three possible next states (one dedicated to itself and two others) and can change on every clock cycle. the state transition is controlled with internal events. if the user needs multiple-stage trigger schemes, the trigger event is based on a sequencer state. address comparator in single mode, address comparators compare either the instruction address or the data address against the user-programmed address. in range mode, the address comparators are arranged in pairs to form a virtual address range resource. details of the address comparator programming are: the first comparator is programmed with the range start address. the second comparator is programmed with the range end address. the resource matches if the address is within the following range: ? (address > = range start address) and (address < range end address) unpredictable behavior occurs if the two address comparators are not configured in the same way. data comparator each full address comparator is associated with a specific data comparator. a data compara- tor is used to observe the data bus only when load and store operations occur. a data comparator has both a value register and a mask register, therefore it is possible to compare only certain bits of a preprogrammed value against the data bus. arm926ej-s bus tracker tms tck tdi tdo scan chain 6 tap controller trace control trigger, sequencer, counters fifo trace enable, view data tps-tps0 tpk15-tpk0 tsync etm9 64 6062b?atarm?15-nov-05 at91sam9261 memory decoder inputs the eight memory map decoder inputs are connected to custom address decoders. the address decoders divide the memory into regi ons of on-chip sram, on-chip rom, and periph- erals. the address decoders also optimize the etm9 trace trigger. fifo a 45-byte fifo is used to store data tracing. the fifo is used to separate the pipeline status from the trace packet, thus the fifo can be used to buffer trace packets. a fifo overflow is detected by the embedded trace macrocell when the fifo is full or when the fifo has fewer bytes than the user-programmed number. half-rate clocking mode the etm9 is implemented in half-rate mode that allows both rising and falling edge data trac- ing of the trace clock. the half-rate mode is implemented to maintain the signal clock integrity of high-speed sys- tems (up to 100 mhz). figure 12-5. half-rate clocking mode care must be taken on the choice of the trace capture system as it needs to support half-rate clock functionality. table 12-2. etm memory map inputs layout product resource area access type start address end address sram internal data 0x0000 0000 0x002f ffff sram internal fetch 0x0000 0000 0x002f ffff rom internal data 0x0040 0000 0x004f ffff rom internal fetch 0x0040 0000 0x004f ffff external bus interface external data 0x1000 0000 0x8fff ffff external bus interface external fetch 0x1000 0000 0x8fff ffff user peripherals internal data 0xf000 0000 0xffff bfff system peripherals internal data 0xffff c000 0xffff ffff half-rate clocking mode trace clock tracedata arm926ej-s clock 65 6062b?atarm?15-nov-05 at91sam9261 12.5.4.3 application board restriction the tclk signal needs to be set with ca re, some timing parameters are required. the specified target system connec tor is the amp mictor connector. the connector must be oriented on the application board as shown in figure 12-6 . the view of the pcb is shown from above with the trace connector mounted near the edge of the board. this allows the trace port analyzer to mini mize the physical intrusiveness of the intercon- nected target. figure 12-6. amp mictor connector orientation 12.5.5 ieee 1149.1 jtag boundary scan ieee 1149.1 jtag boundary scan allows pin-level access independent of the device packag- ing technology. ieee 1149.1 jtag boundary scan is enabled when jtagsel is high. the sample, extest and bypass functions are implement ed. in ice debug mode, the arm processor responds with a non-jtag chip id that identifies the processor to the ice system. this is not ieee 1149.1 jtag-compliant. it is not possible to switch directly between jtag and ice operations. a chip reset must be performed after jtagsel is changed. a boundary-scan descriptor language (bsdl) file is provided to set up test. 12.5.5.1 jtag boundary-scan register the boundary-scan register (bsr) contains 484 bi ts that correspond to active pins and asso- ciated control signals. each at91sam9261 input/output pin corresponds to a 3-bit register in the bsr. the out- put bit contains data that can be forced on th e pad. the input bit fac ilitates the observability of data applied to the pad. the control bit selects the direction of the pad. 38 37 2 1 pin 1chamfer at91sam9261-based application board table 12-3. at91sam9261 jtag boundary scan register bit number pin name pin type associated bsr cells 483 pc23 in/out input 482 output 481 control 480 internal 66 6062b?atarm?15-nov-05 at91sam9261 479 pc24 in/out input 478 output 477 control 476 internal 475 pc25 in/out input 474 output 473 control 472 internal 471 pc26 in/out input 470 output 469 control 468 internal 467 pc27 in/out input 466 output 465 control 464 internal 463 pc28 in/out input 462 output 461 control 460 internal 459 pc29 in/out input 458 output 457 control 456 internal 455 pc0 in/out input 454 output 453 control 452 internal 451 pc1 in/out input 450 output 449 control 448 internal 447 pc2 in/out input 446 output 445 control 444 internal table 12-3. at91sam9261 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells 67 6062b?atarm?15-nov-05 at91sam9261 443 pc3 in/out input 442 output 441 control 440 internal 439 pc4 in/out input 438 output 437 control 436 internal 435 pc5 in/out input 434 output 433 control 432 internal 431 pc6 in/out input 430 output 429 control 428 internal 427 pc7 in/out input 426 output 425 control 424 internal 423 pc8 in/out input 422 output 421 control 420 internal 419 pc9 in/out input 418 output 417 control 416 internal 415 pc10 in/out input 414 output 413 control 412 internal 411 pc11 in/out input 410 output 409 control 408 internal table 12-3. at91sam9261 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells 68 6062b?atarm?15-nov-05 at91sam9261 407 pc12 in/out input 406 output 405 control 404 internal 403 pc13 in/out input 402 output 401 control 400 internal 399 pc14 in/out input 398 output 397 control 396 internal 395 pc15 in/out input 394 output 393 control 392 internal 391 pa 0 i n / o u t input 390 output 389 control 388 internal 387 pa 1 i n / o u t input 386 output 385 control 384 internal 383 pa 2 i n / o u t input 382 output 381 control 380 internal 379 pa 3 i n / o u t input 378 output 377 control 376 internal 375 pa 4 i n / o u t input 374 output 373 control 372 internal table 12-3. at91sam9261 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells 69 6062b?atarm?15-nov-05 at91sam9261 371 pa 5 i n / o u t input 370 output 369 control 368 internal 367 pa 6 i n / o u t input 366 output 365 control 364 internal 363 pa 7 i n / o u t input 362 output 361 control 360 internal 359 pa 1 2 i n / o u t input 358 output 357 control 356 internal 355 pa 8 i n / o u t input 354 output 353 control 352 internal 351 pa 9 i n / o u t input 350 output 349 control 348 internal 347 pa 1 0 i n / o u t input 346 output 345 control 344 internal 343 pa 1 1 i n / o u t input 342 output 341 control 340 internal 339 pa 1 3 i n / o u t input 338 output 337 control 336 internal table 12-3. at91sam9261 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells 70 6062b?atarm?15-nov-05 at91sam9261 335 pa 1 4 i n / o u t input 334 output 333 control 332 internal 331 pa 1 5 i n / o u t input 330 output 329 control 328 internal 327 pa 1 6 i n / o u t input 326 output 325 control 324 internal 323 pa 1 7 i n / o u t input 322 output 321 control 320 internal 319 pa 1 8 i n / o u t input 318 output 317 control 316 internal 315 pa 1 9 i n / o u t input 314 output 313 control 312 internal 311 pa 2 0 i n / o u t input 310 output 309 control 308 internal 307 pa 2 1 i n / o u t input 306 output 305 control 304 internal 303 pa 2 2 i n / o u t input 302 output 301 control 300 internal table 12-3. at91sam9261 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells 71 6062b?atarm?15-nov-05 at91sam9261 299 pa 2 3 i n / o u t input 298 output 297 control 296 internal 295 pa 2 4 i n / o u t input 294 output 293 control 292 internal 291 pa 2 5 i n / o u t input 290 output 289 control 288 internal 287 pa 2 6 i n / o u t input 286 output 285 control 284 internal 283 pa 2 7 i n / o u t input 282 output 281 control 280 internal 279 pa 2 8 i n / o u t input 278 output 277 control 276 internal 275 pa 2 9 i n / o u t input 274 output 273 control 272 internal 271 pa 3 0 i n / o u t input 270 output 269 control 268 internal 267 pa 3 1 i n / o u t input 266 output 265 control 264 internal table 12-3. at91sam9261 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells 72 6062b?atarm?15-nov-05 at91sam9261 263 pb0 in/out input 262 output 261 control 260 internal 259 pb1 in/out input 258 output 257 control 256 internal 255 pb2 in/out input 254 output 253 control 252 internal 251 pb3 in/out input 250 output 249 control 248 internal 247 pb4 in/out input 246 output 245 control 244 internal 243 pb5 in/out input 242 output 241 control 240 internal 239 pb6 in/out input 238 output 237 control 236 internal 235 pb7 in/out input 234 output 233 control 232 internal 231 pb8 in/out input 230 output 229 control 228 internal table 12-3. at91sam9261 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells 73 6062b?atarm?15-nov-05 at91sam9261 227 pb9 in/out input 226 output 225 control 224 internal 223 pb10 in/out input 222 output 221 control 220 internal 219 pb11 in/out input 218 output 217 control 216 internal 215 pb12 in/out input 214 output 213 control 212 internal 211 pb13 in/out input 210 output 209 control 208 internal 207 pb14 in/out input 206 output 205 control 204 internal 203 pb15 in/out input 202 output 201 control 200 internal 199 pb16 in/out input 198 output 197 control 196 internal 195 pb17 in/out input 194 output 193 control 192 internal table 12-3. at91sam9261 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells 74 6062b?atarm?15-nov-05 at91sam9261 191 pb18 in/out input 190 output 189 control 188 internal 187 pb19 in/out input 186 output 185 control 184 internal 183 pb20 in/out input 182 output 181 control 180 internal 179 pb21 in/out input 178 output 177 control 176 internal 175 pb22 in/out input 174 output 173 control 172 internal 171 pb23 in/out input 170 output 169 control 168 internal 167 pb24 in/out input 166 output 165 control 164 internal 163 pb25 in/out input 162 output 161 control 160 internal 159 pb26 in/out input 158 output 157 control 156 internal table 12-3. at91sam9261 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells 75 6062b?atarm?15-nov-05 at91sam9261 155 pb27 in/out input 154 output 153 control 152 internal 151 pb28 in/out input 150 output 149 control 148 internal 147 pb29 in/out input 146 output 145 control 144 internal 143 pb30 in/out input 142 output 141 control 140 internal 139 pb31 in/out input 138 output 137 control 136 internal 135 a0/nbs0 out output 134 a[7:0] control 133 internal 132 a1/nbs2/nwr2 out output 131 a2 out output 130 a3 out output 129 a4 out output 128 a5 out output 127 a6 out output 126 a7 out output 125 a8 out output 124 a[15:8] control 123 a9 out output 122 a10 out output 121 sda10 in/out output table 12-3. at91sam9261 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells 76 6062b?atarm?15-nov-05 at91sam9261 120 sda10/sdramcke ras/cas/sdwe control 119 a11 out output 118 a12 out output 117 a13 out output 116 a14 out output 115 a15 out output 114 a16 out output 113 a[22:16] control 112 a17 out output 111 a18 out output 110 a19 out output 109 a20 out output 108 a21 out output 107 a22 out output 106 ncs0 out output 105 ncs0/ncs1/ncs2/ncs3 nrd/nwr0/nwr1/nwr3 control 104 ncs1/ndcs out output 103 ncs2 out output 102 ncs3/nandcs out output 101 nrd/cfoe out output 100 nwr0/nwe/cfwe in/out input 99 output 98 nwr1/nbs1/cfior in/out input 97 output 96 internal 95 nwr3/nbs3/cfiow out output 94 sdramcke out output 93 sdramclk in/out input 92 output 91 control 90 ras out output 89 cas out output 88 sdwe out output table 12-3. at91sam9261 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells 77 6062b?atarm?15-nov-05 at91sam9261 87 d0 in/out input 86 output 85 control 84 internal 83 d1 in/out input 82 output 81 control 80 d2 in/out input 79 output 78 control 77 d3 in/out input 76 output 75 control 74 d4 in/out input 73 output 72 control 71 internal 70 d5 in/out input 69 output 68 control 67 d6 in/out input 66 output 65 control 64 d7 in/out input 63 output 62 control 61 d8 in/out input 60 output 59 control 58 internal 57 d9 in/out input 56 output 55 control 54 d10 in/out input 53 output 52 control table 12-3. at91sam9261 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells 78 6062b?atarm?15-nov-05 at91sam9261 51 d11 in/out input 50 output 49 control 48 d12 in/out input 47 output 46 control 45 internal 44 d13 in/out input 43 output 42 control 41 d14 in/out input 40 output 39 control 38 d15 in/out input 37 output 36 control 35 pc16 in/out input 34 output 33 control 32 internal 31 pc17 in/out input 30 output 29 control 28 internal 27 pc18 in/out input 26 output 25 control 24 internal 23 pc19 in/out input 22 output 21 control 20 internal 19 pc30 in/out input 18 output 17 control 16 internal table 12-3. at91sam9261 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells 79 6062b?atarm?15-nov-05 at91sam9261 15 pc31 in/out input 14 output 13 control 12 internal 11 pc20 in/out input 10 output 09 control 08 internal 07 pc21 in/out input 06 output 05 control 04 internal 03 pc22 in/out input 02 output 01 control 00 internal table 12-3. at91sam9261 jtag boundary scan register (continued) bit number pin name pin type associated bsr cells 80 6062b?atarm?15-nov-05 at91sam9261 12.5.6 id code register access : read-only version[31:28]: product version number set to 0x0. part number[27:12]: product part number product part number is 0x5b08 manufacturer identity[11:1] set to 0x01f. bit[0] required by ieee std. 1149.1. set to 0x1. jtag id code value is 0x05b0_803f. 31 30 29 28 27 26 25 24 version part number 23 22 21 20 19 18 17 16 part number 15 14 13 12 11 10 9 8 part number manufacturer identity 76543210 manufacturer identity 1 81 6062b?atarm?15-nov-05 at91sam9261 13. at91sam boot program 13.1 description the boot program integrates different programs permitting download and/or upload into the different memories of the product. first, it initializes the debug unit serial port (dbgu) and the usb device port. then the dataflash ? boot program is executed. it looks for a sequence of eight valid arm exception vectors in a dataflash connected to the spi. all these vectors must be b-branch or ldr load register instructions except for the sixth vector. this vector is used to store the size of the image to download. if a valid sequence is found, co de is downloaded into the intern al sram. this is followed by a remap and a jump to the first address of the sram. if no valid arm vector sequence is found, sam-ba ? boot is then executed. it waits for trans- actions either on the usb device, or on the dbgu serial port. 13.2 flow diagram the boot program implements the algorithm in figure 13-1 . figure 13-1. boot program algorithm flow diagram timeout 1 s device setup spi dataflash boot download from dataflash character(s) received on dbgu run run sam-ba boot run sam-ba boot or ye s dataflash boot sam-ba boot usb enumeration successful no 82 6062b?atarm?15-nov-05 at91sam9261 13.3 device initialization initialization follows the steps described below: 1. stack setup for arm supervisor mode 2. main oscillator frequency detection 3. c variable initialization 4. pll setup: pllb is initialized to generate a 48 mhz clock necessary to use the usb device. a register located in the power management controller (pmc) determines the frequency of the main oscillator and thus the correct fact or for the pllb. table 13-1 defines the crystals supported by the dataflash boot program. 5. initialization of the dbgu serial port (115200 bauds, 8, n, 1) 6. disable the watchdog and enable the user reset 7. initialization of the usb device port 8. jump to dataflash boot sequence if dataflash boot fails: 9. activation of the instruction cache 10. jump to sam-ba boot sequence 13.4 dataflash boot the dataflash boot program searches for a valid application in the spi dataflash memory. if a valid application is found, this application is loaded into internal sram and executed by branching at address 0x0000_0000 after remap. th is application may be the application code or a second-level bootloader. all the calls to functions are pc relative and do not use absolute addresses. figure 13-2. remap action after download completion table 13-1. crystals supported by software auto-detection (mhz) 3.0 3.2768 3.6864 3.84 4.0 4.433619 4.608 4.9152 5.0 5.24288 6.0 6.144 6.4 6.5536 7.159090 7.3728 7.864320 8.0 9.8304 10.0 11.05920 12.0 12.288 13.56 14.31818 14.7456 16.0 17.734470 18.432 20.0 remap internal rom internal sram internal sram internal rom 0x0030_0000 0x0000_0000 0x0040_0000 0x0000_0000 83 6062b?atarm?15-nov-05 at91sam9261 after reset, the code in internal rom is mapped at both addresses 0x0000_0000 and 0x0040_0000: 400000 ea000006 b 0x20 00 ea000006 b 0x20 400004 eafffffe b 0x04 04 eafffffe b 0x04 400008 ea00002f b _main 08 ea00002f b _main 40000c eafffffe b 0x0c 0c eafffffe b 0x0c 400010 eafffffe b 0x10 10 eafffffe b 0x10 400014 eafffffe b 0x14 14 eafffffe b 0x14 400018 eafffffe b 0x18 18 eafffffe b 0x18 40001c eafffffe b 0x1c 1c eafffffe b 0x1c 13.4.1 valid image detection the dataflash boot software looks for a valid application by analyzing the first 32 bytes corre- sponding to the arm exception vectors. these bytes must implement arm instructions for either branch or load pc with pc relative addressing. the sixth vector, at offset 0x14, contains the size of the image to download. the user must replace this vector with his own vector (see ?structure of arm vector 6? on page 83 ). figure 13-3. ldr opcode figure 13-4. b opcode unconditional instruction: 0xe for bits 31 to 28 load pc with pc relative addressing instruction: ? rn = rd = pc = 0xf ?i==1 ?p==1 ? u offset added (u==1) or subtracted (u==0) ?w==1 13.4.2 structure of arm vector 6 the arm exception vector 6 is used to store information needed by the dataflash boot program. figure 13-5. structure of the arm vector 6 31 28 27 24 23 20 19 16 15 12 11 0 111011 ipu1w0 rn rd 31 28 27 24 23 0 1 1 1 0 1 0 1 0 offset (24 bits) 31 0 size of the code to download in bytes 84 6062b?atarm?15-nov-05 at91sam9261 13.4.2.1 example an example of valid vectors follows: 00 ea000006 b 0x20 04 eafffffe b 0x04 08 ea00002f b _main 0c eafffffe b 0x0c 10 eafffffe b 0x10 14 00001234 <- code size = 4660 bytes 18 eafffffe b 0x18 1c eafffffe b 0x1c the size of the image to load into sram is cont ained in the location of the sixth arm vector. thus the user must replace this vector by the correct vector for his application. 13.4.3 dataflash boot sequence the dataflash boot program performs device initialization followed by the download procedure. the dataflash boot program supports all atmel dataflash devices. table 13-2 summarizes the parameters to include in the arm vector 6 for all devices. the dataflash has a status register that determines all the parameters required to access the device. the dataflash boot is configured to be compatible with the future design of the dataflash. table 13-2. dataflash device device density page size (bytes) number of pages at45db011b 1 mbit 264 512 at45db021b 2 mbits 264 1024 at45db041b 4 mbits 264 2048 at45db081b 8 mbits 264 4096 at45db161b 16 mbits 528 4096 at45db321b 32 mbits 528 8192 at45db642 64 mbits 1056 8192 85 6062b?atarm?15-nov-05 at91sam9261 figure 13-6. serial dataflash download 13.5 sam-ba boot if no valid dataflash device has been found during the dataflash boot sequence, the sam- ba boot program is performed. the sam-ba boot principle is to: ? wait for usb device enumeration ? in parallel, wait for character(s) received on the dbgu end read the first 8 instructions (32 bytes). decode the sixth arm vector ye s read the dataflash into the internal sram. (code size to read in vector 6) restore the reset value for the peripherals. set the pc to 0 and perform the remap to jump to the downloaded application send status command 8 vectors (except vector 6) are ldr or branch instruction ye s start is status ok ? sam-ba boot executed no no 86 6062b?atarm?15-nov-05 at91sam9261 ? once the communication interface is identified, the application runs in an infinite loop waiting for different commands as in table 13-3 . write commands: write a byte ( o ), a halfword ( h ) or a word ( w ) to the target. ? address : address in hexadecimal. ? value : byte, halfword or word to write in hexadecimal. ? output : ?>?. read commands: read a byte ( o ), a halfword ( h ) or a word ( w ) from the target. ? address : address in hexadecimal ? output : the byte, halfword or word read in hexadecimal following by ?>? send a file ( s ): send a file to a specified address ? address : address in hexadecimal ? output : ?>?. note: there is a time-out on this command which is reached when the prompt ?>? appears before the end of the command execution. receive a file ( r ): receive data into a file from a specified address ? address : address in hexadecimal ? nbofbytes : number of bytes in hexadecimal to receive ? output : ?>? go ( g ): jump to a specified address and execute the code ? address : address to jump in hexadecimal ? output : ?>? get version ( v ): return the sam-ba boot version ? output : ?>? 13.5.1 dbgu serial port communication is performed through the dbgu serial port initialized to 115200 baud, 8, n, 1. the send and receive file commands use the xmodem protocol to communicate. any termi- nal performing this protocol can be used to send t he application file to the target. the size of table 13-3. commands available through the sam-ba boot command action argument(s) example o write a byte address, value# o 200001,ca# o read a byte address,# o 200001,# h write a half word address, value# h 200002,cafe# h read a half word address,# h 200002,# w write a word address, value# w 200000,cafedeca# w read a word address,# w 200000,# s send a file address,# s 200000,# r receive a file address, nbofbytes# r 200000,1234# g go address# g 200200# v display version no argument v # 87 6062b?atarm?15-nov-05 at91sam9261 the binary file to send depends on the sram size embedded in the product. in all cases, the size of the binary file must be lower than the sram size because the xmodem protocol requires some sram memory to work. 13.5.2 xmodem protocol the xmodem protocol supported is the 128-byte l ength block. this protocol uses a two-char- acter crc-16 to guar antee detectio n of a maximum bit error. xmodem protocol with crc is accurate provided both sender and receiver report successful transmission. each block of the transfer looks like: 88 6062b?atarm?15-nov-05 at91sam9261 the vendor id is atmel?s vendor id 0x03eb. th e product id is 0x6124 . these references are used by the host operating system to mount the correct driver. on windows systems, the inf files contain the correspondence between vendor id and product id. atmel provides an inf example to see the devi ce as a new serial port and also provides another custom driver used by the sam-ba app lication: atm6124.sys. refer to the document ?usb basic application?, literature number 6123, for more details. 13.5.3.1 enumeration process the usb protocol is a master/slave protocol. this is the host that starts the enumeration send- ing requests to the device through the control endpoint. the device handles standard requests as defined in the usb specification. the device also handles some class requests defined in the cdc class. unhandled requests are stalled. 13.5.3.2 communication endpoints there are two communication endpoints and endpoint 0 is used for the enumeration process. endpoint 1 is a 64-byte bulk out endpoint an d endpoint 2 is a 64-byte bulk in endpoint. sam-ba boot commands are sent by the host through the endpoint 1. if required, the mes- sage is split by the host into several data payloads by the host driver. if the command requires a response, the host can send in transactions to pick up the response. table 13-4. handled standard requests request definition get_descriptor returns the current device configuration value. set_address sets the device address for all future device access. set_configuration sets the device configuration. get_configuration returns the curr ent device configuration value. get_status returns status for the specified recipient. set_feature used to set or enable a specific feature. clear_feature used to clear or disable a specific feature. table 13-5. handled class requests request definition set_line_coding configures dte rate, stop bits, parity and number of character bits. get_line_coding requests current dte rate, stop bits, parity and number of character bits. set_control_line_state rs-232 signal used to tell the dce device the dte device is now present. 89 6062b?atarm?15-nov-05 at91sam9261 13.6 hardware and software constraints the dataflash downloaded code size must be inferior to 156k bytes. the code is always downloaded from the device address 0x0000_0000 to the address 0x0000_0000 of the internal sram (after remap). the downloaded code must be position-independent or linked at address 0x0000_0000. sam-ba boot uses a block of internal sram for variables and stacks. the remaining available size for the user code is 156k bytes. this user area extends from address 0x0030_0000 to address 0x0032_6fff. the dataflash must be connected to npcs0 of the spi. the spi drivers use several pios in alternate functions to communicate with devices. care must be taken when these pios are used by the application. the devices connected could be unintentionally driven at boot time, and electrical conflicts between spi output pins and the connected devices may appear. to assure correct functionality, it is recommended to plug in critical devices to other pins. table 13-6 contains a list of pins that are driven during the boot program execution. these pins are driven during the boot sequence for a pe riod of less than 1 s if no correct boot pro- gram is found. for the dataflash driven by the spck signal at 8 mhz, the time to download 156k bytes is reduced to 200 ms. before performing the jump to the application in internal sram, all the pios and peripherals used in the boot program are set to their reset state. table 13-6. pins driven during boot program execution peripheral pin pio line spi0 mosi pa1 spi0 miso pa0 spi0 spck pa2 spi0 npcs0 pa3 dbgu drxd pa9 dbgu dtxd pa10 90 6062b?atarm?15-nov-05 at91sam9261 14. reset controller (rstc) 14.1 description the reset controller (rstc), based on power-on reset cells, handles all the resets of the sys- tem without any external components. it reports which reset occurred last. the reset controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 14.2 block diagram figure 14-1. reset controller block diagram 14.3 functional description 14.3.1 reset controller overview the reset controller is made up of an nrst manager, a startup counter and a reset state manager. it runs at slow clock and generates the following reset signals: proc_nreset: processor reset line. it also resets the watchdog timer. backup_nreset: affects all the peripherals powered by vddbu. periph_nreset: affects the whole set of embedded peripherals. nrst_out: drives the nrst pin. these reset signals are asserted by the reset controller, either on external events or on soft- ware action. the reset state manager controls th e generation of reset signals and provides a signal to the nrst manager when an assertion of the nrst pin is required. the nrst manager sha pes the nrst assertion during a pr ogrammable time, thus controlling external device resets. nrst startup counter proc_nreset wd_fault periph_nreset backup_nreset slck reset state manager reset controller rstc_irq nrst manager exter_nreset nrst_out main supply por ice_nreset wdrproc user_reset backup supply por 91 6062b?atarm?15-nov-05 at91sam9261 the reset controller mode register (rstc_mr), allowing the configuration of the reset con- troller, is powered with vddbu, so that its configuration is saved as long as vddbu is on. 14.3.2 nrst manager the nrst manager samples the nrst input pin and drives this pin low when required by the reset state manager. figure 14-2 shows the block diagram of the nrst manager. figure 14-2. nrst manager 14.3.2.1 nrst signal or interrupt the nrst manager samples the nrst pin at slow clock speed. when the line is detected low, a user reset is reported to the reset state manager. however, the nrst manager can be programmed to not trigger a reset when an assertion of nrst occurs. writing the bit ursten at 0 in rstc_mr disables the user reset trigger. the level of the pin nrst can be read at any time in the bit nrstl (nrst level) in rstc_sr. as soon as the pin nrst is asserted, the bit ursts in rstc_sr is set. this bit clears only when rstc_sr is read. the reset controller can also be programmed to generate an interrupt instead of generating a reset. to do so, the bit urstien in rstc_mr must be written at 1. 14.3.2.2 nrst external reset control the reset state manager asserts the signal ext_nreset to assert the nrst pin. when this occurs, the ?nrst_out? signal is driven low by the nrst manager for a time programmed by the field erstl in rstc_mr. this assertio n duration, named external_reset_length, lasts 2 (erstl+1) slow clock cycles. this gives the approximate duration of an assertion between 60 s and 2 seconds. note that erstl at 0 defines a two-cycle duration for the nrst pulse. this feature allows the reset controller to shape the nrst pin level, and thus to guarantee that the nrst line is driven low for a time co mpliant with potential external devices connected on the system reset. as the field is within rstc_mr, which is bac ked-up, this field can be used to shape the sys- tem power-up reset for devices r equiring a longer star tup time than the sl ow clock oscillator. external reset timer ursts ursten erstl exter_nreset urstien rstc_mr rstc_mr rstc_mr rstc_sr nrstl nrst_out nrst rstc_irq other interrupt sources user_reset 92 6062b?atarm?15-nov-05 at91sam9261 14.3.3 reset states the reset state manager handles the different reset sources and generates the internal reset signals. it reports the reset status in the field rsttyp of the status register (rstc_sr). the update of the field rsttyp is performed when the processor reset is released. 14.3.3.1 general reset a general reset occurs when vd dbu is powered on. the backup supply por cell output rises and is filtered with a startup counter, which o perates at slow clock. the purpose of this counter is to make sure the slow clock oscillator is stable before starting up the device. the length of startup time is hardcoded to comply with the slow clock oscillator startup time. after this time, the processor clock is released at slow clock and all the other signals remains valid for 2 cycles for proper processor and logic reset. then, all the reset signals are released and the field rsttyp in rstc_sr reports a general reset. as the rstc_mr is reset, the nrst line rises 2 cycles after the backup_nreset, as erstl defaults at value 0x0. when vddbu is detected low by the backup supp ly por cell, all resets signals are immedi- ately asserted, even if the main supply por cell does not report a main supply shut down. figure 14-3 shows how the general reset affects the reset signals. figure 14-3. general reset state slck periph_nreset proc_nreset backup supply por output nrst (nrst_out) external reset length = 2 cycles startup time mck processor startup = 3 cycles backup_nreset any freq. rsttyp xxx 0x0 = general reset xxx 93 6062b?atarm?15-nov-05 at91sam9261 14.3.3.2 wake-up reset the wake-up reset occurs when the main supply is down. when the main supply por out- put is active, all the reset signals are assert ed except backup_nreset. when the main supply powers up, the por output is resynchronized on slow clock. the processor clock is then re- enabled during 2 slow clock cycles, dependi ng on the requirements of the arm processor. at the end of this delay, the processor and other reset signals rise. the field rsttyp in rstc_sr is updated to report a wake-up reset. the ?nrst_out? remains asserted for exter nal_reset_length cycles. as rstc_mr is backed-up, the programmed number of cycles is applicable. when the main supply is detected falling, the reset signals are immediately asserted. this transition is synchronous with the output of the main supply por. figure 14-4. wake-up state 14.3.3.3 user reset the user reset is entered when a low level is detected on the nrst pin and the bit ursten in rstc_mr is at 1. the nrst input signal is resynchronized with slck to insure proper behavior of the system. the user reset is entered as soon as a low le vel is detected on nrst. the processor reset and the peripheral reset are asserted. the user reset is left when nrst rises, afte r a two-cycle resynchroniz ation time and a three- cycle processor startup. the processor clock is re-enabled as soon as nrst is confirmed high. when the processor reset signal is released, the rsttyp field of the status register (rstc_sr) is loaded with the value 0x4, indicating a user reset. slck periph_nreset proc_nreset main supply por output nrst (nrst_out) external reset length = 4 cycles (erstl = 1) mck processor startup = 3 cycles backup_nreset any freq. resynch. 2 cycles rsttyp xxx 0x1 = wakeup reset xxx 94 6062b?atarm?15-nov-05 at91sam9261 the nrst manager guarantees that the nrst line is asserted for external_reset_length slow clock cycles, as programmed in the field erstl. how- ever, if nrst does not rise after extern al_reset_length because it is driven low externally, the internal reset lines rema in asserted until nrs t actually rises. figure 14-5. user reset state 14.3.3.4 software reset the reset controller offers several commands used to assert the different reset signals. these commands are performed by writing the control register (rst c_cr) with the following bits at 1: procrst: writing procrst at 1 resets the processor and the watchdog timer. perrst: writing perrst at 1 resets all the embedded peripherals, including the memory system, and, in particular, the remap command. the peripheral reset is generally used for debug purposes. extrst: writing extrst at 1 asserts low the nrst pin during a time defined by the field erstl in the mode register (rstc_mr). the software reset is entered if at least one of these bits is set by the software. all these com- mands can be performed independently or simultaneously. the software reset lasts 2 slow clock cycles. the internal reset signals are asserted as soon as the register write is performed. this is detected on the master clock (mck). they are re leased when the software reset is left, i.e.; synchronously to slck. if extrst is set, the nrst_out signal is asserted depending on the programming of the field erstl. however, the result ing falling edge on nrst does not lead to a user reset. slck periph_nreset proc_nreset nrst nrst (nrst_out) >= external reset length mck processor startup = 3 cycles any freq. resynch. 2 cycles rsttyp any xxx resynch. 2 cycles 0x4 = user reset 95 6062b?atarm?15-nov-05 at91sam9261 if and only if the procrst bit is set, the reset controller reports the software status in the field rsttyp of the status register (rstc_sr). other software resets are not reported in rsttyp. as soon as a software operation is detected, the bit srcmp (software reset command in progress) is set in the status register (rstc_sr). it is cleared as soon as the software reset is left. no other software reset can be performed while the srcmp bit is set, and writing any value in rstc_cr has no effect. figure 14-6. software reset slck periph_nreset if perrst=1 proc_nreset if procrst=1 write rstc_cr nrst (nrst_out) if extrst=1 external reset length 8 cycles (erstl=2) mck processor startup = 3 cycles any freq. rsttyp any xxx 0x3 = software reset resynch. 1 cycle srcmp in rstc_sr 96 6062b?atarm?15-nov-05 at91sam9261 14.3.3.5 watchdog reset the watchdog reset is entered when a watchdog fault occurs. this state lasts 2 slow clock cycles. when in watchdog reset, assertion of the reset signals depends on the wdrproc bit in wdt_mr: if wdrproc is 0, the processor reset and the peripheral reset are asserted. the nrst line is also asserted, depending on the programming of the field erstl. however, the resulting low level on nrst does not result in a user reset state. if wdrproc = 1, only the processor reset is asserted. the watchdog timer is reset by the proc_nrese t signal. as the watchdog fault always causes a processor reset if wdrsten is set, the watchdog timer is always reset after a watchdog reset, and the watchdog is enabled by default and with a period set to a maximum. when the wdrsten in wdt_mr bit is reset, t he watchdog fault has no impact on the reset controller. figure 14-7. watchdog reset 14.3.4 reset state priorities the reset state manager manages the following priorities between the different reset sources, given in descending order: backup reset wake-up reset watchdog reset software reset user reset only if wdrproc = 0 slck periph_nreset proc_nreset wd_fault nrst (nrst_out) external reset length 8 cycles (erstl=2) mck processor startup = 3 cycles any freq. rsttyp any xxx 0x2 = watchdog reset 97 6062b?atarm?15-nov-05 at91sam9261 particular cases are listed below: when in user reset: ? a watchdog event is impossible because the watchdog timer is being reset by the proc_nreset signal. ? a software reset is impossible, since the processor reset is being activated. when in software reset: ? a watchdog event has priority over the current state. ? the nrst has no effect. when in watchdog reset: ? the processor reset is active and so a software reset cannot be programmed. ? a user reset cannot be entered. 14.3.5 reset controller status register the reset controller status register (rstc_sr) provides several status fields: rsttyp field: this field gives the type of the last reset, as explained in previous sections. srcmp bit: this field indicates that a software reset command is in progress and that no further software reset should be performed until the end of the current one. this bit is automatically cleared at the end of the current software reset. nrstl bit: the nrstl bit of the status register gives the level of the nrst pin sampled on each mck rising edge. ursts bit: a high-to-low transition of the nrst pin sets the ursts bit of the rstc_sr register. this transition is also detected on the master clock (mck) rising edge (see figure 14-8 ). if the user reset is disabled (ursten = 0) and if the interruption is enabled by the urstien bit in the rstc_mr register, the ursts bit triggers an interrupt. reading the rstc_sr status register resets the ursts bit and clears the interrupt. figure 14-8. reset controller status and interrupt mck nrst nrstl 2 cycle resynchronization 2 cycle resynchronization ursts read rstc_sr peripheral access rstc_irq if (ursten = 0) and (urstien = 1) 98 6062b?atarm?15-nov-05 at91sam9261 14.4 reset controller (rstc) user interface note: 1. the reset value of rstc_sr either reports a general reset or a wake-up reset depending on last rising power supply. 14.4.1 reset controller control register register name: rstc_cr access type: write-only procrst: processor reset 0 = no effect. 1 = if key is correct, resets the processor. perrst: peripheral reset 0 = no effect. 1 = if key is correct, resets the peripherals. extrst: external reset 0 = no effect. 1 = if key is correct, asserts the nrst pin. key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. table 14-1. reset controller (rstc) register mapping offset register name access reset value back-up reset value 0x00 control register rstc_cr write-only - 0x04 status register rstc_sr read-only 0x0000_0001 0x0000_0000 0x08 mode register rstc_mr read/write - 0x0000_0000 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ? 76543210 ????extrstperrst?procrst 99 6062b?atarm?15-nov-05 at91sam9261 14.4.2 reset controller status register register name: rstc_sr access type: read-only ursts: user reset status 0 = no high-to-low edge on nrst happened since the last read of rstc_sr. 1 = at least one high-to-low transition of nrst has been detected since the last read of rstc_sr. rsttyp: reset type reports the cause of the last processor reset. r eading this rstc_sr does not reset this field. nrstl: nrst pin level registers the nrst pin level at master clock (mck). srcmp: software reset command in progress 0 = no software command is being performed by the reset controller. the reset controller is ready for a software command. 1 = a software reset command is being performed by the reset controller. the reset controller is busy. 14.4.3 reset controller mode register register name: rstc_mr access type: read/write 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ??????srcmpnrstl 15 14 13 12 11 10 9 8 ????? rsttyp 76543210 ?????? ursts rsttyp reset type comments 0 0 0 general reset both vddcore and vddbu rising 0 0 1 wake up reset vddcore rising 0 1 0 watchdog reset watchdog fault occurred 0 1 1 software reset processor re set required by the software 1 0 0 user reset nrst pin detected low 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ??????? 100 6062b?atarm?15-nov-05 at91sam9261 ursten: user reset enable 0 = the detection of a low level on the pin nrst does not generate a user reset. 1 = the detection of a low level on the pin nrst triggers a user reset. urstien: user reset interrupt enable 0 = usrts bit in rstc_sr at 1 has no effect on rstc_irq. 1 = usrts bit in rstc_sr at 1 asserts rstc_irq if ursten = 0. erstl: external reset length this field defines the external reset length. the external reset is asserted during a time of 2 (erstl+1) slow clock cycles. this allows assertion duration to be programmed between 60 s and 2 seconds. key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 15 14 13 12 11 10 9 8 ???? erstl 76543210 ? ? urstien ? ? ? ursten 101 6062b?atarm?15-nov-05 at91sam9261 15. real-time timer (rtt) 15.1 overview the real-time timer is built around a 32-bit counter and used to count elapsed seconds. it generates a periodic interrupt or/and triggers an alarm on a programmed value. 15.2 block diagram figure 15-1. real-time timer 15.3 functional description the real-time timer is used to count elapsed seconds. it is built around a 32-bit counter fed by slow clock divided by a programmable 16-bi t value. the value can be programmed in the field rtpres of the real-time mode register (rtt_mr). programming rtpres at 0x00008000 corresponds to feeding the real-time counter with a 1 hz signal (if the slow clock is 32.768 hz). the 32-bit counter can count up to 2 32 seconds, corresponding to more than 136 years, then roll over to 0. the real-time timer can also be used as a free-running timer with a lower time-base. the best accuracy is achieved by writing rtpres to 3. programming rtpres to 1 or 2 is possi- ble, but may result in losing status events because the status register is cleared two slow clock cycles after read. thus if the rtt is conf igured to trigger an interrupt, the interrupt occurs during 2 slow clock cycles after reading rtt_sr. to prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear. slck rtpres rttinc alms 16-bit divider 32-bit counter almv = crtv rtt_mr rtt_vr rtt_ar rtt_sr rttincien rtt_mr 0 10 almien rtt_int rtt_mr set set rtt_sr read rtt_sr reset reset rtt_mr reload rtt_alarm rttrst rtt_mr rttrst 102 6062b?atarm?15-nov-05 at91sam9261 the real-time timer value (crtv) can be read at any time in the register rtt_vr (real-time value register). as this value can be updated asynchronously from the master clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value. the current value of the counter is compared with the value written in the alarm register rtt_ar (real-time alarm register). if the count er value matches the alarm, the bit alms in rtt_sr is set. the alarm register is set to its maximum value, corresponding to 0xffff_ffff, after a reset. the bit rttinc in rtt_sr is set each time t he real-time timer counter is incremented. this bit can be used to start a periodic interrupt, t he period being one second when the rtpres is programmed with 0x8000 and slow clock equal to 32.768 hz. reading the rtt_sr status register resets the rttinc and alms fields. writing the bit rttrst in rtt_mr immediately reloads and restarts the clock divider with the new programmed value. this also resets the 32-bit counter. figure 15-2. rtt counting prescaler almv almv-1 0 almv+1 0 rtpres - 1 rtt apb cycle read rtt_sr alms (rtt_sr) apb interface mck rttinc (rtt_sr) almv+2 almv+3 ... apb cycle 103 6062b?atarm?15-nov-05 at91sam9261 15.4 real-time timer (rtt) user interface 15.4.1 real-time timer mode register register name: rtt_mr access type: read/write rtpres: real-time timer prescaler value defines the number of slck periods required to increment the real-time timer. rtpres is defined as follows: rtpres = 0: the prescaler period is equal to 2 16 rtpres 0: the prescaler period is equal to rtpres. almien: alarm interrupt enable 0 = the bit alms in rtt_sr has no effect on interrupt. 1 = the bit alms in rtt_sr asserts interrupt. rttincien: real-time timer increment interrupt enable 0 = the bit rttinc in rtt_sr has no effect on interrupt. 1 = the bit rttinc in r tt_sr asserts interrupt. rttrst: real-time timer restart 1 = reloads and restarts the clock divider with the new programmed value. this also resets the 32-bit counter. 15.4.2 real-time timer alarm register register name: rtt_ar table 15-1. real-time timer register mapping offset register name access reset value 0x00 mode register rtt_mr read/write 0x0000_8000 0x04 alarm register rtt_ar read/write 0xffff_ffff 0x08 value register rtt_vr read-only 0x0000_0000 0x0c status register rtt_sr read-only 0x0000_0000 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?????rttrstrttincienalmien 15 14 13 12 11 10 9 8 rtpres 76543210 rtpres 104 6062b?atarm?15-nov-05 at91sam9261 access type: read/write almv: alarm value defines the alarm value (almv+1) compared with the real-time timer. 15.4.3 real-time timer value register register name: rtt_vr access type: read-only crtv: current real-time value returns the current value of the real-time timer. 15.4.4 real-time timer status register register name: rtt_sr access type: read-only 31 30 29 28 27 26 25 24 almv 23 22 21 20 19 18 17 16 almv 15 14 13 12 11 10 9 8 almv 76543210 almv 31 30 29 28 27 26 25 24 crtv 23 22 21 20 19 18 17 16 crtv 15 14 13 12 11 10 9 8 crtv 76543210 crtv 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 105 6062b?atarm?15-nov-05 at91sam9261 alms: real-time alarm status 0 = the real-time alarm has not occurred since the last read of rtt_sr. 1 = the real-time alarm occurred since the last read of rtt_sr. rttinc: real-time timer increment 0 = the real-time timer has not been incremented since the last read of the rtt_sr. 1 = the real-time timer has been incremented since the last read of the rtt_sr. 76543210 ??????rttincalms 106 6062b?atarm?15-nov-05 at91sam9261 16. periodic interval timer (pit) 16.1 overview the periodic interval timer (pit) provides the operating system?s scheduler interrupt. it is designed to offer maximum accuracy and efficient management, even for systems with long response time. 16.2 block diagram figure 16-1. periodic interval timer 16.3 functional description the periodic interval timer aims at providing periodic interrupts for use by operating systems. the pit provides a programmable overflow counter and a reset-on-read feature. it is built around two counters: a 20-bit cpiv counter and a 12-bit picnt counter. both counters work at master clock /16. the first 20-bit cpiv counter increments from 0 up to a programmable overflow value set in the field piv of the mode register (pit_mr). when the counter cpiv reaches this value, it resets to 0 and increments the periodic interval counter, picnt. the status bit pits in the status register (pit_sr) rises and triggers an interrupt, provided the interrupt is enabled (pitien in pit_mr). writing a new piv value in pit_mr does not reset/restart the counters. 20-bit counter mck/16 piv pit_mr cpiv pit_pivr picnt 12-bit adder 0 0 read pit_pivr cpiv picnt pit_piir pits pit_sr set reset pitien pit_mr pit_irq 1 0 1 0 mck prescaler = ? 107 6062b?atarm?15-nov-05 at91sam9261 when cpiv and picnt values are obtained by r eading the periodic interval value register (pit_pivr), the overflow counter (picnt) is reset and the pits is cleared, thus acknowledg- ing the interrupt. the value of picnt gives the number of periodic intervals elapsed since the last read of pit_pivr. when cpiv and picnt values are obtained by reading the periodic interval image register (pit_piir), there is no effect on the counters cpiv and picnt, nor on the bit pits. for exam- ple, a profiler can read pit_piir without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading pit_pivr. the pit may be enabled/disabled using the piten bit in the pit_mr register (disabled on reset). the piten bit only becomes effective when the cpiv value is 0. figure 16-2 illustrates the pit counting. after the pit enable bit is reset (piten= 0), the cpiv goes on counting until the piv value is reached, and is then reset. pit restarts counting, only if the piten is set again. the pit is stopped when the core enters debug state. figure 16-2. enabling/disabling pit with piten mck prescaler piv piv - 1 0 piten 10 0 15 cpiv 1 restarts mck prescaler 0 1 apb cycle read pit_pivr 0 picnt pits (pit_sr) mck apb interface apb cycle 108 6062b?atarm?15-nov-05 at91sam9261 16.4 periodic interval time r (pit) user interface 16.4.1 periodic interval timer mode register register name: pit_mr access type: read/write piv: periodic interval value defines the value compared with the primary 20-bit counter of the periodic interval timer (cpiv). the period is equal to (piv + 1). piten: period interval timer enabled 0 = the periodic interval timer is disabled when the piv value is reached. 1 = the periodic interval timer is enabled. pitien: periodic interval timer interrupt enable 0 = the bit pits in pit_sr has no effect on interrupt. 1 = the bit pits in pit_sr asserts interrupt. 16.4.2 periodic interval timer status register register name: pit_sr access type: read-only table 16-1. periodic interval timer (pit) register mapping offset register name access reset value 0x00 mode register pit_mr read/write 0x000f_ffff 0x04 status register pit_sr read-only 0x0000_0000 0x08 periodic interval value register pit_pivr read-only 0x0000_0000 0x0c periodic interval image register pit_piir read-only 0x0000_0000 31 30 29 28 27 26 25 24 ??????pitienpiten 23 22 21 20 19 18 17 16 ???? piv 15 14 13 12 11 10 9 8 piv 76543210 piv 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 109 6062b?atarm?15-nov-05 at91sam9261 pits: periodic interval timer status 0 = the periodic interval timer has not reached piv since the last read of pit_pivr. 1 = the periodic interval timer has reached piv since the last read of pit_pivr. 16.4.3 periodic interval timer value register register name: pit_pivr access type: read-only reading this register clears pits in pit_sr. cpiv: current periodic interval value returns the current value of the periodic interval timer. picnt: periodic interval counter returns the number of occurrences of periodic intervals since the last read of pit_pivr. 16.4.4 periodic interval timer image register register name: pit_piir access type: read-only 15 14 13 12 11 10 9 8 ???????? 76543210 ???????pits 31 30 29 28 27 26 25 24 picnt 23 22 21 20 19 18 17 16 picnt cpiv 15 14 13 12 11 10 9 8 cpiv 76543210 cpiv 31 30 29 28 27 26 25 24 picnt 23 22 21 20 19 18 17 16 picnt cpiv 15 14 13 12 11 10 9 8 cpiv 110 6062b?atarm?15-nov-05 at91sam9261 cpiv: current periodic interval value returns the current value of the periodic interval timer. picnt: periodic interval counter returns the number of occurrences of periodic intervals since the last read of pit_pivr. 76543210 cpiv 111 6062b?atarm?15-nov-05 at91sam9261 17. watchdog timer (wdt) 17.1 overview the watchdog timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. it features a 12-bit down counter that allows a watchdog period of up to 16 sec- onds (slow clock at 32.768 khz). it can generate a general reset or a processor reset only. in addition, it can be stopped while the processor is in debug mode or idle mode. 17.2 block diagram figure 17-1. watchdog timer block diagram = 0 10 set reset read wdt_sr or reset wdt_fault (to reset controlle r) set reset wdfien wdt_int wdt_mr slck 1/128 12-bit down counter current value wdd wdt_mr <= wdd wv wdrstt wdt_mr wdt_cr reload wdunf wderr reload write wdt_mr wdrsten wdt_mr 112 6062b?atarm?15-nov-05 at91sam9261 17.3 functional description the watchdog timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. it is supplied with vddcore. it restarts with initial values on processor reset. the watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field wv of the mode register (wdt_mr) . the watchdog timer uses the slow clock divided by 128 to establish the maximum watchdog period to be 16 seconds (with a typical slow clock of 32.768 khz). after a processor reset, the value of wv is 0xfff, corresponding to the maximum value of the counter with the external reset generat ion enabled (field wdrsten at 1 after a backup reset). this means that a default watchdog is running at reset, i.e., at power-up. the user must either disable it (by setting the wddis bit in wdt_mr) if he does not expect to use it or must reprogram it to meet the maximum watchdog period the application requires. the watchdog mode register (wdt_mr) can be written only once. only a processor reset resets it. writing the wdt_mr register reloads the timer with the newly programmed mode parameters. in normal operation, the user reloads the watchdog at regular intervals before the timer under- flow occurs, by writing the control register (wdt_cr) with the bit wdrstt to 1. the watchdog counter is then immediately reload ed from wdt_mr and restarted, and the slow clock 128 divider is reset and restarted. the wdt_ cr register is write-protected. as a result, writing wdt_cr without the correct hard-coded key has no effect. if an underflow does occur, the ?wdt_fault? signal to the reset controller is asserted if the bit wdrsten is set in the mode register (wdt_mr). moreover, the bit wdunf is set in th e watchdog status register (wdt_sr). to prevent a software deadlock that continuously triggers the watchdog, the reload of the watchdog must occur in a window defined by 0 and wdd in the wdt_mr: 0 wdt wdd; writing wdrstt rest arts the watchdog timer. any attempt to restart the watchdog timer in the range [wdv; wdd] results in a watchdog error, even if the watchdog is disabled. the bit wderr is updated in the wdt_sr and the ?wdt_fault? signal to the reset controller is asserted. note that this feature can be disabled by programming a wdd value greater than or equal to the wdv value. in such a configuration, restarting the watchdog timer is permitted in the whole range [0; wdv] and does not generate an error. this is the default configuration on reset (the wdd and wdv values are equal). the status bits wdunf (watchdog underflow) and wderr (watchdog error) trigger an inter- rupt, provided the bit wdfien is set in the mode register. the signal ?wdt_fault? to the reset controller causes a watchdog reset if the wdrsten bit is set as already explained in the reset controller programmer datasheet. in that case, the processor and the watchdog timer are reset, and the wderr and wdunf flags are reset. if a reset is generated or if wdt_sr is read, the status bits are reset, the interrupt is cleared, and the ?wdt_fault? signal to the reset controller is deasserted. writing the wdt_mr reloads and restarts the down counter. while the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits wdidlehlt and wddbghlt in the wdt_mr. 113 6062b?atarm?15-nov-05 at91sam9261 figure 17-2. watchdog behavior 0 wdv wdd wdt_cr = wdrstt watchdog fault normal behavior watchdog error watchdog underflow fff if wdrsten is 1 if wdrsten is 0 forbidden window permitted window 114 6062b?atarm?15-nov-05 at91sam9261 17.4 watchdog timer (wdt) user interface 17.4.1 watchdog timer control register register name: wdt_cr access type: write-only wdrstt: watchdog restart 0: no effect. 1: restarts the watchdog. key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. table 17-1. watchdog timer (wdt) register mapping offset register name access reset value 0x00 control register wdt_cr write-only - 0x04 mode register wdt_mr read/write once 0x3fff_2fff 0x08 status register wdt_sr read-only 0x0000_0000 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????wdrstt 115 6062b?atarm?15-nov-05 at91sam9261 17.4.2 watchdog timer mode register register name: wdt_mr access type: read / write once wdv: watchdog counter value defines the value loaded in the 12-bit watchdog counter. wdfien: watchdog fault interrupt enable 0: a watchdog fault (underflow or error) has no effect on interrupt. 1: a watchdog fault (underflow or error) asserts interrupt. wdrsten: watchdog reset enable 0: a watchdog fault (underflow or error) has no effect on the resets. 1: a watchdog fault (underflow or error) triggers a watchdog reset. wdrproc: watchdog reset processor 0: if wdrsten is 1, a watchdog fault (underflow or error) activates all resets. 1: if wdrsten is 1, a watchdog fault (underflow or error) activates the processor reset. wdd: watchdog delta value defines the permitted range for reloading the watchdog timer. if the watchdog timer value is less than or equal to wdd, writing wdt_cr with wdrstt = 1 restarts the timer. if the watchdog timer value is greater than wdd, writing wdt_cr with wdrstt = 1 causes a watchdog error. wddbghlt: watchdog debug halt 0: the watchdog runs when the processor is in debug state. 1: the watchdog stops when the processor is in debug state. wdidlehlt: watchdog idle halt 0: the watchdog runs when the system is in idle mode. 1: the watchdog stops when the system is in idle state. wddis: watchdog disable 0: enables the watchdog timer. 1: disables the watchdog timer. 31 30 29 28 27 26 25 24 wdidlehlt wddbghlt wdd 23 22 21 20 19 18 17 16 wdd 15 14 13 12 11 10 9 8 wddis wdrproc wdrsten wdfien wdv 76543210 wdv 116 6062b?atarm?15-nov-05 at91sam9261 17.4.3 watchdog timer status register register name: wdt_sr access type: read-only wdunf: watchdog underflow 0: no watchdog underflow occurred since the last read of wdt_sr. 1: at least one watchdog underflow occurred since the last read of wdt_sr. wderr: watchdog error 0: no watchdog error occurred since the last read of wdt_sr. 1: at least one watchdog error occurred since the last read of wdt_sr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????wderrwdunf 117 6062b?atarm?15-nov-05 at91sam9261 18. shutdown controller (shdwc) 18.1 description the shutdown controller contro ls the power supplies vddi o and vddcore and the wake- up detection on debounced input lines. 18.2 block diagram figure 18-1. shutdown contro ller block diagram 18.3 i/o lines description 18.4 product dependencies 18.4.1 power management the shutdown controller is continuously clocked by slow clock. the power management controller has no effect on the behavior of the shutdown controller. 18.5 functional description the shutdown controller manages the main power supply. to do so, it is supplied with vddbu and manages wake-up input pins and one output pin, shdw. shutdown wake-up shutdown output controller shdw wkup0 shdw wkmode0 shutdown controller rtt alarm rttwken sysc_shmr sysc_shmr sysc_shcr cptwk0 wakeup0 rttwk sysc_shsr sysc_shsr set set reset reset read sysc_shsr read sysc_shsr slck table 18-1. i/o lines description name description type wkup0 wake-up 0 input input shdw shutdown output output 118 6062b?atarm?15-nov-05 at91sam9261 a typical application connects th e pin shdw to the shutdown input of the dc/dc converter providing the main power supplies of the system, and especially vddcore and/or vddio. the wake-up inputs (wkup0) connect to any push-buttons or signal that wake up the system. the software is able to control the pin shdw by writing the shutdown control register (shdw_cr) with the bit shdw at 1. this regi ster is password-protected and so the value written should contain the correct key for the command to be taken into account. as a result, the system should be powered down. a level change on wkup0 is used as wake-up. wake-up is configured in the shutdown mode register (shdw_mr). the trans ition detector can be programmed to detect either a positive or negative transition or any level change on wkup0. the detection can also be disabled. programming is performed by defining wkmode0. moreover, a debouncing circuit can be programmed for wkup0. the debouncing circuit filters pulses on wkup0 shorter than the programmed num ber of 16 slck cycles in cptwk0 of the shdw_mr register. if the programmed level change is detected on a pin, a counter starts. when the counter reaches the value programmed in the corresponding field, cptwk0 , the shdw pin is released. if a new input change is detected before the counter reaches the corre- sponding value, the counter is stopped and cl eared. wakeup0 of the status register (shdw_sr) reports the detection of the programmed events on wkup0, with a reset after the read of shdw_sr. 119 6062b?atarm?15-nov-05 at91sam9261 18.6 shutdown controller (shdwc) user interface 18.6.1 register mapping 18.6.2 shutdown control register register name: shdw_cr access type: write-only shdw: shut down command 0 = no effect. 1 = if key is correct, asserts the shdw pin. key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. table 18-2. shutdown controller (shdwc) registers offset register name access reset value 0x00 shutdown control register shdw_cr write-only - 0x04 shutdown mode register shdw_mr read-write 0x0000_0103 0x18 shutdown status register shdw_sr read-only 0x0000_0000 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????shdw 120 6062b?atarm?15-nov-05 at91sam9261 18.6.3 shutdown mode register register name: shdw_mr access type: read/write wkmode0: wake-up mode 0 cptwk0: counter on wake-up 0 defines the number of 16 slow clock cycles, the level detection on the corresponding input pin shall last before the wake- up event occurs. because of the internal synchro nization of wkup0 , the shdw pin is released (cptwk x 16 + 1) slow clock cycles after the event on wkup. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???? 76543210 cptwk0 ? ? wkmode0 wkmode[1:0] wake-up inpu t transition selection 0 0 none. no detection is performed on the wake-up input 0 1 low to high level 1 0 high to low level 1 1 both levels change 121 6062b?atarm?15-nov-05 at91sam9261 18.6.4 shutdown status register register name: shdw_sr access type: read-only wakeup0: wake-up 0 status 0 = no wake-up event occurred on the corresponding wake-up input since the last read of shdw_sr. 1 = at least one wake-up event occurred on the corresponding wake-up input since the last read of shdw_sr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????w akeup0 122 6062b?atarm?15-nov-05 at91sam9261 19. bus matrix 19.1 overview the bus matrix implements a multi-layer ahb, based on ahb-lite protoc ol, that enables par- allel access paths between multiple ahb masters and slaves in a system, thus increasing the overall bandwidth. the bus matrix interconnects 5 ahb masters to 5 ahb slaves. the bus matrix user interface is compliant with the ar m advanced peripheral bus and provides 5 spe- cial function registers (matrix_sfr) that allow the bus matrix to support application- specific features. 19.2 memory mapping the bus matrix provides one decoder for every ahb master interface. the decoder offers each ahb master several memory mappings. depending on the product, each memory area may be assigned to several slaves. booting at the same address while using different ahb slaves (i.e., external ram, internal rom, internal flash, etc.) becomes possible. the bus matrix user interface provides a mast er configuration register (matrix_mcfg) that performs a remap action for every master independently. 19.3 special bus granting techniques the bus matrix provides some speculative bus granting techniques in order to anticipate access requests from some masters. this technique reduces latency at first accesses. the bus granting technique sets a default master for every slave. at the end of the current access, if no other request is pending, the slave remains connected to its associated default master. a slave can be associated with three kinds of default masters; no default master, last access master and fixed default master. 19.3.1 no default master at the end of current access, if no other request is pending, the slave is disconnected from all masters. no default mast er suits low-power mode. 19.3.2 last access master at the end of current access, if no other request is pending, the slave remains connected to the last master that performs an access request. 19.3.3 fixed default master at the end of current access, if no other request is pending, the slave remains connected to its fixed default master. unlike last access master, the fixed master does not change unless the user changes it by a software action. to change from one kind of default master to another, the bus matrix user interface provides 5 slave configuration registers, one for each slave, that set default master for each slave. the slave configuration register contains two fields; defm str_type and fixed_defmstr. the 2-bit defmstr_type flag selects the defaul t master type (no default, last access mas- ter, fixed default master) whereas the 3-bit fixed_defmstr flag selects a fixed default master provided that defmstr_type is set to a fixed default master. see ?bus matrix user interface? on page 124 . 123 6062b?atarm?15-nov-05 at91sam9261 19.4 arbitration the bus matrix provides an arbitration function that reduces latency when conflicting cases occur, i.e., when two or more masters try to access the same slave at the same time. the bus matrix arbitration mechanism us es slightly modified round-robin algorithms that grant the bus for the first access to a certain master depending on parameters located in the slave?s slave configuration register. there are three round-robin algorithm types: round-robin arbitration without default master round-robin arbitration with last access master round-robin arbitration with fixed default master 19.4.1 round-robin arbitration without default master this is the main algorithm used by bus matrix arbiters. it allows the bus matrix to dispatch requests from different masters to the same slave in a pure round-robin manner. at the end of the current access, if no other request is pendi ng, the slave is disconnected from all masters. this configuration incurs one la tency cycle for the first access. arbitration without default mas- ter can be used for masters that perform significant bursts. 19.4.2 round-robin arbitration with last access master this is a biased round-robin algorithm used by bu s matrix arbiters. it a llows the bus matrix to remove one latency cycle for the last master that accessed the slave. in fact, at the end of the current transfer, if no other master request is pending, the slave remains connected to the last master that performs th e access. other non-privileged master s still obtain one latency cycle if they want to access the same slave. this technique can be used for masters that perform mainly single accesses. 19.4.3 round-robin arbitration with fixed default master this is a biased round-robin algorithm. it allows the bus matrix arbiters to remove one latency cycle for the fixed master of a slave. at the end of the current access, the slave remains con- nected to its fixed default master. any request attempted by this fixed default master does not cause any latency, whereas other non-privileged ma sters still obtain one latency cycle. this technique can be used for masters that perform mainly single accesses. 124 6062b?atarm?15-nov-05 at91sam9261 19.5 bus matrix user interface table 19-1. register mapping offset register name access reset value 0x0000 master configuration register matrix_mcfg write only 0x00000000 0x0004 slave configuration register 0 matrix_scfg0 read/write 0x00000010 0x0008 slave configuration register 1 matrix_scfg1 read/write 0x00000010 0x000c slave configuration register 2 matrix_scfg2 read/write 0x00000010 0x0010 slave configuration register 3 matrix_scfg3 read/write 0x00000010 0x0014 slave configuration register 4 matrix_scfg4 read/write 0x00000010 0x0018 - 0x0020 reserved ? ? ? 0x0024 matrix tcm configuration register matrix_tcr read/write 0x00000000 0x028 - 0x002c reserved ? ? ? 0x0030 ebi chip select assignment register ebi_csa read/write 0x00000000 0x0034 usb pad pull-up control register usb_pucr read/write 0x00000000 125 6062b?atarm?15-nov-05 at91sam9261 19.5.1 bus matrix master configuration register register name: matrix_mcfg access type: read/write rcbx: remap command bit for ahb master x 0: no effect 1: this command bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of addressed slaves from master x. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? rcb4 rcb3 rcb2 rcb1 rcb0 126 6062b?atarm?15-nov-05 at91sam9261 19.5.2 bus matrix slave configuration registers register name: matrix_scfg0...matrix_scfg4 access type: read/write slot_cycle: maximum number of allowed cycles for a burst when the slot_cycle limit is reached for a burst, it may be broken by another master tr ying to access this slave. this limit has been set to avoid locking very sl ow slaves when very long bursts are used. this limit should not be very small. an unreasonably small va lue breaks every burst and the bus matrix spends its time arbitrating without performing any data transfer. 16 cycles is a reasonable value for slot_cycle. defmastr_type: default master type 0: no default master at the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters. this results in one cycle latency for the first transfer of a burst. 1: last default master at the end of the current slave access, if no other master request is pending, the slave remains connected to the last mas- ter that accessed it. this results in not having the one cycle latency when the last master is trying to access the slave again. 2: fixed default master at the end of the current slave access, if no other master req uest is pending, the slave connects with the fixed master that has its index in fixed_defmstr register. this results in not having the one cycle latency when the fixed master is trying to access the slave again. fixed_defmstr: fixed i ndex of default master this is the index of the fixed default master for this slave. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? fixed_defmstr defmstr_type 15 14 13 12 11 10 9 8 ???????? 76543210 slot_cycle 127 6062b?atarm?15-nov-05 at91sam9261 19.5.3 bus matrix tcm configuration register register name: matrix_tcr access type: read/write reset: 0x0000_0000 itcm_size: size of itcm enabled memory block 0000 0kb (no itcm memory) 0101: 16 kb 0110: 32 kb 0111: 64 kb others: reserved dtcm_size: size of dtcm enabled memory block 0000 0 kb (no dtcm memory) 0101: 16 kb 0110: 32 kb 0111: 64 kb others: reserved 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 dtcm_size itcm_size 128 6062b?atarm?15-nov-05 at91sam9261 19.5.4 ebi chip select assignment register register name: ebi_csa access type: read/write reset: 0x0000_0000 ebi_cs1a: ebi chip select 1 assignment 0 = ebi chip select 1 is assigned to the static memory controller. 1 = ebi chip select 1 is assigned to the sdram controller. ebi_cs3a: ebi chip select 3 assignment 0 = ebi chip select 3 is only assigned to the static memory controller and ebi_ncs3 behaves as defined by the smc. 1 = ebi chip select 3 is assigned to the static memory controller and the smartmedia logic is activated. ebi_cs4a: ebi chip select 4 assignment 0 = ebi chip select 4 is only assigned to the static memory controller and ebi_ncs4 behaves as defined by the smc. 1 = ebi chip select 4 is assigned to the static memory controller and the compactflash logic (first slot) is activated. ebi_cs5a: ebi chip select 5 assignment 0 = ebi chip select 5 is only assigned to the static memory controller and ebi_ncs5 behaves as defined by the smc. 1 = ebi chip select 5 is assigned to the static memory co ntroller and the compactflash logic (second slot) is activated. ebi_dbpuc: ebi data bus pull-up configuration 0 = ebi d0 - d15 data bus bits are interna lly pulled-up to the vddiom0 power supply. 1 = ebi d0 - d15 data bus bits are not internally pulled-up. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????ebi_dbpuc 76543210 ? ? ebi_cs5a ebi_cs4a ebi_cs3a ? ebi_cs1a ? 129 6062b?atarm?15-nov-05 at91sam9261 19.5.5 usb pad pull-up control register register name: usb_pucr access type: read/write reset: 0x0000_0000 udp_pup_on: udp pad pull-up enable 0: pad pull-up disabled 1: pad pull-up enabled 31 30 29 28 27 26 25 24 reserved udp_pup_on ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????? 130 6062b?atarm?15-nov-05 at91sam9261 20. external bus interface (ebi) 20.1 overview the external bus interface (ebi) is designed to ensure the successful data transfer between several external devices and the embedded memory controller of an arm ? -based device. the static memory and sdram controllers are all featured external memory controllers on the ebi. these external memory controllers are capable of handling several types of external memory and peripheral devices, such as sram, prom, eprom, eeprom, flash, and sdram. the ebi also supports the compactflash and the nand flash protocols via integrated cir- cuitry that greatly reduces the requirements for external components. furthermore, the ebi handles data transfers with up to eight exte rnal devices, each assigned to eight address spaces defined by the embedded memory controller. data transfers are performed through a 16-bit or 32-bit data bus, an address bus of up to 26 bits, up to eight chip select lines (ncs[7:0]) and several control pins that are generally multiplexed between the different exter- nal memory controllers. 131 6062b?atarm?15-nov-05 at91sam9261 20.2 block diagram figure 20-1 shows the organization of the external bus interface. figure 20-1. organization of the external bus interface external bus interface d[15:0] a[15:2], a[21:18] pio mux logic nand flash logic compactflash logic user interface chip select assignor static memory controller sdram controller bus matrix apb ahb address decoders a16/ba0 a0/nbs0 a1/nwr2/nbs2 a17/ba1 ncs0 ncs3/nandcs nrd/cfoe ncs1/sdcs ncs2 nwr0/nwe/cfwe nwr1/nbs1/cfior nwr3/nbs3/cfiow sdck sdcke ras cas sdwe d[31:16] a[24:23] a25/cfrnw ncs4/cfcs0 ncs5/cfcs1 ncs6/nandoe ncs7/nandwe cfce1 cfce2 nwait sda10 a22/reg 132 6062b?atarm?15-nov-05 at91sam9261 20.3 i/o lines description table 20-1. i/o lines description name function type active level ebi d0 - d31 data bus i/o a0 - a25 address bus output nwait external wait signal input low smc ncs0 - ncs7 chip select lines output low nwr0 - nwr3 write signals output low nrd read signal output low nwe write enable output low nbs0 - nbs3 byte mask signals output low ebi for compactflash support cfce1 - cfce2 compactflash chip enable output low cfoe compactflash output enable output low cfwe compactflash write enable output low cfior compactflash i/o read signal output low cfiow compactflash i/o write signal output low cfrnw compactflash read not write signal output cfcs0 - cfcs1 compactflash chip select lines output low ebi for nand flash support nandcs nand flash chip select line output low nandoe nand flash output enable output low nandwe nand flash write enable output low sdram controller sdck sdram clock output sdcke sdram clock enable output high sdcs sdram controller chip select line output low ba0 - ba1 bank select output sdwe sdram write enable output low ras - cas row and column signal output low nwr0 - nwr3 write signals output low nbs0 - nbs3 byte mask signals output low sda10 sdram address 10 line output 133 6062b?atarm?15-nov-05 at91sam9261 the connection of some signals through the mux logic is not direct and depends on the mem- ory controller in use at the moment. table 20-2 on page 133 details the connections between the two memory controllers and the ebi pins. 20.4 application example 20.4.1 hardware interface table 20-3 and table 20-4 detail the connections to be applied between the ebi pins and the external devices for each memory controller. table 20-2. ebi pins and memory controllers i/o lines connections ebi pins sdramc i/o lines smc i/o lines nwr1/nbs1/cfior nbs1 nwr1/nub a0/nbs0 not supported smc_a0/nlb a1/nbs2/nwr2 not supported smc_a1 a[11:2] sdramc_a[9:0] smc_a[11:2] sda10 sdramc_a1 0 not supported a12 not supported smc_a12 a[14:13] sdramc_a[12:11] smc_a[14:13] a[25:15] not supported smc_a[25:15] d[31:16] d[31:16] d[31:16] d[15:0] d[15:0] d[15:0] table 20-3. ebi pins and external static devices connections pins pins of the interfaced device 8-bit static device 2 x 8-bit static devices 16-bit static device 4 x 8-bit static devices 2 x 16-bit static devices 32-bit static device controller smc d0 - d7 d0 - d7 d0 - d7 d0 - d7 d0 - d7 d0 - d7 d0 - d7 d8 - d15 ? d8 - d15 d8 - d15 d8 - d15 d8 - 15 d8 - 15 d16 - d23 ? ? ? d16 - d23 d16 - d23 d16 - d23 d24 - d31 ? ? ? d24 - d31 d24 - d31 d24 - d31 a0/nbs0 a0 ? nlb ? nlb (3) be0 (5) a1/nwr2/nbs2 a1 a0 a0 we (2) nlb (4) be2 (5) a2 - a25 a[2:25] a[1:24] a[1:24] a[0:23] a[0:23] a[0:23] ncs0 cs cs cs cs cs cs ncs1/sdcs cs cs cs cs cs cs ncs2 cs cs cs cs cs cs ncs3/nandcs cs cs cs cs cs cs ncs4/cfcs0 cs cs cs cs cs cs 134 6062b?atarm?15-nov-05 at91sam9261 notes: 1. nwr1 enables upper byte writes. nwr0 enables lower byte writes. 2. nwrx enables corresponding byte x writes. (x = 0, 1, 2 or 3) 3. nbs0 and nbs1 enable respectively lower and upper bytes of the lower 16-bit word. 4. nbs2 and nbs3 enable respectively lower and upper bytes of the upper 16-bit word. 5. bex: byte x enable (x = 0,1,2 or 3) ncs5/cfcs1 cs cs cs cs cs cs ncs6/nand0e cs cs cs cs cs cs ncs7/nandwe cs cs cs cs cs cs nrd/cfoe oe oe oe oe oe oe nwr0/nwe we we (1) we we (2) we we nwr1/nbs1 ? we (1) nub we (2) nub (3) be1 (5) nwr3/nbs3 ? ? ? we (2) nub (4) be3 (5) table 20-3. ebi pins and external static devices connections (continued) pins pins of the interfaced device 8-bit static device 2 x 8-bit static devices 16-bit static device 4 x 8-bit static devices 2 x 16-bit static devices 32-bit static device controller smc table 20-4. ebi pins and external devices connections pins pins of the interfaced device sdram compact flash compact flash true ide mode nand flash controller sdramc smc d0 - d7 d0 - d7 d0 - d7 d0 - d7 ad0-ad7 d8 - d15 d8 - d15 d8 - 15 d8 - 15 ad8-ad15 d16 - d31 d16 - d31 ? ? ? a0/nbs0 dqm0 a0 a0 ? a1/nwr2/nbs2 dqm2 a1 a1 ? a2 - a10 a[0:8] a[2:10] a[2:10] ? a11 a9 ? ? ? sda10 a10 ? ? ? a12 ? ? ? ? a13 - a14 a[11:12] ? ? ? a15 ? ? ? ? a16/ba0 ba0 ? ? ? a17/ba1 ba1 ? ? ? a18 - a20 ? ? ? ? a21 ? ? ? cle (3) a22 ? reg reg ale (3) a23 - a24 ? ? ? ? 135 6062b?atarm?15-nov-05 at91sam9261 note: 1. not directly connected to the compactflash slot. permits the control of the bidirectional buffer between the ebi data bus and the compactflash slot. 2. any pio line. 3. the cle and ale signals of the nand flash device may be driven by any address bit. for details, see ?nand flash support? on page 142 . a25 ? cfrnw (1) cfrnw (1) ? ncs0 ? ? ? ? ncs1/sdcs cs ? ? ? ncs2 ? ? ? ? ncs3/nandcs ? ? ? ? ncs4/cfcs0 ? cfcs0 (1) cfcs0 (1) ? ncs5/cfcs1 ? cfcs1 (1) cfcs1 (1) ? ncs6/nandoe ? ? ? oe ncs7/nandwe ? ? ? we nrd/cfoe ? oe ? ? nwr0/nwe/cfwe ? we we ? nwr1/nbs1/cfior dqm1 ior ior ? nwr3/nbs3/cfiow dqm3 iow iow ? cfce1 ? ce1 cs0 ? cfce2 ? ce2 cs1 ? sdck clk ? ? ? sdcke cke ? ? ? ras ras ? ? ? cas cas ? ? ? sdwe we ? ? ? nwait ? wait wait ? pxx (2) ? cd1 or cd2 cd1 or cd2 ? pxx (2) ???ce pxx (2) ???rdy table 20-4. ebi pins and external devices connections (continued) pins pins of the interfaced device sdram compact flash compact flash true ide mode nand flash controller sdramc smc 136 6062b?atarm?15-nov-05 at91sam9261 20.4.2 connection examples figure 20-2 shows an example of connections be tween the ebi and external devices. figure 20-2. ebi connections to memory devices 20.5 product dependencies 20.5.1 i/o lines the pins used for interfacing the external bus interface may be multiplexed with the pio lines. the programmer must first program the pio controller to assign the external bus interface pins to their peripheral function. if i/o lines of the external bus interface are not used by the application, they can be used for other purposes by the pio controller. ebi d0-d31 a2-a15 ras cas sdck sdcke sdwe a0/nbs0 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 nwr1/nbs1 a1/nwr2/nbs2 nwr3/nbs3 ncs1/sdcs d0-d7 d8-d15 a16/ba0 a17/ba1 a18-a25 a10 sda10 sda10 a2-a11, a13 ncs0 ncs2 ncs3 ncs4 ncs5 ncs6 ncs7 a16/ba0 a17/ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 a10 sda10 a2-a11, a13 a16/ba0 a17/ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 d16-d23 d24-d31 a10 sda10 a2-a11, a13 a16/ba0 a17/ba1 2m x 8 sdram d0-d7 a0-a9, a11 ras cas clk cke we dqm cs ba0 ba1 a10 sda10 a2-a11, a13 a16/ba0 a17/ba1 nbs0 nbs1 nbs3 nbs2 nrd nwr0/nwe 128k x 8 sram 128k x 8 sram d0-d7 d0-d7 a0-a16 a0-a16 a1-a17 a1-a17 cs cs oe we d0-d7 d8-d15 oe we nrd/noe a0/nwr0/nbs0 nrd/noe nwr1/nbs1 sdwe sdwe sdwe sdwe 137 6062b?atarm?15-nov-05 at91sam9261 20.6 functional description the ebi transfers data between the internal ahb bus (handled by the bus matrix) and the external memories or peripheral devices. it co ntrols the waveforms and the parameters of the external address, data and control busses and is composed of the following elements: static memory controller (smc) sdram controller (sdramc) a chip select assignment feature that assigns an ahb address space to the external devices a multiplex controller circuit that shares the pins between the different memory controllers programmable compactflash support logic programmable nand flash support logic 20.6.1 bus multiplexing the ebi offers a complete set of control signals that share the 32-bit data lines, the address lines of up to 26 bits and the control signals through a multiplex logic operating in function of the memory area requests. multiplexing is specific ally organized in order to guarantee the maintenance of the address and output control lines at a stable state while no external access is being performed. multi- plexing is also designed to respect the data float times defined in the memory controllers. furthermore, refresh cycles of the sdram ar e executed independently by the sdram con- troller without delaying the other external memory controller accesses. 20.6.2 pull-up control the ebi_csa register in the bus matrix user interface permits enabling of on-chip pull-up resistors on the data bus lines not multiplexed with the pio controller lines. the pull-up resis- tors are enabled after reset. setting the dbpuc bit disables the pull-up resistors on the d0 to d15 lines. enabling the pull-up resistor on the d16-d31 lines can be performed by program- ming the appropriate pio controller. 20.6.3 static memory controller for information on the static memory controller, refer to the static memory controller section. 20.6.4 sdram controller for information on the sdram contro ller, refer to the sdram section. 20.6.5 compactflash support the external bus interface integrates circuitry that interfaces to compactflash devices. the compactflash logic is driven by the static memory controller (smc) on the ncs4 and/or ncs5 address space. programming the cs4a and/ or cs5a bit of the ebi_csa register to the appropriate value enables this logic. for details on this register, refer to the bus matrix user interface section. access to an external compactflash device is then made by access- ing the address space reserved to ncs4 and/or ncs5 (i.e., between 0x5000 0000 and 0x5fff ffff for ncs4 and between 0x6000 0000 and 0x6fff ffff for ncs5). all compactflash modes (attribute memory, common memory, i/o and true ide) are sup- ported but the signals _iois16 (i/o and true ide modes) and _ata sel (true ide mode) are not handled. 138 6062b?atarm?15-nov-05 at91sam9261 20.6.5.1 i/o mode, common memory mode, attribute memory mode and true ide mode within the ncs4 and/or ncs5 address space, the current transfer address is used to distin- guish i/o mode, common memory mode, attribute memory mode and true ide mode. the different modes are accessed through a specific memory mapp ing as illustrated on figure 20-3 . a[23:21] bits of the transfer address are used to select the desired mode as described in table 20-5 on page 138 . figure 20-3. compactflash memory mapping note: the a22 pin of the ebi is used to drive the reg signal of the compactflash device (except in true ide mode). 20.6.5.2 cfce1 and cfce2 signals to cover all types of access, the smc must be alternatively set to drive 8-bit data bus or 16-bit data bus. the odd byte access on the d[7:0] bus is only possible when the smc is configured to drive 8-bit memory devices on the corresponding ncs pin (ncs4 and or ncs5). the chip select register (dbw field in the corresponding chip select mode register) of the ncs4 and/or ncs5 address space must be set as shown in table 20-6 to enable the required access type. nbs1 and nbs0 are the byte selection signals from smc and are available when the smc is set in byte select mode on the corresponding chip select. table 20-5. compactflash mode selection a[23:21] mode base address 000 attribute memory 010 common memory 100 i/o mode 110 true ide mode 111 alternate true ide mode cf address space attribute memory mode space common memory mode space i/o mode space true ide mode space true ide alternate mode space offset 0x00e0 0000 offset 0x00c0 0000 offset 0x0080 0000 offset 0x0040 0000 offset 0x0000 0000 139 6062b?atarm?15-nov-05 at91sam9261 the cfce1 and cfce2 waveforms are identical to the corresponding ncsx waveform. for details on these waveforms and timings, refer to the static memory controller section. 20.6.5.3 read/write signals in i/o mode and true ide mode, the compactflash logic drives the read and write command signals of the smc on cfior and cfiow signals, while the cfoe and cfwe signals are deactivated. likewise, in common memory mode and attribute memory mode, the smc sig- nals are driven on the cfoe and cfwe signals, while the cfior and cfiow are deactivated. figure 20-4 on page 140 demonstrates a schematic representation of this logic. attribute memory mode, common memory mode and i/o mode are supported by setting the address setup and hold time on the ncs4 (and/or ncs5) chip select to the appropriate values. table 20-6. cfce1 and cfce2 truth table mode cfce2 cfce1 dbw comment smc access mode attribute memory nbs1 nbs0 16 bits access to even byte on d[7:0] byte select common memory nbs1 nbs0 16bits access to even byte on d[7:0] access to odd byte on d[15:8] byte select 1 0 8 bits access to odd byte on d[7:0] don?t care i/o mode nbs1 nbs0 16 bits access to even byte on d[7:0] access to odd byte on d[15:8] byte select 1 0 8 bits access to odd byte on d[7:0] don?t care true ide mode task file 1 0 8 bits access to even byte on d[7:0] access to odd byte on d[7:0] don?t care data register 1 0 16 bits access to even byte on d[7:0] access to odd byte on d[15:8] byte select alternate true ide mode control register alternate status read 01 don?t care access to even byte on d[7:0] don?t care drive address 0 1 8 bits access to odd byte on d[7:0] don?t care true ide standby mode or address space is not assigned to cf 11 don?t care don?t care don?t care 140 6062b?atarm?15-nov-05 at91sam9261 figure 20-4. compactflash read/write control signals 20.6.5.4 multiplexing of compactflash signals on ebi pins table 20-8 on page 140 and table 20-9 on page 141 illustrate the multiplexing of the com- pactflash logic signals with other ebi signals on the ebi pins. the ebi pins in table 20-8 are strictly dedicated to the compactflash interface as soon as the cs4a and/or cs5a field of the ebi_csa register is set. these pins must not be used to drive any other memory devices. the ebi pins in table 20-9 on page 141 remain shared between all memory areas when the corresponding compactflash interface is enabled (cs4a = 1 and/or cs5a = 1). smc nrd nwr0_nwe a21 cfior cfiow cfoe cfwe 1 1 compactflash logic external bus interface 1 1 1 0 a20 1 0 1 0 1 0 table 20-7. compactflash mode selection mode base address cfoe cfwe cfior cfiow attribute memory common memory nrd nwr0_nwe 1 1 i/o mode 1 1 nrd nwr0_nwe true ide mode 0 1 nrd nwr0_nwe table 20-8. dedicated compactflash interface multiplexing pins compactflash sign als ebi signals cs4a = 1 cs5a = 1 cs4a = 0 cs5a = 0 ncs4/cfcs0 cfcs0 ncs4 ncs5/cfcs1 cfcs1 ncs5 141 6062b?atarm?15-nov-05 at91sam9261 20.6.5.5 application example figure 20-5 on page 142 illustrates an example of a compactflash application. cfcs0 and cfrnw signals are not directly connected to the compactflash slot 0, but do control the direction and the output enable of the buffers between the ebi and the compactflash device. the timing of the cfcs0 signal is identical to the ncs4 signal. moreover, the cfrnw signal remains valid throughout the transfer, as does the address bus. the compactflash _wait signal is connected to the nwait input of the static memory controller. for details on these waveforms and timings, refer to the static memory controller section. table 20-9. shared compactflash interface mu ltiplexing pins access to compactfl ash device access to other ebi devices compactflash sign als ebi signals nrd/cfoe cfoe nrd nwr0/nwe/cfwe cfwe nwr0/nwe nwr1/nbs1/cfior cfior nwr1/nbs1 nwr3/nbs3/cfiow cfiow nwr3/nbs3 a25/cfrnw cfrnw a25 142 6062b?atarm?15-nov-05 at91sam9261 figure 20-5. compactflash application example 20.6.6 nand flash support the ebi integrates circuitry that interfaces to nand flash devices. the nand flash logic is driven by the static memory controller on the ncs3 address space. programming the cs3a field in the ebi_csa register in the bus matrix user interface to the appropriate value enables the nand flash logic. fo r details on this register, refer to the bus matrix user interface section. access to an external nand flash device is then made by accessing the address space reserved to ncs3 (i.e., between 0x40000000 and 0x4fff ffff). the nand flash logic drives the read and write command signals of the smc on the nan- doe and nandwe signals when the ncs3 si gnal is active. nandoe and nandwe are invalidated as soon as the transfer address fails to lie in the ncs3 address space. for details on these waveforms, refer to the static memory controller section. the nandoe and nandwe signals are multiple xed with ncs6 and ncs7 signals of the static memory controller. this mu ltiplexing is controlled in the mux logic part of the ebi by the cs3a bit in the in the ebi_csa register for de tails on this register, refer to the bus matrix user interface section. ncs6 and ncs7 become unavailable. performing an access within the address space reserved to ncs6 and ncs7 (i.e., between 0x70000000 and 0x8fff ffff) may lead to an unpredictable outcome. compactflash connecto r ebi d[15:0] /oe dir _cd1 _cd2 /oe d[15:0] a25/cfrnw ncs4/cfcs0 cd (pio) a[10:0] a22/reg nrd/cfoe a[10:0] _reg _oe _we _iord _iowr _ce1 _ce2 nwe/cfwe nwr1/cfior nwr3/cfiow cfce1 cfce2 _wait nwait 143 6062b?atarm?15-nov-05 at91sam9261 figure 20-6. nand flash signal multiplexing on ebi pins the address latch enable and command latch enable signals on the nand flash device are driven by address bits a22 and a21 of the ebi ad dress bus. the user should note that any bit on the ebi address bus can also be used for this purpose. the command, address or data words on the data bus of the nand flash device are distinguished by using their address within the ncs3 address space. the chip enable (ce) signal of the device and the ready/busy (r/b) signals are connected to pio lines. the ce signal then remains asserted even when ncs3 is not selected, preventing the device from returning to standby mode. smc nrd nwr0_nwe nandoe nandwe nand flash logic ncs3 mux logic cs3a ncs7_nandw e ncs6_nando e cs3a ncs7 ncs6 144 6062b?atarm?15-nov-05 at91sam9261 figure 20-7. nand flash application example note: the external bus interface is also able to support 16-bits devices. d[7:0] ale ncs7/nandwe ncs6/nandoe noe nwe a[22:21] cle ad[7:0] pio r/b ebi ce nand flash pio ncs3/nandcs not connected 145 6062b?atarm?15-nov-05 at91sam9261 21. static memory controller (smc) 21.1 overview the static memory controller (smc) generates the signals that control the access to the external memory devices or peripheral devices . it has 8 chip selects and a 26-bit address bus. the 32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. separate read and write control signals allow for direct memory and peripheral interfacing. read and write signal waveforms are fully parametrizable. the smc can manage wait requests from exter nal devices to extend the current access. the smc is provided with an automatic slow clock mode. in slow clock mode, it switches from user-programmed waveforms to slow-rate specific waveforms on read and write signals. the smc supports asynchronous burst read in page mode access for page size up to 32 bytes. 21.2 block diagram figure 21-1. smc block diagram bus matrix apb ncs[7:0] nwr0/nwe nwait smc pio controller a0/nbs0 nrd nwr1/nbs1 a1/nwr2/nbs2 nwr3/nbs3 a[25:2] user interface pmc mck d[31:0] smc chip select 146 6062b?atarm?15-nov-05 at91sam9261 21.3 i/o lines description 21.4 multiplexed signals table 21-1. i/o line description name description type active level ncs[7:0] static memory controller chip select lines output low nrd read signal output low nwr0/nwe write 0/write enable signal output low a0/nbs0 address bit 0/byte 0 select signal output low nwr1/nbs1 write 1/byte 1 select signal output low a1/nwr2/nbs2 address bit 1/write 2/byte 2 select signal output low nwr3/nbs3 write 3/byte 3 select signal output low a[25:2] address bus output d[31:0] data bus i/o nwait external wait signal input low table 21-2. static memory controller (smc) multiplexed signals multiplexed signal s related function nwr0 nwe byte-write or byte-select access, see ?byte write or byte select access? on page 148 a0 nbs0 8-bit or 16-/32-bit data bus, see ?data bus width? on page 148 nwr1 nbs1 byte-write or byte-select access see ?byte write or byte sele ct access? on page 148 a1 nwr2 nbs2 8-/16-bit or 32-bit data bus, see ?data bus width? on page 148 . byte-write or byte-select access, see ?byte write or byte select access? on page 148 nwr3 nbs3 byte-write or byte-select access see ?byte write or byte sele ct access? on page 148 147 6062b?atarm?15-nov-05 at91sam9261 21.5 application example 21.5.1 hardware interface figure 21-2. smc connections to st atic memory devices 21.6 product dependencies 21.6.1 i/o lines the pins used for interfacing the static memory controller may be multiplexed with the pio lines. the programmer must first program the pio controller to assign the static memory con- troller pins to their peripheral function. if i/o lines of the smc are not used by the application, they can be used for other putposes by the pio controller. static memory controller d0-d31 a2 - a25 a0/nbs0 nwr0/nwe nwr1/nbs1 a1/nwr2/nbs2 nwr3/nbs3 128k x 8 sram d0 - d7 a0 - a16 oe we cs d0 - d7 d8-d15 a2 - a18 128k x 8 sram d0-d7 cs d16 - d23 d24-d31 128k x 8 sram d0-d7 cs nwr1/nbs1 nwr3/nbs3 nrd nwr0/nwe 128k x 8 sram d0 - d7 oe we cs nrd a1/nwr2/nbs2 ncs0 ncs1 ncs2 ncs3 ncs4 ncs5 ncs6 ncs7 a2 - a18 a0 - a16 nrd oe we oe we nrd a2 - a18 a0 - a16 a2 - a18 a0 - a16 148 6062b?atarm?15-nov-05 at91sam9261 21.7 external memory mapping the smc provides up to 26 address lines, a[25:0]. this allows each chip select line to address up to 64 mbytes of memory. if the physical memory device connected on one chip select is smaller than 64 mbytes, it wraps around and appears to be repeated within this space. the smc correctly handles any valid access to the memory device within the page (see figure 21-1 ). a[25:0] is only significant for 8-bit memory, a[25:1] is used for 16-bit memory, a[25:2] is used for 32-bit memory. figure 21-3. memory connections for eight external devices 21.8 connection to external devices 21.8.1 data bus width a data bus width of 8, 16, or 32 bits can be selected for each chip select. this option is con- trolled by the field dbw in smc_mode (mode register) for the corresponding chip select. figure 21-4 shows how to connect a 512k x 8-bit memory on ncs2. figure 21-5 shows how to connect a 512k x 16-bit memory on ncs2. figure 21-6 shows two 16-bit memories con- nected as a single 32-bit memory 21.8.2 byte write or byte select access each chip select with a 16-bit or 32-bit data bus can operate with one of two different types of write access: byte write or byte select access . this is controlled by the bat field of the smc_mode register for the corresponding chip select. nrd nwe a[25:0] d[31:0] 8 or 16 or 32 memory enable memory enable memory enable memory enable memory enable memory enable memory enable memory enable output enable write enable a[25:0] d[31:0] or d[15:0] or d[7:0] ncs3 ncs0 ncs1 ncs2 ncs7 ncs4 ncs5 ncs6 ncs[0] - ncs[7] smc 149 6062b?atarm?15-nov-05 at91sam9261 figure 21-4. memory connection for an 8-bit data bus figure 21-5. memory connection for a 16-bit data bus figure 21-6. memory connection for a 32-bit data bus smc a0 nwe nrd ncs[2] a0 write enable output enable memory enable d[7:0] d[7:0] a[18:2] a[18:2] a1 a1 smc nbs0 nwe nrd ncs[2] low byte enable write enable output enable memory enable nbs1 high byte enable d[15:0] d[15:0] a[19:2] a[18:1] a[0] a1 d[31:16] smc nbs0 nwe nrd ncs[2] nbs1 d[15:0] a[20:2] d[31:16] nbs2 nbs3 byte 0 enable write enable output enable memory enable byte 1 enable d[15:0] a[18:0] byte 2 enable byte 3 enable 150 6062b?atarm?15-nov-05 at91sam9261 21.8.2.1 byte write access byte write access supports one byte write signal per byte of the data bus and a single read signal. for 16-bit devices: the smc provides nwr0 and nwr1 write signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. one single read signal (nrd) is provided. byte write access is used to connect 2 x 8-bit devices as a 16-bit memory. for 32-bit devices: nwr0, nwr1, nwr2 and nwr3, are the write signals of byte0 (lower byte), byte1, byte2 and byte 3 (upper byte) respectively. one single read signal (nrd) is provided. byte write access is used to connect 4 x 8-bit devices as a 32-bit memory. byte write option is illustrated on figure 21-7 . 21.8.2.2 byte select access in this mode, read/write operations can be enabl ed/disabled at a byte level. one byte-select line per byte of the data bus is provided. one nrd and one nwe signal control read and write. for 16-bit devices: the smc provides nbs0 and nbs1 selection signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. byte select access is used to connect one 16-bit device. for 32-bit devices: nbs0, nbs1, nbs2 and nbs3, are the selection signals of byte0 (lower byte), byte1, byte2 and byte 3 (upper byte) respectively. byte select access is used to connect two 16-bit devices. figure 21-8 shows how to connect two 16-bit devices on a 32-bit data bus in byte select access mode, on ncs3 (bat = byte select access). 151 6062b?atarm?15-nov-05 at91sam9261 figure 21-7. connection of 2 x 8-bit devices on a 16-bit bus: byte write option 21.8.2.3 signal multiplexing depending on the bat, only the write signals or the byte select signals are used. to save ios at the external bus interface, control signals at the smc interface are multiplexed. table 21-3 shows signal multiplexing depending on the data bus width and the byte access type. for 32-bit devices, bits a0 and a1 are unused. for 16-bit devices, bit a0 of address is unused. when byte select option is selected, nwr1 to nwr3 are unused. when byte write option is selected, nbs0 to nbs3 are unused. smc a1 nwr0 nrd ncs[3] write enable read enable memory enable nwr1 write enable read enable memory enable d[7:0] d[7:0] d[15:8] d[15:8] a[24:2] a[23:1] a[23:1] a[0] a[0] 152 6062b?atarm?15-nov-05 at91sam9261 figure 21-8. connection of 2x16-bit data bus on a 32-bit data bus (byte select option) 21.9 standard read and write protocols in the following sections, the byte access type is not considered. byte select lines (nbs0 to nbs3) always have the same timing as the a address bus. nwe represents either the nwe signal in byte select access type or one of the byte write lines (nwr0 to nwr3) in byte write access type. nwr0 to nwr3 have the same timings and protocol as nwe. in the same way, ncs represents one of the ncs[0..7] chip select lines. smc nwe nrd ncs[3] write enable read enable memory enable nbs0 d[15:0] d[15:0] d[31:16] a[25:2] a[23:0] write enable read enable memory enable d[31:16] a[23:0] low byte enable high byte enable low byte enable high byte enable nbs1 nbs2 nbs3 table 21-3. smc multiplexed signal translation signal name 32-bit bus 16-bit bus 8-bit bus device type 1x32-bit 2x16-bit 4 x 8- bit 1x16-bit 2 x 8-bit 1 x 8-bit byte access type (bat) byte select byte select byte write byte select byte write nbs0_a0 nbs0 nbs0 nbs0 a0 nwe_nwr0 nwe nwe nwr0 nwe nwr0 nwe nbs1_nwr1 nbs1 nbs1 nwr1 nbs1 nwr1 nbs2_nwr2_a1 nbs2 nbs2 nwr2 a1 a1 a1 nbs3_nwr3 nbs3 nbs3 nwr3 153 6062b?atarm?15-nov-05 at91sam9261 21.9.1 read waveforms the read cycle is shown on figure 21-9 . the read cycle starts with the address setting on the memory address bus, i.e.: {a[25:2], a1, a0} for 8-bit devices {a[25:2], a1} for 16-bit devices a[25:2] for 32-bit devices. figure 21-9. standard read cycle 21.9.1.1 nrd waveform the nrd signal is characterized by a setu p timing, a pulse width and a hold timing. a. nrd_setup: the nrd setup time is defined as the setup of address before the nrd falling edge; b. nrd_pulse: the nrd pulse length is the time between nrd falling edge and nrd rising edge; c. nrd_hold: the nrd hold time is defined as the hold time of address after the nrd rising edge. a[25:2] nbs0,nbs1, nbs2,nbs3, a0, a1 ncs nrd_setup nrd_pulse nrd_hold mck nrd d[31:0] ncs_rd_setup ncs_rd_pulse ncs_rd_hold nrd_cycle 154 6062b?atarm?15-nov-05 at91sam9261 21.9.1.2 ncs waveform similarly, the ncs signal can be divided into a setup time, pulse length and hold time: a. ncs_rd_setup: the ncs setup time is defined as the setup time of address before the ncs falling edge. b. ncs_rd_pulse: the ncs pulse length is the time between ncs falling edge and ncs rising edge; c. ncs_rd_hold: the ncs hold time is defin ed as the hold time of address after the ncs rising edge. 21.9.1.3 read cycle the nrd_cycle time is defined as the total durat ion of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change. the total read cycle time is equal to: nrd_cycle = nrd_setup + nrd_pulse + nrd_hold = ncs_rd_setup + ncs_rd_pulse + ncs_rd_hold all nrd and ncs timings are defined separately for each chip select as an integer number of master clock cycles. to ensure that the nrd a nd ncs timings are coherent, user must define the total read cycle instead of the hold timi ng. nrd_cycle implicitly defines the nrd hold time and ncs hold time as: nrd_hold = nrd_cycle - nrd setup - nrd pulse ncs_rd_hold = nrd_cycle - ncs_rd_setup - ncs_rd_pulse 21.9.1.4 null delay setup and hold if null setup and hold parameters are programmed for nrd and/or ncs, nrd and ncs remain active continuously in case of cons ecutive read cycles in the same memory (see fig- ure 21-10 ). 155 6062b?atarm?15-nov-05 at91sam9261 figure 21-10. no setup, no hold on nrd and ncs read signals 21.9.1.5 null pulse programming null pulse is not permitted. pulse must be at least set to 1. a null value leads to unpredictable behavior. 21.9.2 read mode as ncs and nrd waveforms are defined independently of one other, the smc needs to know when the read data is available on the data bus. the smc does not compare ncs and nrd timings to know which signal rises first. the read_mode parameter in the smc_mode reg- ister of the corresponding chip select indicates which signal of nrd and ncs controls the read operation. 21.9.2.1 read is controlled by nrd (read_mode = 1): figure 21-11 shows the waveforms of a read operation of a typical asynchronous ram. the read data is available t pacc after the falling edge of nrd, and tu rns to ?z? after the rising edge of nrd. in this case, the read_mode must be set to 1 (read is controlled by nrd), to indi- cate that data is available with the risi ng edge of nrd. the smc samples the read data internally on the rising edge of master clock that generates the rising edge of nrd, whatever the programmed waveform of ncs may be. mck nrd_pulse ncs_rd_pulse nrd_cycle nrd_pulse nrd_pulse ncs_rd_pulse ncs_rd_pulse nrd_cycle nrd_cycle a[25:2] nbs0,nbs1, nbs2,nbs3, a0, a1 ncs nrd d[31:0] 156 6062b?atarm?15-nov-05 at91sam9261 figure 21-11. read_mode = 1: data is sampled by smc before the rising edge of nrd 21.9.2.2 read is controlled by ncs (read_mode = 0) figure 21-12 shows the typical read cycle of an lcd module. the read data is valid t pacc after the falling edge of the ncs signal and remains valid until the rising edge of ncs. data must be sampled when ncs is raised. in that case, the read_mode must be set to 0 (read is con- trolled by ncs): the smc internally samples t he data on the rising edge of master clock that generates the rising edge of ncs, whatever the progra mmed waveform of nrd may be. figure 21-12. read_mode = 0: data is sampled by smc before the rising edge of ncs data sampling t pacc mck a[25:2] nbs0,nbs1, nbs2,nbs3, a0, a1 ncs nrd d[31:0] data sampling t pacc mck d[31:0] a[25:2] nbs0,nbs1, nbs2,nbs3, a0, a1 ncs nrd 157 6062b?atarm?15-nov-05 at91sam9261 21.9.3 write waveforms the write protocol is similar to the read protocol. it is depicted in figure 21-13 . the write cycle starts with the address setting on the memory address bus. 21.9.3.1 nwe waveforms the nwe signal is characterized by a setu p timing, a pulse width and a hold timing. a. nwe_setup: the nwe setup time is defined as the setup of address and data before the nwe falling edge; b. nwe_pulse: the nwe pulse length is the time between nwe falling edge and nwe rising edge; c. nwe_hold: the nwe hold time is defined as the hold time of address and data after the nwe rising edge. the nwe waveforms apply to all byte-write lines in byte write access mode: nwr0 to nwr3. 21.9.3.2 ncs waveforms the ncs signal waveforms in write operation are not the same that those applied in read operations, but are separately defined: a. ncs_wr_setup: the ncs setup time is defined as the setup time of address before the ncs falling edge. b. ncs_wr_pulse: the ncs pulse length is the time between ncs falling edge and ncs rising edge; c. ncs_wr_hold: the ncs hold time is defined as the hold time of address after the ncs rising edge. figure 21-13. write cycle a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1 ncs nwe_setup nwe_pulse nwe_hold mck nwe ncs_wr_setup ncs_wr_pulse ncs_wr_hold nwe_cycle 158 6062b?atarm?15-nov-05 at91sam9261 21.9.3.3 write cycle the write_cycle time is defined as the total dura tion of the write cycle, that is, from the time where address is set on the address bus to the point where address may change. the total write cycle time is equal to: nwe_cycle = nwe_setup + nwe_pulse + nwe_hold = ncs_wr_setup + ncs_wr_pulse + ncs_wr_hold all nwe and ncs (write) timings are defined separa tely for each chip select as an integer number of master clock cycles. to ensure that the nwe and ncs timings are coherent, the user must define the total write cycle instead of the hold timing. this im plicitly defines the nwe hold time and ncs (write) hold times as: nwe_hold = nwe_cycle - nwe_setup - nwe_pulse ncs_wr_hold = nwe_cycle - ncs_wr_setup - ncs_wr_pulse 21.9.3.4 null delay setup and hold if null setup parameters are programmed for nwe and/or ncs, nwe and/or ncs remain active continuously in case of consecut ive write cycles in the same memory (see figure 21- 14 ). however, for devices that perform write operations on the rising edge of nwe or ncs, such as sram, either a setup or a hold must be programmed. figure 21-14. null setup and hold values of ncs and nwe in write cycle 21.9.3.5 null pulse programming null pulse is not permitted. pulse must be at least set to 1. a null value leads to unpredictable behavior. ncs mck nwe, nwr0, nwr1, nwr2, nwr3 d[31:0] nwe_pulse ncs_wr_pulse nwe_cycle nwe_pulse ncs_wr_pulse nwe_cycle nwe_pulse ncs_wr_pulse nwe_cycle a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1 159 6062b?atarm?15-nov-05 at91sam9261 21.9.4 write mode the write_mode parameter in the smc_mode register of the corresponding chip select indicates which signal cont rols the write operation. 21.9.4.1 write is controlled by nwe (write_mode = 1): figure 21-15 shows the waveforms of a write operation with write_mode set to 1. the data is put on the bus during the pulse and hold steps of the nwe signal. the internal data buffers are turned out after the nwe_setup time, and unt il the end of the write cycle, regardless of the programmed waveform on ncs. figure 21-15. write_mode = 1. the write ope ration is controlled by nwe 21.9.4.2 write is controlle d by ncs (write_mode = 0) figure 21-16 shows the waveforms of a write operation with write_mode set to 0. the data is put on the bus during the pulse and hold steps of the ncs signal. the internal data buffers are turned out after the ncs_wr_setup time, and until the end of the write cycle, regardless of the programmed waveform on nwe. mck d[31:0] ncs a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1 nwe, nwr0, nwr1, nwr2, nwr3 160 6062b?atarm?15-nov-05 at91sam9261 figure 21-16. write_mode = 0. the write ope ration is controlled by ncs 21.9.5 coding timing parameters all timing parameters are defined for one chip select and are grouped together in one smc_register according to their type. the smc_setup register groups the definition of all setup parameters: nrd_setup, ncs_rd_setup, nwe_setup, ncs_wr_setup the smc_pulse register groups the definition of all pulse parameters: nrd_pulse, ncs_rd_pulse, nwe_pulse, ncs_wr_pulse the smc_cycle register groups the definition of all cycle parameters: nrd_cycle, nwe_cycle table 21-4 shows how the timing parameters are coded and their permitted range. mck d[31:0] ncs nwe, nwr0, nwr1, nwr2, nwr3 a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1 table 21-4. coding and range of timing parameters coded value number of bits effective value permitted range coded value effective value setup [5:0] 6 128 x setup[5] + setup[4:0] 0 31 128 128+31 pulse [6:0] 7 256 x pulse[6] + pulse[5:0] 0 63 256 256+63 cycle [8:0] 9 256 x cycle[8:7] + cycle[6:0] 0 127 256 256+127 512 512+127 768 768+127 161 6062b?atarm?15-nov-05 at91sam9261 21.9.6 reset values of timing parameters table 21-5 gives the default value of timing parameters at reset. 21.9.7 usage restriction the smc does not check the validity of the user-programmed parameters. if the sum of setup and pulse parameters is larger than the corresponding cycle parameter, this leads to unpredictable behavior of the smc. for read operations: null but positive setup and hold of address and nrd and/or ncs can not be guaranteed at the memory interface because of the propagation delay of theses signals through external logic and pads. if positive setup and hold values must be verified, then it is strictly recommended to program non-null values so as to cover possible skews between address, ncs and nrd signals. for write operations: if a null hold value is programmed on nwe, the smc can guarantee a positive hold of address, byte select lines, and ncs signal after the rising edge of nwe. this is true for write_mode = 1 only. see ?early read wait state? on page 162 . for read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable behavior. in read and write cycles, the setup and hold time parameters are defined in reference to the address bus. for external devices that requ ire setup and hold time between ncs and nrd signals (read), or between ncs and nwe signals (write), these setup and hold times must be converted into setup and hold times in reference to the address bus. 21.10 automatic wait states under certain circumstances, the smc automatical ly inserts idle cycles between accesses to avoid bus contention or operation conflict. 21.10.1 chip select wait states the smc always inserts an idle cycle between 2 tr ansfers on separate chip selects. this idle cycle ensures that there is no bus contention between the de-activation of one device and the activation of the next one. during chip select wait state, all control lines are turned inactive: nbs0 to nbs3, nwr0 to nwr3, ncs[0..7], nrd lines are all set to 1. table 21-5. reset values of timing parameters register reset value smc_setup 0x01010101 all setup timings are set to 1 smc_pulse 0x01010101 all pulse timings are set to 1 smc_cycle 0x00030003 the read and write operation last 3 master clock cycles and provide one hold cycle write_mode 1 write is controlled with nwe read_mode 1 read is controlled with nrd 162 6062b?atarm?15-nov-05 at91sam9261 figure 21-17 illustrates a chip select wait state between access on chip select 0 and chip select 2. figure 21-17. chip select wait state between a read access on ncs0 and a write access on ncs2 21.10.2 early read wait state in some cases, the smc inserts a wait stat e cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. this wait state is not generated in addition to a chip sele ct wait state. the early read cycle thus only occurs between a write and read access to the same memory device (same chip select). an early read wait state is automatically inserted if at least one of the following conditions is valid: if the write controlling signal has no hold time and the read controlling signal has no setup time ( figure 21-18 ). in ncs write controlled mode (write_mode = 0), if there is no hold timing on the ncs signal and the ncs_rd_setup parameter is set to 0, regardless of the read mode ( figure 21-19 ). the write operation must end with a ncs rising edge. without an early read wait state, the write operation could not complete properly. in nwe controlled mode (write_mode = 1) and if there is no hold timing (nwe_hold = 0), the feedback of the write control signal is used to control address, data, chip select and byte select lines. if the external write control signal is not inactivated as expected due to load capacitances, an early read wait state is inserted and address, data and control signals are maintained one more cycle. see figure 21-20 . a[25:2] nbs0, nbs1, nbs2, nbs3, a0,a1 ncs0 nrd_cycle chip select wait state nwe_cycle mck ncs2 nrd nwe d[31:0] read to write wait state 163 6062b?atarm?15-nov-05 at91sam9261 figure 21-18. early read wait state: write with no hold followe d by read with no setup figure 21-19. early read wait state: ncs cont rolled write with no hold followed by a read with no ncs setup write cycle early read wait state mck nrd nwe read cycle no setup no hold d[31:0] nbs0, nbs1, nbs2, nbs3, a0, a1 a[25:2] write cycle (write_mode = 0) early read wait state mck nrd ncs read cycle (read_mode = 0 or read_mode = 1) no setup no hold d[31:0] nbs0, nbs1, nbs2, nbs3, a0,a1 a[25:2] 164 6062b?atarm?15-nov-05 at91sam9261 figure 21-20. early read wait state: nwe-controlled write with no hold followed by a read with one set-up cycle 21.10.3 reload user configuration wait state the user may change any of the configuration parameters by writing the smc user interface. when detecting that a new user configuration has been written in the user interface, the smc inserts a wait state before starting the next access. the so called ?reload user configuration wait state? is used by the smc to load the new set of parameters to apply to next accesses. the reload configuration wait state is not applied in addition to the chip select wait state. if accesses before and after re-programming the user interface are made to different devices (chip selects), then one single chip select wait state is applied. on the other hand, if accesses before and after writing the user interface are made to the same device, a reload configuration wait state is inserted, even if the change does not con- cern the current chip select. 21.10.3.1 user procedure to insert a reload configuration wait state, the smc detects a write access to any smc_mode register of the user interface. if the user only modifies timing registers (smc_setup, smc_pulse, smc_cycle registers) in the user interface, he must validate the modification by writing the smc_mode, even if no change was made on the mode parameters. 21.10.3.2 slow clock mode transition a reload configuration wait state is also in serted when the slow clock mode is entered or exited, after the end of the current transfer (see ?slow clock mode? on page 175 ). a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1 write cycle (write_mode = 1) early read wait state mck nrd internal write controlling signal external write controlling signal (nwe) d[31:0] read cycle (read_mode = 0 or read_mode = 1) no hold read setup = 1 165 6062b?atarm?15-nov-05 at91sam9261 21.10.4 read to write wait state due to an internal mechanism, a wait cycle is always inserted between consecutive read and write smc accesses. this wait cycle is referred to as a read to write wait stat e in this document. this wait cycle is applied in addition to chip se lect and reload user configuration wait states when they are to be inserted. see figure 21-17 on page 162 . 21.11 data float wait states some memory devices are slow to release the ex ternal bus. for such devices, it is necessary to add wait states (data float wait states) after a read access: before starting a read access to a different external memory before starting a write access to the same device or to a different external one. the data float output time (t df ) for each external memory device is programmed in the tdf_cycles field of the smc_mode register for the corresponding chip select. the value of tdf_cycles indicates the number of data float wait cycles (between 0 and 15) before the external device releases the bus, and represents the time allowed for the data output to go to high impedance after the memory is disabled. data float wait states do not delay internal memory accesses. hence, a single access to an external memory with long t df will not slow down the execution of a program from internal memory. the data float wait states management depends on the read_mode and the tdf_mode fields of the smc_mode register for the corresponding chip select. 21.11.1 read_mode setting the read_mode to 1 indicates to the smc that the nrd signal is responsible for turning off the tri-state buffers of the external memory device. the data float period then begins after the rising edge of the nrd signal and lasts tdf_cycles mck cycles. when the read operation is controlled by the ncs signal (read_mode = 0), the tdf field gives the number of mck cycles during which the data bus remains busy after the rising edge of ncs. figure 21-21 illustrates the data float period in nrd-controlled mode (read_mode =1), assuming a data float period of 2 cycles (tdf_cycles = 2). figure 21-22 shows the read operation when controlled by ncs (read_mode = 0) and the tdf_cycles parameter equals 3. 166 6062b?atarm?15-nov-05 at91sam9261 figure 21-21. tdf period in nrd controlled read access (tdf = 2) figure 21-22. tdf period in ncs controlled read operation (tdf = 3) nbs0, nbs1, nbs2, nbs3, a0, a1 ncs nrd controlled read operation tpacc mck nrd d[31:0] tdf = 2 clock cycles a[25:2] ncs tdf = 3 clock cycles tpacc mck d[31:0] ncs controlled read operation a[25:2] nbs0, nbs1, nbs2, nbs3, a0,a1 nrd 167 6062b?atarm?15-nov-05 at91sam9261 21.11.2 tdf optimization enabled (tdf_mode = 1) when the tdf_mode of the smc_mode register is set to 1 (tdf optimization is enabled), the smc takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert. figure 21-23 shows a read access controlled by nrd, followed by a write access controlled by nwe, on chip select 0. chip se lect 0 has been programmed with: nrd_hold = 4; read_mode = 1 (nrd controlled) nwe_setup = 3; write_mode = 1 (nwe controlled) tdf_cycles = 6; tdf_mode = 1 (optimization enabled). figure 21-23. tdf optimization: no tdf wait states are inserted if the tdf period is over when the next access begins 21.11.3 tdf optimization disabled (tdf_mode = 0) when optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that the data float period is ended when the second access begins. if the hold period of the read1 controlling signal overlaps the data float period, no additional tdf wait states will be inserted. figure 21-24 , figure 21-25 and figure 21-26 illustrate the cases: read access followed by a read access on another chip select, read access followed by a write access on another chip select, read access followed by a write access on the same chip select, with no tdf optimization. a [25:2] ncs0 mck nrd nwe d[31:0] read to write wait state tdf_cycles = 6 read access on ncs0 (nrd controlled) nrd_hold= 4 nwe_setup= 3 write access on ncs0 (nwe controlled) 168 6062b?atarm?15-nov-05 at91sam9261 figure 21-24. tdf optimization disabled (tdf mode = 0). tdf wait states between 2 read accesses on different chip selects figure 21-25. tdf mode = 0: tdf wait states between a read and a write access on different chip selects tdf_cycles = 6 tdf_cycles = 6 tdf_mode = 0 (optimization disabled) a[ 25:2] read1 cycle chip select wait state mck read1 controlling signal (nrd) read2 controlling signal (nrd) d[31:0] read1 hold = 1 read 2 cycle read2 setup = 1 5 tdf wait states nbs0, nbs1, nbs2, nbs3, a0, a1 tdf_cycles = 4 tdf_cycles = 4 tdf_mode = 0 (optimization disabled) a [25:2] read1 cycle chip select wait state read to write wait state mck read1 controlling signal (nrd) write2 controlling signal (nwe) d[31:0] read1 hold = 1 write2 cycle write2 setup = 1 2 tdf wait states nbs0, nbs1, nbs2, nbs3, a0, a1 169 6062b?atarm?15-nov-05 at91sam9261 figure 21-26. tdf mode = 0: tdf wait states between read and write accesses on the same chip select 21.12 external wait any access can be extended by an external de vice using the nwait input signal of the smc. the exnw_mode field of the smc_mode register on the corresponding chip select must be set to either to ?10? (frozen mode) or ?11? (ready mode). when the exnw_mode is set to ?00? (disabled), the nwait signal is simply igno red on the corresponding chip select. the nwait signal delays the read or write operation in regards to the read or write controlling signal, depending on the read and write modes of the corresponding chip select. 21.12.1 restriction when one of the exnw_mode is enabled, it is mandatory to program at least one hold cycle for the read/write controlling signal. for that reason, the nwait signal cannot be used in page mode ( ?asynchronous page mode? on page 178 ), or in slow clock mode ( ?slow clock mode? on page 175 ). the nwait signal is assumed to be a response of the external device to the read/write request of the smc. then nwait is examined by the smc only in the pulse state of the read or write controlling signal. the assertion of the nwait signal outside the expe cted period has no impact on smc behavior. tdf_cycles = 5 tdf_cycles = 5 tdf_mode = 0 (optimization disabled) a [25:2] read1 cycle read to write wait state mck read1 controlling signal (nrd) write2 controlling signal (nwe) d[31:0] read1 hold = 1 write2 cycle write2 setup = 1 4 tdf wait states nbs0, nbs1, nbs2, nbs3, a0, a1 170 6062b?atarm?15-nov-05 at91sam9261 21.12.2 frozen mode when the external device assert s the nwait signal (active low), and after internal synchroni- zation of this signal, the smc state is frozen, i.e., smc internal counters are frozen, and all control signals remain unchanged. when the resy nchronized nwait signal is deasserted, the smc completes the access, resuming the access from the point where it was stopped. see figure 21-27 . this mode must be selected when the ex ternal device uses the nwait signal to delay the access and to freeze the smc. the assertion of the nwait sig nal outside the expected period is ignored as illustrated in fig- ure 21-28 . figure 21-27. write access with nwait assertion in frozen mode (exnw_mode = 10) exnw_mode = 10 (frozen) write_mode = 1 (nwe_controlled) nwe_pulse = 5 ncs_wr_pulse = 7 a [25:2] mck nwe ncs 432 1 110 1 4 5 63222210 write cycle d[31:0] nwait frozen state nbs0, nbs1, nbs2, nbs3, a0,a1 internally synchronized nwait signal 171 6062b?atarm?15-nov-05 at91sam9261 figure 21-28. read access with nwait assertion in frozen mode (exnw_mode = 10) exnw_mode = 10 (frozen) read_mode = 0 (ncs_controlled) nrd_pulse = 2, nrd_hold = 6 ncs_rd_pulse =5, ncs_rd_hold =3 a [25:2] mck ncs nrd 10 43 43 2 555 22 0 210 210 1 read cycle assertion is ignored nwait internally synchronized nwait signal frozen state nbs0, nbs1, nbs2, nbs3, a0,a1 172 6062b?atarm?15-nov-05 at91sam9261 21.12.3 ready mode in ready mode (exnw_mode = 11), the sm c behaves differently. normally, the smc begins the access by down counting the setup and pulse counters of th e read/write controlling signal. in the last cycle of the pulse phase, the resynchronized nwait signal is examined. if asserted, the smc suspends the access as shown in figure 21-29 and figure 21-30 . after deassertion, the access is completed: the hold step of the access is performed. this mode must be selected when the external device uses deassertion of the nwait signal to indicate its ability to comple te the read or write operation. if the nwait signal is deasserted before the end of the pulse, or asserted after the end of the pulse of the controlling read/write signal, it has no impact on the access length as shown in figure 21-30 . figure 21-29. nwait assertion in write access: ready mode (exnw_mode = 11) exnw_mode = 11 (ready mode) write_mode = 1 (nwe_controlled) nwe_pulse = 5 ncs_wr_pulse = 7 a [25:2] mck nwe ncs 432 1 00 0 4 5 6321110 write cycle d[31:0] nwait internally synchronized nwait signal wait state nbs0, nbs1, nbs2, nbs3, a0,a1 173 6062b?atarm?15-nov-05 at91sam9261 figure 21-30. nwait assertion in read access: ready mode (exnw_mode = 11) exnw_mode = 11(ready mode) read_mode = 0 (ncs_controlled) nrd_pulse = 7 ncs_rd_pulse =7 a[25:2] mck ncs nrd 4 5 63200 0 1 4 5 6321 1 read cycle assertion is ignored nwait internally synchronized nwait signal wait state assertion is ignored nbs0, nbs1, nbs2, nbs3, a0,a1 174 6062b?atarm?15-nov-05 at91sam9261 21.12.4 nwait latency and read/write timings there may be a latency between the assertion of the read/write controlling signal and the assertion of the nwait signal by the device. the programmed pulse length of the read/write controlling signal must be at leas t equal to this latency plus the 2 cycles of resynchronization + 1 cycle. otherwise, the smc may enter the hold state of the access without detecting the nwait signal assertion. this is true in frozen mode as well as in re ady mode. this is illus- trated on figure 21-31 . when exnw_mode is enabled (ready or frozen), the user must program a pulse length of the read and write controlling signal of at least: minimal pulse length = nwait latency + 2 resynchronization cycles + 1 cycle figure 21-31. nwait latency exnw_mode = 10 or 11 read_mode = 1 (nrd_controlled) nrd_pulse = 5 a [25:2] mck nrd 43 210 0 0 read cycle minimal pulse length nwait latency nwait intenally synchronized nwait signal wait state 2 cycle resynchronization nbs0, nbs1, nbs2, nbs3, a0,a1 175 6062b?atarm?15-nov-05 at91sam9261 21.13 slow clock mode the smc is able to automatically apply a set of ?slow clock mode? read/write waveforms when an internal signal driven by the power managem ent controller is asserted because mck has been turned to a very slow clock rate (typically 32khz clock rate). in this mode, the user-pro- grammed waveforms are ignored and the slow clock mode waveforms are applied. this mode is provided so as to avoid reprogramming the user interface with appropriate waveforms at very slow clock rate. when activated, the slow mode is active on all chip selects. 21.13.1 slow clock mode waveforms figure 21-32 illustrates the read and write operations in slow clock mode. they are valid on all chip selects. table 21-6 indicates the value of read and write parameters in slow clock mode. figure 21-32. read/write cycles in slow clock mode a[ 25:2] ncs 1 mck nwe 1 1 nwe_cycle = 3 a [25:2] mck nrd nrd_cycle = 2 1 1 ncs slow clock mode write slow clock mode read nbs0, nbs1, nbs2, nbs3, a0,a1 nbs0, nbs1, nbs2, nbs3, a0,a1 table 21-6. read and write timing parameters in slow clock mode read parameters duration (cycles) write parameters duration (cycles) nrd_setup 1 nwe_setup 1 nrd_pulse 1 nwe_pulse 1 ncs_rd_setup 0 ncs_wr_setup 0 ncs_rd_pulse 2 ncs_wr_pulse 3 nrd_cycle 2 nwe_cycle 3 176 6062b?atarm?15-nov-05 at91sam9261 21.13.2 switching from (to) slow clock mode to (from) normal mode when switching from slow clock mode to the normal mode, the current slow clock mode trans- fer is completed at high clock rate, with the set of slow clock mode parameters.see figure 21- 33 on page 176 . the external device may not be fa st enough to support such timings. figure 21-34 illustrates the recommended procedure to properly swit ch from one mode to the other. figure 21-33. clock rate transition occurs while the smc is performing a write operation a [25:2] ncs 1 mck nwe 1 1 nwe_cycle = 3 slow clock mode write slow clock mode internal signal from pmc 11 1 2 3 2 nwe_cycle = 7 normal mode write slow clock mode transition is detected: reload configuration wait state this write cycle finishes with the slow clock mode set of parameters after the clock rate transition slow clock mode write nbs0, nbs1, nbs2, nbs3, a0,a1 177 6062b?atarm?15-nov-05 at91sam9261 figure 21-34. recommended procedure to switch from slow clock mo de to normal mode or from normal mode to slow clock mode a [25:2] ncs 1 mck nwe 1 1 slow clock mode write slow clock mode internal signal from pmc 2 3 2 normal mode write idle state reload configuration wait state nbs0, nbs1, nbs2, nbs3, a0,a1 178 6062b?atarm?15-nov-05 at91sam9261 21.14 asynchronous page mode the smc supports asynchronous burst reads in page mode, providing that the page mode is enabled in the smc_mode register (pmen field). the page size must be configured in the smc_mode register (ps field) to 4, 8, 16 or 32 bytes. the page defines a set of consecutive bytes into memory. a 4-byte page (resp. 8-, 16-, 32- byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of mem- ory. the msb of data address defines the address of the page in memory, the lsb of address define the address of the data in the page as detailed in table 21-7 . with page mode memory devices, the first access to one page (t pa ) takes longer than the sub- sequent accesses to the page (t sa ) as shown in figure 21-35 . when in page mode, the smc enables the user to define different read timings for the first access within one page, and next accesses withi n the page. notes: 1. a denotes the address bus of the memory device 2. for 16-bit devices, the bit 0 of address is ignored. for 32-bit devices, bits [1:0] are ignored. 21.14.1 protocol and timings in page mode figure 21-35 shows the nrd and ncs timings in page mode access. figure 21-35. page mode read protocol (address msb and lsb are defined in table 21-7 ) the nrd and ncs signals are held low during al l read transfers, what ever the programmed values of the setup and hold timings in the user interface may be. moreover, the nrd and ncs timings are identical. the pul se length of the first access to the page is defined with the table 21-7. page address and data address within a page page size page address (1) data address in the page (2) 4 bytes a[25:2] a[1:0] 8 bytes a[25:3] a[2:0] 16 bytes a[25:4] a[3:0] 32 bytes a[25:5] a[4:0] a[msb] ncs mck nrd d[31:0] ncs_rd_pulse nrd_pulse nrd_pulse tsa tpa tsa a[lsb] 179 6062b?atarm?15-nov-05 at91sam9261 ncs_rd_pulse field of the smc_pulse register. the pulse length of subsequent accesses within the page are defined using the nrd_pulse parameter. in page mode, the programming of the read timings is described in table 21-8 : the smc does not check the coherency of ti mings. it will always apply the ncs_rd_pulse timings as page access timing (t pa ) and the nrd_pulse for accesses to the page (t sa ), even if the programmed value for t pa is shorter than the programmed value for t sa . 21.14.2 byte access type in page mode the byte access type configuration remains active in page mode. for 16-bit or 32-bit page mode devices that require byte selection signals, configure the bat field of the smc_register to 0 (byt e select access type). 21.14.3 page mode restriction the page mode is not compatible with the use of the nwait signal. using the page mode and the nwait signal may lead to unpredictable behavior. 21.14.4 sequential and non-sequential accesses if the chip select and the msb of addresses as defined in table 21-7 are identical, then the current access lies in the same page as the previous one, and no page break occurs. using this information, all data within the same page, sequential or not sequential, are accessed with a minimum access time (t sa ). figure 21-36 illustrates access to an 8-bit memory device in page mode, with 8-byte pages. access to d1 causes a page access with a long access time (t pa ). accesses to d3 and d7, though they are not sequential accesses, only require a short access time (t sa ). if the msb of addresses are different, the smc performs the access of a new page. in the same way, if the chip select is different from the previous access, a page break occurs. if two sequential accesses are made to the page mode memory, but separated by an other internal or external peripheral access, a page break occurs on the second access because the chip select of the device was dea sserted between both accesses. table 21-8. programming of read timings in page mode parameter value definition read_mode ?x? no impact ncs_rd_setup ?x? no impact ncs_rd_pulse t pa access time of firs t access to the page nrd_setup ?x? no impact nrd_pulse t sa access time of subsequent accesses in the page nrd_cycle ?x? no impact 180 6062b?atarm?15-nov-05 at91sam9261 figure 21-36. access to non-sequential data within the same page a [25:3] a[2], a1, a0 ncs mck nrd page address a1 a3 a7 d[7:0] ncs_rd_pulse nrd_pulse nrd_pulse d1 d3 d7 181 6062b?atarm?15-nov-05 at91sam9261 21.15 static memory contro ller (smc) user interface the smc is programmed using the registers listed in table 21-9 . for each chip select, a set of 4 registers is used to program the parameters of the external device connected on it. in table 21-9 , ?cs_number? denotes the chip select number. 16 bytes (0x10) are required per chip select. the user must complete writing the configur ation by writing any one of the smc_mode registers. table 21-9. smc register mapping offset register name access reset state 0x10 x cs_number + 0x00 smc setup r egister smc_setup read/write 0x00000000 0x10 x cs_number + 0x04 smc pulse register smc_pulse read/write 0x01010101 0x10 x cs_number + 0x08 smc cycle register smc_cycle read/write 0x00010001 0x10 x cs_number + 0x0c smc mode register smc_mode read/write 0x10001000 182 6062b?atarm?15-nov-05 at91sam9261 21.15.1 smc setup register register name: smc_setup[0 .. 7 ] access type: read/write nwe_setup: nwe setup length the nwe signal setup length is defined as: nwe setup length = (128* nwe_setup [5] + nwe_setup[4:0]) clock cycles ncs_wr_setup: ncs setup length in write access in write access, the ncs signal setup length is defined as: ncs setup length = (128* ncs_wr_setup [5] + ncs_wr_setup[4:0]) clock cycles nrd_setup: nrd setup length the nrd signal setup length is defined in clock cycles as: nrd setup length = (128* nrd_setup[5] + nrd_setup[4:0]) clock cycles ncs_rd_setup: ncs setup length in read access in read access, the ncs signal setup length is defined as: ncs setup length = (128* ncs_rd_setup [5] + ncs_rd_setup[4:0]) clock cycles 31 30 29 28 27 26 25 24 ? ? ncs_rd_setup 23 22 21 20 19 18 17 16 ? ? nrd_setup 15 14 13 12 11 10 9 8 ? ? ncs_wr_setup 76543210 ? ? nwe_setup 183 6062b?atarm?15-nov-05 at91sam9261 21.15.2 smc pulse register register name: smc_pulse[0.. 7 ] access type: read/write nwe_pulse: nwe pulse length the nwe signal pulse length is defined as: nwe pulse length = (256* nwe_pulse[6] + nwe_pulse[5:0]) clock cycles the nwe pulse length must be at least 1 clock cycle. ncs_wr_pulse: ncs pulse length in write access in write access, the ncs signal pulse length is defined as: ncs pulse length = (256* ncs_wr_pul se[6] + ncs_wr_pulse[5:0]) clock cycles the ncs pulse length must be at least 1 clock cycle. nrd_pulse: nrd pulse length in standard read access, the nrd signal pulse length is defined in clock cycles as: nrd pulse length = (256* nrd_pulse[ 6] + nrd_pulse[5:0]) clock cycles the nrd pulse length must be at least 1 clock cycle. in page mode read access, the nrd_pulse parameter defines the duration of the subsequent accesses in the page. ncs_rd_pulse: ncs pulse length in read access in standard read access, the ncs signal pulse length is defined as: ncs pulse length = (256* ncs_rd_pul se[6] + ncs_rd_pulse[5:0]) clock cycles the ncs pulse length must be at least 1 clock cycle. in page mode read access, the ncs_rd_pulse parameter defines the duration of the first access to one page. 31 30 29 28 27 26 25 24 ? ncs_rd_pulse 23 22 21 20 19 18 17 16 ? nrd_pulse 15 14 13 12 11 10 9 8 ? ncs_wr_pulse 76543210 ?nwe_pulse 184 6062b?atarm?15-nov-05 at91sam9261 21.15.3 smc cycle register register name: smc_cycle[0.. 7 ] access type: read/write nwe_cycle: total write cycle length the total write cycle length is the total du ration in clock cycles of the write cycle. it is equal to the sum of the setup, pul se and hold steps of the nwe and ncs signals. it is defined as: write cycle length = (nwe_cycle[8:7 ]*256 + nwe_cycle[6:0]) clock cycles nrd_cycle: total read cycle length the total read cycle length is the total duration in clock cycles of the read cycle. it is equal to the sum of the setup, pulse and hold steps of the nrd and ncs signals. it is defined as: read cycle length = (nrd_cycle[8:7] *256 + nrd_cycle[6:0]) clock cycles 31 30 29 28 27 26 25 24 ???????nrd_cycle 23 22 21 20 19 18 17 16 nrd_cycle 15 14 13 12 11 10 9 8 ???????nwe_cycle 76543210 nwe_cycle 185 6062b?atarm?15-nov-05 at91sam9261 21.15.4 smc mode register register name: smc_mode[0.. 7 ] access type: read/write read_mode: 1: the read operation is controlled by the nrd signal. ? if tdf cycles are programmed, the external bus is marked busy after the rising edge of nrd. ? if tdf optimization is enabled (tdf_mode =1), tdf wait states are inserted after the setup of nrd. 0: the read operation is controlled by the ncs signal. ? if tdf cycles are programmed, the external bus is marked busy after the rising edge of ncs. ? if tdf optimization is enabled (tdf_mode =1), tdf wait states are inserted after the setup of ncs. write_mode 1: the write operation is controlled by the nwe signal. ? if tdf optimization is enabled (tdf_mode =1), tdf wa it states will be inserted after the setup of nwe. 0: the write operation is controlled by the ncs signal. ? if tdf optimization is enabled (tdf_mode =1), tdf wa it states will be inserted after the setup of ncs. exnw_mode: nwait mode the nwait signal is used to extend the current read or write signal. it is only taken into account during the pulse phase of the read and writ e controlling signal. when the use of nwait is enable d, at least one cycle hold duration mu st be pro- grammed for the read and write controlling signal. disabled mode: the nwait input signal is ignored on the corresponding chip select. frozen mode: if asserted, the nwait signal freezes the current read or write cycle. after deassertion, the read/write cycle is resumed from the point where it was stopped. 31 30 29 28 27 26 25 24 ?? ps ???pmen 23 22 21 20 19 18 17 16 ? ? ? tdf_mode tdf_cycles 15 14 13 12 11 10 9 8 ?? dbw ???bat 76543210 ?? exnw_mode ?? write_mod e read_mode exnw_mode nwait mode 00disabled 01reserved 1 0 frozen mode 1 1 ready mode 186 6062b?atarm?15-nov-05 at91sam9261 ready mode: the nwait si gnal indicates the availa bility of the external device at t he end of the pulse of the controlling read or write signal, to complete the access. if high, the access normally completes. if low, the access is extended until nwait returns high. bat: byte access type this field is used only if dbw defines a 16- or 32-bit data bus. 1: byte write access type: ? write operation is controlled us ing ncs, nwr0, nwr1, nwr2, nwr3. ? read operation is controlled using ncs and nrd. 0: byte select access type: ? write operation is controlled using ncs, nwe, nbs0, nbs1, nbs2 and nbs3 ? read operation is controlled using ncs, nrd, nbs0, nbs1, nbs2 and nbs3 dbw: data bus width tdf_cycles: data float time this field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the read controlling signal. the smc always provide one full cycle of bus turnaround after the tdf_cycles period. the external bus cannot be used by another chip select during tdf_cycles + 1 cycles. from 0 up to 15 tdf_cycles can be set. tdf_mode: tdf optimization 1: tdf optimization is enabled. ? the number of tdf wait states is optimized using the setup period of the next read/write access. 0: tdf optimization is disabled. ? the number of tdf wait states is inserted before the next access begins. pmen: page mode enabled 1: asynchronous burst read in page mode is applied on the corresponding chip select. 0: standard read is applied. ps: page size if page mode is enabled, this field indicates the size of the page in bytes. dbw data bus width 008-bit bus 0116-bit bus 1032-bit bus 11reserved ps page size 0 0 4-byte page 0 1 8-byte page 1 0 16-byte page 1 1 32-byte page 187 6062b?atarm?15-nov-05 at91sam9261 22. sdram controller (sdramc) 22.1 description the sdram controller (sdramc) ex tends the memory capabilities of a chip by providing the interface to an external 16-bit or 32-bit sdram device. the page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. it supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. the sdram controller supports a read or write bu rst length of one location. it keeps track of the active row in each bank, thus maximizing sdram performance, e.g., the application may be placed in one bank and data in the other banks. so as to optimize performance, it is advis- able to avoid accessing different rows in the same bank. the sdram controller supports a cas latency of 1, 2 or 3 and optimizes the read access depending on the frequency. the different modes available - self-refresh, power-down and deep power-down modes - mini- mize power consumption on the sdram device. 22.2 block diagram figure 22-1. sdram controller block diagram memory controller apb sdramc interrupt sdck sdcs sdramc_a[12:0] sdramc pio controller ba[1:0] sdcke ras cas sdwe nbs[3:0] user interface pmc mck d[31:0] sdramc chip select 188 6062b?atarm?15-nov-05 at91sam9261 22.3 i/o lines description 22.4 application example 22.4.1 software interface the sdram address space is organized into banks, rows, and columns. the sdram control- ler allows mapping different memory types a ccording to the values set in the sdramc configuration register. the sdram controller?s function is to make the sdram device access protocol transparent to the user. table 22-2 to table 22-7 illustrate the sdram device memory mapping seen by the user in correlation with the device struct ure. various configur ations are illustrated. 22.4.1.1 32-bit memory data bus width table 22-1. i/o line description name description type active level sdck sdram clock output sdcke sdram clock enable output high sdcs sdram controller chip select output low ba[1:0] bank select signals output ras row signal output low cas column signal output low sdwe sdram write enable output low nbs[3:0] data mask enable signals output low sdramc_a[12:0] address bus output d[31:0] data bus i/o table 22-2. sdram configuration mapping: 2k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[10:0] column[7:0] m[1:0] bk[1:0] row[10:0] column[8:0] m[1:0] bk[1:0] row[10:0] column[9:0] m[1:0] bk[1:0] row[10:0] column[10:0] m[1:0] table 22-3. sdram configuration mapping: 4k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[11:0] column[7:0] m[1:0] bk[1:0] row[11:0] column[8:0] m[1:0] bk[1:0] row[11:0] column[9:0] m[1:0] bk[1:0] row[11:0] column[10:0] m[1:0] 189 6062b?atarm?15-nov-05 at91sam9261 notes: 1. m[1:0] is the byte address inside a 32-bit word. 2. bk[1] = ba1, bk[0] = ba0. 22.4.1.2 16-bit memory data bus width notes: 1. m0 is the byte address inside a 16-bit half-word. 2. bk[1] = ba1, bk[0] = ba0. table 22-4. sdram configuration mapping: 8k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[12:0] column[7:0] m[1:0] bk[1:0] row[12:0] column[8:0] m[1:0] bk[1:0] row[12:0] column[9:0] m[1:0] bk[1:0] row[12:0] column[10:0] m[1:0] table 22-5. sdram configuration mapping: 2k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[10:0] column[7:0] m0 bk[1:0] row[10:0] column[8:0] m0 bk[1:0] row[10:0] column[9:0] m0 bk[1:0] row[10:0] column[10:0] m0 table 22-6. sdram configuration mapping: 4k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[11:0] column[7:0] m0 bk[1:0] row[11:0] column[8:0] m0 bk[1:0] row[11:0] column[9:0] m0 bk[1:0] row[11:0] column[10:0] m0 table 22-7. sdram configuration mapping: 8k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[12:0] column[7:0] m0 bk[1:0] row[12:0] column[8:0] m0 bk[1:0] row[12:0] column[9:0] m0 bk[1:0] row[12:0] column[10:0] m0 190 6062b?atarm?15-nov-05 at91sam9261 22.5 product dependencies 22.5.1 sdram device initialization the initialization sequence is generated by software. the sdram devices are initialized by the following sequence: 1. sdram features must be set in the configuration register: asynchronous timings (trc, tras, etc.), number of column, rows, cas latency, and the data bus width. 2. for mobile sdram, temperature-compensated self refresh (tcsr), drive strength (ds) and partial array self refresh (pasr) must be set in the low power register. 3. the sdram memory type must be set in the memory device register. 4. a minimum pause of 200 s is provided to precede any signal toggle. 5. an all banks precharge command is issued to the sdram devices. the application must set mode to 2 in the mode register and perform a write access to any sdram address. 6. eight auto-refresh (cbr) cycles are provided. the application must set the mode to 4 in the mode register and performs a write access to any sdram location height times. 7. a mode register set (mrs) cycle is issued to program the parameters of the sdram devices, in particular cas latency and burst length. the application must set mode to 3 in the mode register and perform a write access to the sdram. the write address must be chosen so that ba[1:0] are set to 0. for example, with a 16-bit 128 mb sdram (12 rows, 9 columns, 4 banks) bank address, the sdram write access should be done at the address 0x20000000. 8. for mobile sdram initialization, an ex tended mode register set (emrs) cycle is issued to program the sdram parameters (tcsr, pasr, ds). the application must set mode to 5 in the mode register and perform a write access to the sdram. the write address must be chosen so that ba[1] or ba[0] are set to 1. for example, with a 16-bit 128 mb sdram, (12 rows, 9 columns, 4 banks) bank address the sdram write access should be done at the address 0x20800000 or 0x20400000. 9. the application must go into normal mode, setting mode to 0 in the mode register and performing a write access at any location in the sdram. 10. write the refresh rate into the count field in the sdramc refresh timer register. (refresh rate = delay between refresh cycles). the sdram device requires a refresh every 15.625 us or 7.81 us. with a 100 mhz frequency, the refresh timer counter register must be set with the value 1562(15.652 s x 100 mhz) or 781(7.81 s x 100 mhz). after initialization, the sdram devices are fully functional. 191 6062b?atarm?15-nov-05 at91sam9261 figure 22-2. sdram device initialization sequence 22.5.2 i/o lines the pins used for interfacing the sdram controller may be multiplexed with the pio lines. the programmer must first program the pio controller to assign the sdram controller pins to their peripheral function. if i/o lines of the sdram controller are not used by the application, they can be used for other purposes by the pio controller. 22.5.3 interrupt the sdram controller interrupt (refresh error notification) is connected to the memory con- troller. this interrupt may be ored with other system peripheral interrupt lines and is finally provided as the system interrupt source (source 1) to the aic (advanced interrupt controller). using the sdram controller interrupt requires the aic to be programmed first. sdck sdramc_a[9:0] a10 sdramc_a[12:11] sdcs ras cas sdwe nbs inputs stable for 200 sec precharge all banks 1st auto-refresh 8th auto-refresh mrs command valid command sdcke t rp t rc t mrd 192 6062b?atarm?15-nov-05 at91sam9261 22.6 functional description 22.6.1 sdram controller write cycle the sdram controller allows burst access or si ngle access. in both cases, the sdram con- troller keeps track of the active row in each bank, thus maximizing performance. to initiate a burst access, the sdram controller uses the transfer type signal provided by the master requesting the access. if the next access is a sequential write access, writing to the sdram device is carried out. if the next access is a write-sequential access, but the current access is to a boundary page, or if the next access is in another row, then the sdram controller gener- ates a precharge command, activates the new row and initiates a write command. to comply with sdram timing parameters, additional clock cycles are inserted between precharge/active (t rp ) commands and active/write (t rcd ) commands. for definition of these timing parameters, refer to the ?sdramc configuration register? on page 202 . this is described in figure 22-3 below. figure 22-3. write burst, 32-bit sdram access sdck sdcs ras cas sdramc_a[12:0] d[31:0] t rcd = 3 dna sdwe dnb dnc dnd dne dnf dng dnh dni dnj dnk dnl row n col a col b col c col d col e col f col g col h col i col j col k col l 193 6062b?atarm?15-nov-05 at91sam9261 22.6.2 sdram controller read cycle the sdram controller allows burst access, incr emental burst of unspecified length or single access. in all cases, the sdram controller keeps track of the active row in each bank, thus maximizing performance of the sdram. if row and bank addresses do not match the previous row/bank address, then the sdram controller automatically generates a precharge com- mand, activates the new row and starts the read command. to comply with the sdram timing parameters, additional clock cycles on sdck ar e inserted between precharge and active com- mands (t rp ) and between active and read command (t rcd ). these two parameters are set in the configuration register of the sdram controller. after a read command, additional wait states are generated to comply with the cas la tency (1, 2 or 3 clock delays specified in the configuration register). for a single access or an incremented burst of unspecified length, the sdram controller anticipates the next access. while the last value of the column is returned by the sdram con- troller on the bus, the sdram controller anticipates the read to the next column and thus anticipates the cas latency. this reduces the effect of the cas latency on the internal bus. for burst access of specified length (4, 8, 16 words), access is not anticipated. this case leads to the best performance. if the burst is broken (border, busy mode, etc.), the next access is handled as an incrementing burst of unspecified length. figure 22-4. read burst, 32-bit sdram access sdck sdcs ras cas sdramc_a[12:0] d[31:0] (input) t rcd = 3 dna sdwe dnb dnc dnd dne dnf row n col a col b col c col d col e col f cas = 2 194 6062b?atarm?15-nov-05 at91sam9261 22.6.3 border management when the memory row boundary has been reached, an automatic page break is inserted. in this case, the sdram controller generates a precharge command, activates the new row and initiates a read or write command. to comply with sdram timing parameters, an additional clock cycle is inserted between the precharge/active (t rp ) command and the active/read (t rcd ) command. this is described in figure 22-5 below. figure 22-5. read burst with boundary row access sdck sdcs ras cas sdramc_a[12:0] d[31:0] t rp = 3 sdwe row m col a col a col b col c col d col e dna dnb dnc dnd t rcd = 3 cas = 2 col b col c col d dma dmb dmc dmd row n dme 195 6062b?atarm?15-nov-05 at91sam9261 22.6.4 sdram controller refresh cycles an auto-refresh command is used to refres h the sdram device. refresh addresses are gen- erated internally by the sdram device and incremented after each auto-refresh automatically. the sdram controller generates these auto-refres h commands periodically. an internal timer is loaded with the value in the register sdramc_tr that indicates the number of clock cycles between refresh cycles. a refresh error interrupt is generated when the previous auto-refresh command did not per- form. it is acknowledged by reading the interrupt status register (sdramc_isr). when the sdram controller initiates a refres h of the sdram device, internal memory accesses are not delayed. however, if the cp u tries to access the sdram, the slave indi- cates that the device is busy and the master is held by a wait signal. see figure 22-6 . figure 22-6. refresh cycle followed by a read access 22.6.5 power management three low-power modes are available: self-refresh mode: the sdram executes its own auto-refresh cycle without control of the sdram controller. current drain ed by the sdram is very low. power-down mode: auto-refresh cycles are controlled by the sdram controller. between auto-refresh cycles, the sdram is in power-do wn. current drained in power-down mode is higher than in self-refresh mode. deep power-down mode: (only available with mobile sdram) the sdram contents are lost, but the sdram does not drain any current. the sdram controller activates one low-power mo de as soon as the sdram device is not selected. it is possible to delay the entry in self-refresh and power-down mode after the last access by programming a timeout value in the low power register. sdck sdcs ras cas sdramc_a[12:0] d[31:0] (input) t rp = 3 sdwe dnb dnc dnd col c col d cas = 2 row m col a t rc = 8 t rcd = 3 dma row n 196 6062b?atarm?15-nov-05 at91sam9261 22.6.5.1 self-refresh mode this mode is selected by programming the lpcb field to 1 in the sdramc low power regis- ter. in self-refresh mode, the sdram device retains data without external clocking and provides its own internal clocking, thus performing its own auto-refresh cycles. all the inputs to the sdram device become ?don?t care? except sdcke, which remains low. as soon as the sdram device is selected, the sdram cont roller provides a sequence of commands and exits self-refresh mode. some low-power sdrams (e.g., mobile sdram) can refresh only one-quarter or half quarter or all banks of the sdram array. this feature reduces the self refresh current. to configure this feature, temperature compensated self refresh (tcsr), partial array self refresh (pasr) and drive strength (ds) parameters must be set in the low power register and transmitted to the low-power sdram during the initialization. the sdram device must remain in self-refresh mode for a minimum period of t ras and may remain in self-refresh mode for an indefinite period. this is described in figure 22-7 . figure 22-7. self-refresh mode behavior sdck sdcs ras cas sdramc_a[12:0] self refresh mode sdwe row t xsr = 3 sdcke write sdramc_srr srcb = 1 access request to the sdram controller 197 6062b?atarm?15-nov-05 at91sam9261 22.6.5.2 low-power mode this mode is selected by programming the lpcb field to 2 in the sdramc low power regis- ter. power consumption is greater than in self-refresh mode. all the input and output buffers of the sdram device are deactivated except sdcke, which remains low. in contrast to self- refresh mode, the sdram device cannot remain in low-power mode longer than the refresh period (64 ms for a whole device refresh operation). as no auto-refresh operations are per- formed by the sdram itself, the sdram controller carries out the refresh operation. the exit procedure is faster than in self-refresh mode. this is described in figure 22-8 . figure 22-8. low-power mode behavior sdck sdcs ras cas sdramc_a[12:0] d[31:0] (input) t rcd = 3 dna dnb dnc dnd dne dnf row n col a col b col c col d col e col f cas = 2 sdcke low power mode 198 6062b?atarm?15-nov-05 at91sam9261 22.6.5.3 deep power-down mode this mode is selected by programming the lpcb field to 3 in the sdramc low power regis- ter. when this mode is activated, all internal voltage generators inside the sdram are stopped and all data is lost. when this mode is enabled, the application must not access to the sdram until a new initial- ization sequence is done (see ?sdram device initialization? on page 190 ). this is described in figure 22-9 . figure 22-9. deep power-down mode behavior sdck sdcs ras cas sdramc_a[12:0] d[31:0] (input) t rp = 3 sdwe dnb dnc dnd col c col d row n cke 199 6062b?atarm?15-nov-05 at91sam9261 22.7 sdram controller ( sdramc) user interface table 22-8. sdram controller memory map offset register name access reset state 0x00 sdramc mode register sd ramc_mr read/write 0x00000000 0x04 sdramc refresh timer regist er sdramc_tr read/write 0x00000000 0x08 sdramc configuration regist er sdramc_cr read/write 0x852372c0 0x0c sdramc high speed register sdramc_hsr read/write 0x00 0x10 sdramc low power register sdramc_lpr read/write 0x0 0x14 sdramc interrupt enable register sdramc_ier write-only ? 0x18 sdramc interrupt disable register sdramc_idr write-only ? 0x1c sdramc interrupt mask register sdramc_imr read-only 0x0 0x20 sdramc interrupt status register sdramc_isr read-only 0x0 0x24 sdramc memory device register sdramc_mdr read 0x0 0x28 - 0xfc reserved ? ? ? 200 6062b?atarm?15-nov-05 at91sam9261 22.7.1 sdramc mode register register name : sdramc_mr access type : read/write reset value : 0x00000000 mode: sdramc command mode this field defines the command issued by the sdram controller when the sdram device is accessed. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????? mode mode description 0 0 0 normal mode. any access to the sdram is decoded normally. 001 the sdram controller issues a nop command when the sdram device is accessed regardless of the cycle. 010 the sdram controller issues an ?all banks prec harge? command when the sdram device is accessed regardless of the cycle. 011 the sdram controller issues a ?load mode registe r? command when the sdram device is accessed regardless of the cycle. the address offset with respect to the sdram device base address is used to program the mode register. for instance, when this mode is activated, an access to the ?sdram_base + offset? address generates a ?load mode register? comm and with the value ?offset? written to the sdram device mode register. 100 the sdram controller issues an ?auto-refresh? command when the sdram device is accessed regardless of the cycle. previously, an ?all banks precharge? command must be issued. 101 the sdram controller issues an extended load mo de register command when the sdram device is accessed regardless of the cycle. the address offset wi th respect to the sdram device base address is used to program the mode register. for instance, w hen this mode is activated, an access to the ?sdram_base + offset? address generates an ?extended load mode register? command with the value ?offset? written to the sdram device mode register. 1 1 0 deep power-down mode. enters deep power-down mode. 201 6062b?atarm?15-nov-05 at91sam9261 22.7.2 sdramc refresh timer register register name : sdramc_tr access type : read/write reset value : 0x00000000 count: sdramc refresh timer count this 12-bit field is loaded into a timer that generates the refr esh pulse. each time the refresh pulse is generated, a refresh burst is initiated. the value to be loaded depends on the sdramc clock frequency (mck: master clock), the refresh rate of the sdram device and the refresh burst length where 15.6 s per row is a typical value for a burst of length one. to refresh the sdram device, this 12-bit field must be written. if this condition is not satisfied, no refresh command is issued and no refresh of the sdram device is carried out. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???? count 76543210 count 202 6062b?atarm?15-nov-05 at91sam9261 22.7.3 sdramc configuration register register name : sdramc_cr access type : read/write reset value : 0x852372c0 nc: number of column bits reset value is 8 column bits. nr: number of row bits reset value is 11 row bits. nb: number of banks reset value is two banks. 31 30 29 28 27 26 25 24 txsr tras 23 22 21 20 19 18 17 16 trcd trp 15 14 13 12 11 10 9 8 trc twr 76543210 dbw cas nb nr nc nc column bits 008 019 1010 1111 nr row bits 00 11 01 12 10 13 11 reserved nb number of banks 02 14 203 6062b?atarm?15-nov-05 at91sam9261 cas: cas latency reset value is two cycles. in the sdramc, only a cas latency of one, two and three cycles are managed. in any case, another value must be programmed. dbw: data bus width reset value is 16 bits 0: data bus width is 32 bits. 1: data bus width is 16 bits. twr: write recovery delay reset value is two cycles. this field defines the write recovery time in numb er of cycles. number of cycles is between 0 and 15. trc: row cycle delay reset value is seven cycles. this field defines the delay between a refresh and an activate command in numbe r of cycles. number of cycles is between 0 and 15. trp: row precharge delay reset value is three cycles. this field defines the delay between a precharge command and another command in number of cycles. number of cycles is between 0 and 15. trcd: row to column delay reset value is two cycles. this field defines the delay between an activate command and a read/write co mmand in number of cycles. number of cycles is between 0 and 15. tras: active to precharge delay reset value is five cycles. this field defines the delay between an activate command and a precharge command in number of cycles. number of cycles is between 0 and 15. txsr: exit self refresh to active delay reset value is height cycles. this field defines the delay between scke set high and an activate command in numb er of cycles. number of cycles is between 0 and 15. cas cas latency (cycles) 00 reserved 01 1 10 2 11 3 204 6062b?atarm?15-nov-05 at91sam9261 22.7.4 sdramc high speed register register name : sdramc_hsr access type : read/write da: decode cycle enable 0: decode cycle is disabled. 1: decode cycle is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????da 205 6062b?atarm?15-nov-05 at91sam9261 22.7.5 sdramc low power register register name : sdramc_lpr access type : read/write reset value :0x0 lpcb: low-power configuration bits pasr: partial array self-refresh (only for low-power sdram) pasr parameter is transmitted to the sdram during initialization to specify whether only one quar ter, one half or all banks of the sdram array are enabled. disabled banks are not refreshed in self-refresh mode. this parameter must be set according to the sdram device specification. tcsr: temperature compensated self -refresh (only fo r low-power sdram) tcsr parameter is transmitted to the sdram during initializa tion to set the refresh interval during self-refresh mode depending on the temperature of the low-power sdram. this parameter must be set according to the sdram device specification. ds: drive strength (only for low-power sdram) ds parameter is transmitted to the sdram during initialization to sele ct the sdram strength of data output. this parame- ter must be set according to the sdram device specification. timeout: time to define when low-power mode is enabled 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?? timeout ds tcsr 76543210 ? pasr ? ? lpcb 00 low power feature is inhibited: no power-down, self -refresh or deep power-down command is issued to the sdram device. 01 the sdram controller issues a self-refresh comm and to the sdram device, the sdclk clock is deactivated and the sdcke signal is set low. t he sdram device leaves the self refresh mode when accessed and enters it after the access. 10 the sdram controller issues a power-down command to the sdram device after each access, the sdcke signal is set to low. the sdram device leaves the power-down mode when accessed and enters it after the access. 11 the sdram controller issues a deep power-down command to the sdram device. this mode is unique to low-power sdram. 00 the sdram controller activates the sdram low-power mode immediately after the end of the last transfer. 01 the sdram controller activates the sdram low-power mode 64 clock cycles after the end of the last transfer. 10 the sdram controller activates the sdram low-power mode 128 clock cycles after the end of the last transfer. 11 reserved. 206 6062b?atarm?15-nov-05 at91sam9261 22.7.6 sdramc interrupt enable register register name : sdramc_ier access type : write-only res: refresh error status 0: no effect. 1: enables the refresh error interrupt. 22.7.7 sdramc interrupt disable register register name : sdramc_idr access type : write-only res: refresh error status 0: no effect. 1: disables the refresh error interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????res 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????res 207 6062b?atarm?15-nov-05 at91sam9261 22.7.8 sdramc interrupt mask register register name : sdramc_imr access type : read-only res: refresh error status 0: the refresh error interrupt is disabled. 1: the refresh error interrupt is enabled. 22.7.9 sdramc interrupt status register register name : sdramc_isr access type : read-only res: refresh error status 0: no refresh error has been detected since the register was last read. 1: a refresh error has been detected since the register was last read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????res 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????res 208 6062b?atarm?15-nov-05 at91sam9261 22.7.10 sdramc memory device register register name : sdramc_mdr access type : read/write md: memory device type 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????? md 00 sdram 01 low-power sdram 10 reserved 11 reserved. 209 6062b?atarm?15-nov-05 at91sam9261 23. peripheral dma controller (pdc) 23.1 description the peripheral dma controller (pdc) transfers data between on-chip serial peripherals and the on- and/or off-chip memories. the link between the pdc and a serial peripheral is oper- ated by the ahb to abp bridge. the pdc contains 19 channels. the full-duplex peripherals feature 18 mono directional chan- nels used in pairs (transmit only or receive only). the half-duplex peripherals feature 1 bi- directional channels. the user interface of each pdc channel is integrated into the user interface of the peripheral it serves. the user interface of mono directional channels (receive only or transmit only), con- tains two 32-bit memory pointers and two 16-bit counters, one set (pointer, counter) for current transfer and one set (pointer, counter) for next tr ansfer. the bi-directional channel user inter- face contains four 32-bit memory pointers and four 16-bit counters. each set (pointer, counter) is used by current transmit, next transmit, current receive and next receive. using the pdc removes processor overhead by reducing its intervention during the transfer. this significantly reduces the number of clock cycles required for a data transfer, which improves microcontroller performance. to launch a transfer, the peripheral triggers its associated pdc channels by using transmit and receive signals. when the programmed data is transferred, an end of transfer interrupt is generated by the peripheral itself. 210 6062b?atarm?15-nov-05 at91sam9261 23.2 block diagram figure 23-1. block diagram pdc full duplex peripheral thr rhr pdc channel a pdc channel b control status & control control pdc channel c half duplex peripheral thr status & control receive or transmit peripheral rhr or thr control control rhr pdc channel d status & control 211 6062b?atarm?15-nov-05 at91sam9261 23.3 functional description 23.3.1 configuration the pdc channel user interface enables the user to configure and control data transfers for each channel. the user interface of each pdc channel is integrated into the associated peripheral user interface. the user interface of a serial peripheral, whether it is full or half duplex, contains four 32-bit pointers (rpr, rnpr, tpr, tnpr) and four 16-bit counter registers (rcr, rncr, tcr, tncr). however, the transmit and receive parts of each type are programmed differently: the transmit and receive parts of a full duplex peripheral can be programmed at the same time, whereas only one part (transmit or receive) of a half duplex peripheral can be programmed at a time. 32-bit pointers define the access location in memory for current and next transfer, whether it is for read (transmit) or write (receive). 16-bit counters define the size of current and next trans- fers. it is possible, at any moment, to read the number of transfers left for each channel. the pdc has dedicated status registers which indicate if the transfer is enabled or disabled for each channel. the status for each channel is located in the associated peripheral status regis- ter. transfers can be enabled and/or disabled by setting txten/txtdis and rxten/rxtdis in the peripheral?s transfer control register. at the end of a transfer, the pdc channel sends status flags to its associated peripheral. these flags are visible in the peripheral status register (endrx, endtx, rxbuff, and txbufe). refer to section 23.3.3 and to the associated peripheral user interface. 23.3.2 memory pointers each full duplex peripheral is connected to th e pdc by a receive channel and a transmit chan- nel. both channels have 32-bit memory pointers t hat point respectively to a receive area and to a transmit area in on- and/or off-chip memory. each half duplex peripheral is connected to th e pdc by a bidirectional channel. this channel has two 32-bit memory pointers, one for current transfer and the other for next transfer. these pointers point to transmit or receive data depending on the operating mode of the peripheral. depending on the type of transfer (byte, half-word or word), the memory pointer is incre- mented respectively by 1, 2 or 4 bytes. if a memory pointer address changes in the middl e of a transfer, the pdc channel continues operating using the new address. 23.3.3 transfer counters each channel has two 16-bit counters, one for current transfer and the other one for next transfer. these counters define the size of data to be transferred by the channel. the current transfer counter is decremented first as the dat a addressed by current memory pointer starts to be transferred. when the current transfer counter reaches zero, the channel checks its next transfer counter. if the value of next counter is zero, the channel stops transferring data and sets the appropriate flag. but if the next counter value is greater then zero, the values of the next pointer/next counter are copied into the current pointer/current counter and the channel resumes the transfer whereas next pointer/next counter get zero/zero as values. at the end of this transfer the pdc channel sets the appropri ate flags in the peripheral status register. 212 6062b?atarm?15-nov-05 at91sam9261 the following list gives an overview of ho w status register flags behave depending on the counters? values: endrx flag is set when the periph_rcr register reaches zero. rxbuff flag is set when both per iph_rcr and periph_rncr reach zero. endtx flag is set when the periph_tcr register reaches zero. txbufe flag is set when both periph_tcr and periph_tncr reach zero. these status flags are described in the peripheral status register. 23.3.4 data transfers the serial peripheral triggers its associated pd c channels? transfers using transmit enable (txen) and receive enable (rxen) flags in the transfer control register integrated in the peripheral?s user interface. when the peripheral receives an external data, it sends a receive ready signal to its pdc receive channel which then reques ts access to the matrix. wh en access is granted, the pdc receive channel starts reading the peripheral receive holding register (rhr). the read data are stored in an internal buffer and then written to memory. when the peripheral is about to send data, it sends a transmit read y to its pdc transmit channel which then requests access to the matrix. when access is granted, the pdc transmit channel reads data from memory and puts them to transmit holding register (thr) of its associated peripheral. the same peripheral sends data according to its mechanism. 23.3.5 pdc flags and peripheral status register each peripheral connected to the pdc sends out receive ready and transmit ready flags and the pdc sends back flags to the peripheral. all these flags are only visible in the peripheral status register. depending on the type of peripheral, half or fu ll duplex, the flags belong to either one single channel or two different channels. 23.3.5.1 receive transfer end this flag is set when periph_rcr register r eaches zero and the last data has been trans- ferred to memory. it is reset by writing a non zero value in periph_rcr or periph_rncr. 23.3.5.2 transmit transfer end this flag is set when periph_tcr register reaches zero and the last data has been written into peripheral thr. it is reset by writing a non zero value in periph_tcr or periph_tncr. 23.3.5.3 receive buffer full this flag is set when periph_rcr register r eaches zero with periph_rncr also set to zero and the last data has been transferred to memory. it is reset by writing a non zero value in periph_tcr or periph_tncr. 213 6062b?atarm?15-nov-05 at91sam9261 23.3.5.4 transmit buffer empty this flag is set when periph_tcr register reaches zero with periph_tncr also set to zero and the last data has been written into peripheral thr. it is reset by writing a non zero value in periph_tcr or periph_tncr. 214 6062b?atarm?15-nov-05 at91sam9261 23.4 peripheral dma controll er (pdc) user interface note: 1. periph: ten registers are mapped in the peripheral memory space at the same offset. these can be defined by the user according to the function and the peripheral desired (dbgu, usart, ssc, spi, mci, etc.) table 23-1. memory map offset register name access reset state 0x100 receive pointer register periph (1) _rpr read/write 0 0x104 receive counter register periph_rcr read/write 0 0x108 transmit pointer register periph_tpr read/write 0 0x10c transmit counter regi ster periph_tcr read/write 0 0x110 receive next pointer register periph_rnpr read/write 0 0x114 receive next counter register periph_rncr read/write 0 0x118 transmit next pointer register periph_tnpr read/write 0 0x11c transmit next counter register periph_tncr read/write 0 0x120 transfer control register periph_ptcr write 0 0x124 transfer status register periph_ptsr read 0 215 6062b?atarm?15-nov-05 at91sam9261 23.4.1 receive pointer register register name: periph_rpr access type: read/write rxptr: receive pointer register rxptr must be set to receive buffer address. when a half duplex peripheral is connected to the pdc, rxptr = txptr. 23.4.2 receive counter register register name: periph_rcr access type: read/write rxctr: receive counter register rxctr must be set to receive buffer size. when a half duplex peripheral is connected to the pdc, rxctr = txctr. 0 = stops peripheral data transfer to the receiver 1 - 65535 = starts peripheral data transfer if corresponding channel is active 31 30 29 28 27 26 25 24 rxptr 23 22 21 20 19 18 17 16 rxptr 15 14 13 12 11 10 9 8 rxptr 76543210 rxptr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rxctr 76543210 rxctr 216 6062b?atarm?15-nov-05 at91sam9261 23.4.3 transmit pointer register register name: periph_tpr access type: read/write txptr: transmit counter register txptr must be set to transmit buffer address. when a half duplex peripheral is connected to the pdc, rxptr = txptr. 23.4.4 transmit counter register register name: periph_tcr access type: read/write txctr: transmit counter register txctr must be set to transmit buffer size. when a half duplex peripheral is connected to the pdc, rxctr = txctr. 0 = stops peripheral data transfer to the transmitter 1- 65535 = starts peripheral data transfer if corresponding channel is active 31 30 29 28 27 26 25 24 txptr 23 22 21 20 19 18 17 16 txptr 15 14 13 12 11 10 9 8 txptr 76543210 txptr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 txctr 76543210 txctr 217 6062b?atarm?15-nov-05 at91sam9261 23.4.5 receive next pointer register register name: periph_rnpr access type: read/write rxnptr: receive next pointer rxnptr contains next receive buffer address. when a half duplex peripheral is connected to the pdc, rxnptr = txnptr. 23.4.6 receive next counter register register name: periph_rncr access type: read/write rxnctr: receive next counter rxnctr contains next receive buffer size. when a half duplex peripheral is connected to the pdc, rxnctr = txnctr. 31 30 29 28 27 26 25 24 rxnptr 23 22 21 20 19 18 17 16 rxnptr 15 14 13 12 11 10 9 8 rxnptr 76543210 rxnptr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rxnctr 76543210 rxnctr 218 6062b?atarm?15-nov-05 at91sam9261 23.4.7 transmit next pointer register register name: periph_tnpr access type: read/write txnptr: transmit next pointer txnptr contains next transmit buffer address. when a half duplex peripheral is connected to the pdc, rxnptr = txnptr. 23.4.8 transmit next counter register register name: periph_tncr access type: read/write txnctr: transmit counter next txnctr contains next transmit buffer size. when a half duplex peripheral is connected to the pdc, rxnctr = txnctr. 31 30 29 28 27 26 25 24 txnptr 23 22 21 20 19 18 17 16 txnptr 15 14 13 12 11 10 9 8 txnptr 76543210 txnptr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 txnctr 76543210 txnctr 219 6062b?atarm?15-nov-05 at91sam9261 23.4.9 transfer control register register name: periph_ptcr access type: write rxten: receiver transfer enable 0 = no effect. 1 = enables pdc receiver channel requests if rxtdis is not set. when a half duplex peripheral is connected to the pdc, en abling the receiver channel requests automatically disables the transmitter channel requests. it is forbidden to set both txten and rxten for a half duplex peripheral. rxtdis: receiver transfer disable 0 = no effect. 1 = disables the pdc receiver channel requests. when a half duplex peripheral is connecte d to the pdc, disabling the receiver chann el requests also disables the transmit- ter channel requests. txten: transmitter transfer enable 0 = no effect. 1 = enables the pdc transmitter channel requests. when a half duplex peripheral is connected to the pdc, it en ables the transmitter channel requests only if rxten is not set. it is forbidden to set both txten and rxten for a half duplex peripheral. txtdis: transmitter transfer disable 0 = no effect. 1 = disables the pdc transmitter channel requests. when a half duplex peripheral is connected to the pdc, disab ling the transmitter channel requests disables the receiver channel requests. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????txtdistxten 76543210 ??????rxtdisrxten 220 6062b?atarm?15-nov-05 at91sam9261 23.4.10 transfer status register register name: periph_ptsr access type: read rxten: receiver transfer enable 0 = pdc receiver channel requests are disabled. 1 = pdc receiver channel requests are enabled. txten: transmitter transfer enable 0 = pdc transmitter channel requests are disabled. 1 = pdc transmitter channel requests are enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????txten 76543210 ???????rxten 221 6062b?atarm?15-nov-05 at91sam9261 24. clock generator 24.1 description the clock generator is made up of 2 plls, a main oscillator, and a 32,768 hz low-power oscillator. it provides the following clocks: slck, the slow clock, is the only permanent clock within the system mainck is the output of the main oscillator the clock generator user interface is embedded within the power management controller one and is described in section 25.11 . however, the clock generator registers are named ckgr_. pllack is the output of the divider and pll a block pllbck is the output of the divider and pll b block 24.2 slow clock crystal oscillator the slow clock is the output of the slow clock generator and is the only clock considered per- manent in a system that includes the power management controller. it is mandatory in the operations of the pmc. in all cases, a 32,768 hz crystal must be connected to the xin32 and xout32 pins in order to ensure that the slow clock is present. the clock generator integrates a 32,768 hz low-power osc illator. the xin32 and xout32 pins must be connected to a 32,768 hz crystal . two external capacitors must be wired as shown in figure 24-1 . figure 24-1. typical slow clock crystal oscillator connection xin32 xout32 gndpll c l2 c l1 32,768 hz crystal 222 6062b?atarm?15-nov-05 at91sam9261 24.3 main oscillator figure 24-2 shows the main oscillator block diagram. figure 24-2. main oscillator block diagram 24.3.1 main oscillator connections the clock generator integrates a main oscillator that is designed for a 3 to 20 mhz funda- mental crystal. the typical crys tal connection is illustrated in figure 24-3 . the 1 k ? resistor is only required for crystals with frequencies lowe r than 8 mhz. the oscillator contains 25 pf capacitors on each xin and xout pin. consequently, cl1 and cl2 can be removed when a crystal with a load capacitance of 12.5 pf is used . for further details on the electrical charac- teristics of the main oscillato r, see the dc characteristics se ction of the product datasheet. figure 24-3. typical crystal connection 24.3.2 main oscillator startup time the startup time of the main oscillator is given in the dc characteristi cs section of the product datasheet. the startup time depends on the crystal frequency and decreases when the fre- quency rises. 24.3.3 main oscillator control to minimize the power required to start up the system, the main oscillator is disabled after reset and slow clock is selected. xin xout moscen main oscillator counter oscount moscs mainck main clock main clock frequency counter mainf mainrdy slck slow clock main oscillator 1k xin xout gnd c l2 c l1 223 6062b?atarm?15-nov-05 at91sam9261 the software enables or disables the main os cillator so as to reduc e power cons umption by clearing the moscen bit in the main oscillator register (ckgr_mor). when disabling the main oscilla tor by clearing the moscen bit in ckgr_mor, the moscs bit in pmc_sr is automatically clear ed, indicating the main clock is off. when enabling the main oscillator, the user must initiate the main oscillator counter with a value corresponding to the star tup time of the oscillator. th is startup time depends on the crystal frequency connecte d to the main oscillator. when the moscen bit and the oscount are written in ckgr_mor to enable the main oscillator, the moscs bit in pmc_sr (status register) is cleared and the counter starts counting down on the slow clock divided by 8 from the oscount value. since the oscount value is coded with 8 bits, the maximum startup time is about 62 ms. when the counter reaches 0, the moscs bit is se t, indicating that the main clock is valid. set- ting the moscs bit in pmc_imr can trigger an interrupt to the processor. 24.3.4 main clock frequency counter the main oscillator features a main clock fr equency counter that provides the quartz fre- quency connected to the main oscillator. generally, this value is known by the system designer; however, it is useful for the boot program to configure the device with the correct clock speed, independently of the application. the main clock frequency counter starts incrementing at the main clock speed after the next rising edge of the slow clock as soon as the main oscillator is stable, i.e., as soon as the moscs bit is set. then, at the 16th falling edge of slow clock, the mainrdy bit in ckgr_mcfr (main clock frequency register) is set and the counter stops counting. its value can be read in the mainf field of ckgr_mcfr and gives the number of main clock cycles during 16 periods of slow clock, so t hat the frequency of the crystal connected on the main oscillator ca n be determined. 24.3.5 main oscillator bypass the user can input a clock on the device instead of connecting a crystal. in this case, the user has to provide the external clock signal on the xi n pin. the input characteristics of the xin pin under these conditions are given in the product electrical characteristics section. the program- mer has to be sure to set the oscbypass bit to 1 and the moscen bit to 0 in the main osc register (ckgr_mor) for the external clock to operate properly. 224 6062b?atarm?15-nov-05 at91sam9261 24.4 divider and pll block the pll embeds an input divider to increase the accuracy of the resulting clock signals. how- ever, the user must respect the pll minimum input frequency when programming the divider. figure 24-4 shows the block diagram of the divider and pll blocks. figure 24-4. divider and pll blocks block diagram 24.4.1 pll filter the pll requires connection to an external second-order filter through the pin, either pplrca or pllrcb. figure 24-6 shows a schematic of these filters. figure 24-5. pll capacitors and resistors values of r, c1 and c2 to be connected to the pllrc pin must be calculated as a function of the pll input frequency, the pll output frequency and the phase margin. a trade-off has to be found between output signal overshoot and startup time. divider b pllrcb divb pll b mulb pllrca diva pll a counter pllbcount lockb pll a counter pllacount locka mula outb outa slck pllack pllbck divider a pll b mainck gnd c1 c2 pll pllrc r 225 6062b?atarm?15-nov-05 at91sam9261 24.4.2 divider and phase lock loop programming the divider can be set between 1 and 255 in steps of 1. when a divider field (div) is set to 0, the output of the corresponding divider and the p ll output is a continuous signal at level 0. on reset, each div field is set to 0, thus the corresponding pll input clock is set to 0. the pll allows multiplication of the divider?s outputs. the pll clock signal has a frequency that depends on the respective source signal frequency and on the parameters div and mul. the factor applied to the source signal frequency is (mul + 1)/div. when mul is written to 0, the corresponding pll is disabled and its power consumption is saved. re-enabling the pll can be performed by writing a value higher than 0 in the mul field. whenever the pll is re-enabled or one of its parameters is changed, the lock bit (locka or lockb) in pmc_sr is automatically cleared. the values written in the pllcount field (pllacount or pllbcount) in ckgr_p llr (ckgr_pllar or ckgr_pllbr), are loaded in the pll counter. the pll counter then decrements at the speed of the slow clock until it reaches 0. at this time, the lock bit is set in pmc_sr and can trigger an interrupt to the processor. the user has to load the number of slow clock cycles required to cover the pll transient time into the pllcount field. the transient time depends on the pll filter. the initial state of the pll and its target frequency can be calculated using a specific tool provided by atmel. 226 6062b?atarm?15-nov-05 at91sam9261 25. power management controller (pmc) 25.1 description the power management controller (pmc) opti mizes power consumption by controlling all system and user peripheral clocks. the pmc enab les/disables the clock inputs to many of the peripherals and the arm processor. the power management controller provides the following clocks: mck, the master clock, programmable from a few hundred hz to the maximum operating frequency of the device. it is available to the modules running permanently, such as the aic and the memory controller. processor clock (pck), switched off wh en entering processor in idle mode. peripheral clocks, typically mck, provided to the embedded peripherals (usart, ssc, spi, twi, tc, mci, etc.) and independently controllable. in order to reduce the number of clock names in a product, the peripheral cloc ks are named mck in the product datasheet. hclocks (mck), provided to the ahb/asb high speed peripherals and independently controllable. in order to reduce the number of clock names in a product, the hclocks are named mck in the product datasheet. uhp clock (uhpck), required by usb host port operations. programmable clock outputs can be selected from the clocks provided by the clock generator and driven on the pckx pins. 25.2 master clock controller the master clock controller provides selection and division of the master clock (mck). mck is the clock provided to all the peripherals and the memory controller. the master clock is selected from one of the clocks provided by the clock generator. select- ing the slow clock provides a slow clock signal to the whole device. selecting the main clock saves power consumption of the plls. the master clock controller is made up of a clock selector and a prescaler. it also contains a master clock divider which allows the processor clock to be faster than the master clock. the master clock selection is made by writi ng the css field (clock source selection) in pmc_mckr (master clock register). the prescale r supports the division by a power of 2 of the selected clock between 1 and 64. the pres field in pmc_mckr programs the prescaler. the master clock divider can be programmed through the mdiv field in pmc_mckr. each time pmc_mckr is written to define a ne w master clock, the mckrdy bit is cleared in pmc_sr. it reads 0 until the master clock is established. then, the mckrdy bit is set and can trigger an interrupt to the processor. this feature is useful when switching from a high- speed clock to a lower one to inform the software when the change is actually done. 227 6062b?atarm?15-nov-05 at91sam9261 figure 25-1. master clock controller 25.3 processor clock controller the pmc features a processor clock controller (pck) that implements the processor idle mode. the processor clock can be enabled and disabled by writing the system clock enable (pmc_scer) and system clock disable registers (pmc_scdr). the status of this clock (at least for debug purpose) can be read in the system clock status register (pmc_scsr). the processor clock pck is enabled after a re set and is automatically re-enabled by any enabled interrupt. the processor idle mode is achieved by disabling the processor clock, which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product. when the processor clock is disabled, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus. 25.4 usb clock controller the usb source clock is always generated from the pll b output. if using the usb, the user must program the pll to generate a 48 mhz, a 96 mhz or a 192 mhz signal with an accuracy of 0.25% depending on the usbdiv bit in ckgr_pllbr (see figure 25-6 ). when the pll b output is stable, i.e., the lockb is set: the usb host clock can be enabled by setting the uhp bit in pmc_scer. to save power on this peripheral when it is not used, the user can set the uhp bit in pmc_scdr. the uhp bit in pmc_scsr gives the activity of this clock. the usb host port require both the 12/48 mhz signal and the master clock. the master clock may be controlled via the peripheral clock controller. figure 25-2. usb clock controller slck master clock prescaler mck pres css master clock divider mainck pllack pllbck mdiv to the processor clock controller (pck) pmc_mckr pmc_mckr pmc_mckr usb source clock udp clock (udpck) udp usbdiv divider /1,/2,/4 uhp clock (uhpck) uhp 228 6062b?atarm?15-nov-05 at91sam9261 25.5 peripheral clock controller the power management controller controls t he clocks of each embedded peripheral by the way of the peripheral clock controller. the user can individually enable and disable the mas- ter clock on the peripherals by writing into the peripheral clock enable (pmc_pcer) and peripheral clock disable (pmc_pcdr) registers. th e status of the peripheral clock activity can be read in the peripheral clock status register (pmc_pcsr). when a peripheral clock is disabled, the clock is immediately stopped. the peripheral clocks are automatically disabled after a reset. in order to stop a peripheral, it is recommended that the system software wait until the periph- eral has executed its last programmed operation before disabling the clock. this is to avoid data corruption or erroneous behavior of the system. the bit number within the peripheral clock co ntrol registers (pmc_pcer, pmc_pcdr, and pmc_pcsr) is the peripheral identifier defined at the product level. generally, the bit number corresponds to the interrupt source number assigned to the peripheral. 25.6 hclock controller the pmc facilitates control of th e clocks of each specific ah b/asb peripheral by means of the hclock controller. the user can individually ena ble and disable the hclocks by writing into the registers; system clock enable (pmc_scer) and system clock disable (pmc_scdr). the status of hclock activity can be read in the system clock status register (pmc_scsr). when an hclock is disabled, the clock is immediately stopped. when the hclock is re- enabled, the peripheral resumes action wher e it left off. the hclocks are automatically dis- abled after a reset. 1 hclock can be controlled. 25.7 programmable clock output controller the pmc controls 4 signals to be output on exte rnal pins pckx. each signal can be indepen- dently programmed via the pmc_pckx registers. pckx can be independently selected between the sl ow clock, the pll a output, the pll b output and the main clock by writing the css field in pmc_pckx. each output signal can also be divided by a power of 2 between 1 and 64 by writing the pres (prescaler) field in pmc_pckx. each output signal can be enabled and disabled by writing 1 in the corresponding bit, pckx of pmc_scer and pmc_scdr, respec tively. status of the active programmable output clocks are given in the pckx bits of pmc_scsr (system clock status register). moreover, like the pck, a status bit in pmc_sr indicates that the programmable clock is actually what has been programmed in the programmable clock registers. as the programmable clock controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disabl e the programmable clock before any configura- tion change and to re-enable it after the change is actually performed. 229 6062b?atarm?15-nov-05 at91sam9261 25.8 programming sequence 1. enabling the main oscillator: the main oscillator is enabled by setting the moscen field in the ckgr_mor register. in some cases it may be advantageous to define a start-up time. this can be achieved by writing a value in the oscount field in the ckgr_mor register. once this register has been correctly configured, the user must wait for moscs field in the pmc_sr register to be set. this can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to moscs has been enabled in the pmc_ier register. code example: write_register(ckgr_mor,0x00000701) start up time = 8 * oscount / slck = 56 slow clock cycles. so, the main oscillator will be enabled (moscs bit set) after 56 slow clock cycles. 2. checking the main oscilla tor frequency (optional): in some situations the user may need an accurate measure of the main oscillator fre- quency. this measure can be accomp lished via the ckgr_mcfr register. once the mainrdy field is set in ckgr_mcfr register, the user may read the mainf field in ckgr_mcfr register. this provides the number of main clock cycles within six- teen slow clock cycles. 3. setting pll a and divider a: all parameters necessary to configure pll a and divider a are located in the ckgr_pllar register. it is important to note that bit 29 must always be set to 1 when programming the ckgr_pllar register. the diva field is used to control the divider a itself. the user can program a value between 0 and 255. divider a output is divider a input divided by diva. by default, diva parameter is set to 0 which means that divider a is turned off. the outa field is used to select the pll a output frequency range. the mula field is the pll a multiplier factor. this parameter can be programmed between 0 and 2047. if mula is set to 0, pll a will be turned off. otherwise pl l a output frequency is pll a input frequency multiplied by (mula + 1). the pllacount field specifies the number of slow clock cycles before locka bit is set in the pmc_sr register after ckgr_pllar register has been written. once ckgr_pllar register has been written, the user is obliged to wait for the locka bit to be set in the pmc_sr register. this can be done either by pollin g the status register or by waiting the interrupt line to be raised if the associated interrupt to locka has been enabled in the pmc_ier register. all parameters in ckgr_pllar can be programmed in a single write operation. if at some stage one of the following parameters, srca, mula, diva is modified, locka bit will go 230 6062b?atarm?15-nov-05 at91sam9261 low to indicate that pll a is not ready yet. when pll a is locked, locka will be set again. user has to wait for locka bit to be set before using the pll a output clock. code example: write_register(ckgr_pllar,0x20030605) pll a and divider a are enabled. pll a input cl ock is main clock divided by 5. pll an out- put clock is pll a input clock multiplied by 4. once ckgr_pllar has been written, locka bit will be set after six slow clock cycles. 4. setting pll b and divider b: all parameters needed to configure pll b and divider b are located in the ckgr_pllbr register. the divb field is used to control divider b itself. a value between 0 and 255 can be pro- grammed. divider b output is divider b input divided by divb parameter. by default divb parameter is set to 0 which means that divider b is turned off. the outb field is used to select the pll b output frequency range. the mulb field is the pll b multiplier factor. this parameter can be programmed between 0 and 2047. if mulb is set to 0, pll b will be turned off, otherwise the pll b output fre- quency is pll b input frequency multiplied by (mulb + 1). the pllbcount field specifies the number of slow clock cycles before lockb bit is set in the pmc_sr register after ckgr_pllbr register has been written. once the pmc_pllb register has been written, the user must wait for the lockb bit to be set in the pmc_sr register. this can be done eith er by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to lockb has been enabled in the pmc_ier register. all parameters in ckgr_pllbr can be programmed in a single write operation. if at some stage one of the following parameters, mulb, divb is modified, lockb bit will go low to indicate that pll b is not ready yet. when pll b is locked, lockb will be set again. the user is constr ained to wait for lockb bit to be set before using the pll a output clock. the usbdiv field is used to control the addition al divider by 1, 2 or 4, which generates the usb clock(s). code example: write_register(ckgr_pllbr,0x00040805) if pll b and divider b are enabled, the pll b input clock is the main clock. pll b output clock is pll b input clock multiplied by 5. once ckgr_pllbr has been written, lockb bit will be set after eight slow clock cycles. 5. selection of master clock and processor clock the master clock and the processor clock are configurable via the pmc_mckr register. the css field is used to select the master clock divider source. by default, the selected clock source is slow clock. the pres field is used to control the master clock prescaler. the user can choose between different values (1, 2, 4, 8, 16, 32, 64). master clock output is prescaler input 231 6062b?atarm?15-nov-05 at91sam9261 divided by pres parameter. by default, pres parameter is set to 1 which means that master clock is equal to slow clock. the mdiv field is used to control the master clock prescaler. it is possible to choose between different values (0, 1, 2). the master clock output is processor clock divided by 1, 2 or 4, depending on the value programmed in mdiv. by default, mdiv is set to 0, which indicates that the processor clock is equal to the master clock. once the pmc_mckr register has been written, the user must wait for the mckrdy bit to be set in the pmc_sr register. this can be done either by po lling the status register or by waiting for the interrupt line to be raised if the associated interrupt to mckrdy has been enabled in the pmc_ier register. the pmc_mckr register must not be programmed in a single write operation. the pre- ferred programming sequence for the pmc_mckr register is as follows: if a new value for css field corresponds to pll clock, ? program the pres field in the pmc_mckr register. ? wait for the mckrdy bit to be set in the pmc_sr register. ? program the css field in the pmc_mckr register. ? wait for the mckrdy bit to be set in the pmc_sr register. if a new value for css field corresponds to main clock or slow clock, ? program the css field in the pmc_mckr register. ? wait for the mckrdy bit to be set in the pmc_sr register. ? program the pres field in the pmc_mckr register. ? wait for the mckrdy bit to be set in the pmc_sr register. if at some stage one of the following parameters, css or pres, is modified, the mckrdy bit will go low to indicate that the master clock an d the processor clock are not ready yet. the user must wait for mckrdy bit to be set again before using the master and processor clocks. note: if pllx clock was selected as the master clock and the user decides to modify it by writing in ckgr_pllr (ckgr_pllar or ckgr_pllbr), the mckrdy flag will go low while pll is unlocked. once pll is locked again, lock (locka or lockb) goes high and mckrdy is set. while plla is unlocked, the master clock sele ction is automatically changed to slow clock.. while pllb is unlocked, the master clock select ion is automatically changed to main clock. for further information, see section 25.10.2 . ?clock switching waveforms? on page 238 . code example: write_register(pmc_mckr,0x00000001) wait (mckrdy=1) write_register(pmc_mckr,0x00000011) wait (mckrdy=1) the master clock is main clock divided by 16. the processor clock is the master clock. 232 6062b?atarm?15-nov-05 at91sam9261 6. selection of programmable clocks programmable clocks are controlled vi a registers; pmc_scer, pmc_scdr and pmc_scsr. programmable clocks can be enabled and/or disabled via the pmc_scer and pmc_scdr registers. depend ing on the system used, 4 programmable clocks can be enabled or disabled. the pmc_scsr provides a clear indication as to which programma- ble clock is enabled. by default all programmable clocks are disabled. pmc_pckx registers are used to configure programmable clocks. the css field is used to select the programmable clock divider source. four clock options are available: main clock, slow clock, p llack, pllbck. by default, the clock source selected is slow clock. the pres field is used to control the programmable clock prescaler. it is possible to choose between different values (1, 2, 4, 8, 16, 32, 64). programmable clock output is prescaler input divided by pres parameter. by default, the pres parameter is set to 1 which means that master clock is equal to slow clock. once the pmc_pckx register has been programmed, the corresponding programmable clock must be enabled and the user is constrained to wait for the pckrdyx bit to be set in the pmc_sr register . this can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to pckrdyx has been enabled in the pmc_ier register. all para meters in pmc_pckx can be programmed in a single write operation. if the css and pres parameters are to be modified, the corresponding programmable clock must be disabled first. the parameters can then be modified. once this has been done, the user must re-enable the programmable clock and wait for the pckrdyx bit to be set. code example: write_register(pmc_pck0,0x00000015) programmable clock 0 is main clock divided by 32. 7. enabling peripheral clocks once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via registers pmc_pcer and pmc_pcdr. depending on the system used, 17 peripheral clocks can be enabled or disabled. the pmc_pcsr provides a clear view as to which peripheral clock is enabled. note: each enabled peripheral clock corresponds to master clock. code examples: write_register(pmc_pcer,0x00000110) 233 6062b?atarm?15-nov-05 at91sam9261 peripheral clocks 4 and 8 are enabled. write_register(pmc_pcdr,0x00000010) peripheral clock 4 is disabled. 8. enabling hclocks once all of the previous st eps have been completed, the hclocks can be enabled and/or disabled via registers; pmc_scer and pmc_scdr. depending on the system used, 1 hclocks can be enabled or disabled. the pmc_scsr register indi cates which hclock is enabled. note: each enabled hclock corresponds to master clock. code examples: write_register(pmc_scer,0x00110000) hclocks 0 and 4 are enabled. 234 6062b?atarm?15-nov-05 at91sam9261 25.9 clock switching details 25.9.1 master clock switching timings table 25-1 and table 25-2 give the worst case timings required for the master clock to switch from one selected clock to another one. this is in the event that the prescaler is de-activated. when the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. notes: 1. pll designates either the pll a or the pll b clock. 2. pllcount designates eit her pllacount or pllbcount. table 25-1. clock switching timings (worst case) from main clock slck pll clock to main clock ? 4 x slck + 2.5 x main clock 3 x pll clock + 4 x slck + 1 x main clock slck 0.5 x main clock + 4.5 x slck ? 3 x pll clock + 5 x slck pll clock 0.5 x main clock + 4 x slck + pllcount x slck + 2.5 x pllx clock 2.5 x pll clock + 5 x slck + pllcount x slck 2.5 x pll clock + 4 x slck + pllcount x slck table 25-2. clock switching timings between two plls (worst case) from plla clock pllb clock to plla clock 2.5 x plla clock + 4 x slck + pllacount x slck 3 x plla clock + 4 x slck + 1.5 x plla clock pllb clock 3 x pllb clock + 4 x slck + 1.5 x pllb clock 2.5 x pllb clock + 4 x slck + pllbcount x slck 235 6062b?atarm?15-nov-05 at91sam9261 25.9.2 clock switching waveforms figure 25-3. switch master clock from slow clock to pll clock figure 25-4. switch master clo ck from main clock to slow clock slow clock lock mckrdy master clock write pmc_mckr pll clock slow clock main clock mckrdy master clock write pmc_mckr 236 6062b?atarm?15-nov-05 at91sam9261 figure 25-5. change plla programming figure 25-6. change pllb programming slow clock slow clock plla clock lock mckrdy master clock write ckgr_pllar main clock main clock pllb clock lock mckrdy master clock write ckgr_pllbr 237 6062b?atarm?15-nov-05 at91sam9261 figure 25-7. programmable clock output programming pll clock pckrdy pckx output write pmc_pckx write pmc_scer write pmc_scdr pckx is disabled pckx is enabled pll clock is selected 238 6062b?atarm?15-nov-05 at91sam9261 25.10 power management contro ller (pmc) user interface table 25-3. register mapping offset register name access reset value 0x0000 system clock enable register pmc_scer write-only ? 0x0004 system clock disable register pmc_scdr write-only ? 0x0008 system clock status register pmc _scsr read-only 0x03 0x000c reserved ? ? ? 0x0010 peripheral clock enable register pmc _pcer write-only ? 0x0014 peripheral clock disable register pmc_pcdr write-only ? 0x0018 peripheral clock status register pmc_pcsr read-only 0x0 0x001c reserved ? ? ? 0x0020 main oscillator register ckgr_mor read/write 0x0 0x0024 main clock frequency register ckgr_mcfr read-only 0x0 0x0028 pll a register ckgr_pllar readwrite 0x3f00 0x002c pll b register ckgr_pllbr readwrite 0x3f00 0x0030 master clock register pmc_mckr read/write 0x0 0x0034 application clock register pmc_ackr read/write 0x0 0x0038 reserved ? ? ? 0x003c reserved ? ? ? 0x0040 programmable clock 0 register pmc_pck0 read/write 0x0 0x0044 programmable clock 1 register pmc_pck1 read/write 0x0 ... ... ... ... ... 0x0060 interrupt enable register pmc_ier write-only -- 0x0064 interrupt disable register pmc_idr write-only -- 0x006c interrupt mask register pmc_imr read-only 0x0 0x0070 - 0x00fc reserved ? ? ? 239 6062b?atarm?15-nov-05 at91sam9261 25.10.1 pmc system clock enable register register name: pmc_scer access type: write-only pck: processor clock enable 0 = no effect. 1 = enables the processor clock. uhp: usb host port clock enable 0 = no effect. 1 = enables the 12 and 48 mhz clock of the usb host port. udp: usb device port clock enable 0 = no effect. 1 = enables the 48 mhz clock of the usb device port. pckx: programmable clock x output enable 0 = no effect. 1 = enables the corresponding programmable clock output. hckx: hclock x output enable 0 = no effect. 1 = enables the corresponding hclock output. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????hck0 15 14 13 12 11 10 9 8 ????pck3pck2pck1pck0 76543210 udpuhp?????pck 240 6062b?atarm?15-nov-05 at91sam9261 25.10.2 pmc system clock disable register register name: pmc_scdr access type: write-only pck: processor clock disable 0 = no effect. 1 = disables the processor clock. this is used to enter the processor in idle mode. uhp: usb host port clock disable 0 = no effect. 1 = disables the 12 and 48 mhz clock of the usb host port. udp: usb device port clock disable 0 = no effect. 1 = disables the 48 mhz clock of the usb device port. pckx: programmable clock x output disable 0 = no effect. 1 = disables the corresponding programmable clock output. hckx: hclock x output disable 0 = no effect. 1 = disables the corresponding hclock output. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????hck0 15 14 13 12 11 10 9 8 ????pck3pck2pck1pck0 76543210 udpuhp?????pck 241 6062b?atarm?15-nov-05 at91sam9261 25.10.3 pmc system clock status register register name: pmc_scsr access type: read-only pck: processor clock status 0 = the processor clock is disabled. 1 = the processor clock is enabled. uhp: usb host port clock status 0 = the 12 and 48 mhz clock (uhpck) of the usb host port is disabled. 1 = the 12 and 48 mhz clock (uhpck) of the usb host port is enabled. udp: usb device port clock status 0 = the 48 mhz clock (udpck) of th e usb device port is disabled. 1 = the 48 mhz clock (udpck) of the usb device port is enabled. pckx: programmable clock x output status 0 = the corresponding programmable clock output is disabled. 1 = the corresponding programmable clock output is enabled. hckx: hclock output x status 0 = the corresponding hclo ck output is disabled. 1 = the corresponding hclo ck output is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????hck0 15 14 13 12 11 10 9 8 ????pck3pck2pck1pck0 76543210 udpuhp?????pck 242 6062b?atarm?15-nov-05 at91sam9261 25.10.4 pmc peripheral clock enable register register name: pmc_pcer access type: write-only pidx: peripheral clock x enable 0 = no effect. 1 = enables the corresponding peripheral clock. note: programming the control bits of the peripheral id that ar e not implemented has no effect on the behavior of the pmc. 25.10.5 pmc peripheral clock disable register register name: pmc_pcdr access type: write-only pidx: peripheral clock x disable 0 = no effect. 1 = disables the corresponding peripheral clock. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 - - 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 - - 243 6062b?atarm?15-nov-05 at91sam9261 25.10.6 pmc peripheral clock status register register name: pmc_pcsr access type: read-only pidx: peripheral clock x status 0 = the corresponding peripheral clock is disabled. 1 = the corresponding peripheral clock is enabled. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 ? ? 244 6062b?atarm?15-nov-05 at91sam9261 25.10.7 pmc clock generator main oscillator register register name: ckgr_mor access type: read/write moscen: main oscillator enable a crystal must be connected between xin and xout. 0 = the main oscillator is disabled. 1 = the main oscillator is enabl ed. oscbypass must be set to 0. when moscen is set, the moscs flag is set once the main oscillator startup time is achieved. oscbypass: oscillator bypass 0 = no effect. 1 = the main oscillator is bypassed. moscen must be set to 0. an exter nal clock must be connected on xin. when oscbypass is set, th e moscs flag in pmc_sr is automatically set. clearing moscen and oscbypass bits allows resetting the moscs flag. oscount: main oscillator start-up time specifies the number of slow clock cycles multip lied by 8 for the main o scillator start-up time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 oscount 76543210 ??????oscbypassmoscen 245 6062b?atarm?15-nov-05 at91sam9261 25.10.8 pmc clock generator main clock frequency register register name: ckgr_mcfr access type: read-only mainf: main clock frequency gives the number of main clock cycles within 16 slow clock periods. mainrdy: main clock ready 0 = mainf value is not valid or the main oscillator is disabled. 1 = the main oscillator has been enabled pr eviously and mainf value is available. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????mainrdy 15 14 13 12 11 10 9 8 mainf 76543210 mainf 246 6062b?atarm?15-nov-05 at91sam9261 25.10.9 pmc clock generator pll a register register name: ckgr_pllar access type: read/write possible limitations on pll a input frequencies and multiplier factors should be checked before using the pmc. warning: bit 29 must always be set to 1 when programming the ckgr_pllar register. diva: divider a pllacount: pll a counter specifies the number of slow clock cycles before the lo cka bit is set in pmc_sr af ter ckgr_pllar is written. outa: pll a clock frequency range mula: pll a multiplier 0 = the pll a is deactivated. 1 up to 2047 = the pll a clock frequency is the pll a input frequency multiplied by mula + 1. 31 30 29 28 27 26 25 24 ??1?? mula 23 22 21 20 19 18 17 16 mula 15 14 13 12 11 10 9 8 outa pllacount 76543210 diva diva divider selected 0 divider output is 0 1 divider is bypassed 2 - 255 divider output is the main clock divided by diva. outa pll a frequency output range 0 0 refer to the dc characteristics section of the product datasheet 01reserved 1 0 refer to the dc characteristics section of the product datasheet 11reserved 247 6062b?atarm?15-nov-05 at91sam9261 25.10.10 pmc clock generator pll b register register name: ckgr_pllbr access type: read/write possible limitations on pll b input frequencies and multiplier factors should be checked before using the pmc. divb: divider b pllbcount: pll b counter specifies the number of slow clock cycles before the lo ckb bit is set in pmc_sr after ckgr_pllbr is written. outb: pllb clock frequency range mulb: pll multiplier 0 = the pll b is deactivated. 1 up to 2047 = the pll b clock frequency is the pll b input frequency multiplied by mulb + 1. usbdiv: divider for usb clock 31 30 29 28 27 26 25 24 ? ? usbdiv ? mulb 23 22 21 20 19 18 17 16 mulb 15 14 13 12 11 10 9 8 outb pllbcount 76543210 divb divb divider selected 0 divider output is 0 1 divider is bypassed 2 - 255 divider output is the selected clock divided by divb. outb pll b clock frequency range 0 0 refer to the dc characteristics section of the product datasheet 01reserved 1 0 refer to the dc characteristics section of the product datasheet 11reserved usbdiv divider for usb clock(s) 0 0 divider output is pll b clock output. 0 1 divider output is pll b clock output divided by 2. 1 0 divider output is pll b clock output divided by 4. 1 1 reserved. 248 6062b?atarm?15-nov-05 at91sam9261 25.10.11 pmc master clock register register name: pmc_mckr access type: read/write css: master clock selection pres: master clock prescaler mdiv: master clock division 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? mdiv 76543210 ? ? ? pres css css clock source selection 0 0 slow clock is selected 0 1 main clock is selected 1 0 pll a clock is selected 1 1 pll b clock is selected pres master clock 0 0 0 selected clock 0 0 1 selected clock divided by 2 0 1 0 selected clock divided by 4 0 1 1 selected clock divided by 8 1 0 0 selected clock divided by 16 1 0 1 selected clock divided by 32 1 1 0 selected clock divided by 64 111reserved mdiv master clock division 0 0 master clock is processor clock. 0 1 master clock is proce ssor clock divided by 2. 1 0 master clock is proce ssor clock divided by 4. 1 1 reserved. 249 6062b?atarm?15-nov-05 at91sam9261 25.10.12 pmc programmable clock register register name: pmc_pckx access type: read/write css: master clock selection pres: programmable clock prescaler 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? pres css css clock source selection 0 0 slow clock is selected 0 1 main clock is selected 1 0 pll a clock is selected 1 1 pll b clock is selected pres master clock 0 0 0 selected clock 0 0 1 selected clock divided by 2 0 1 0 selected clock divided by 4 0 1 1 selected clock divided by 8 1 0 0 selected clock divided by 16 1 0 1 selected clock divided by 32 1 1 0 selected clock divided by 64 111reserved 250 6062b?atarm?15-nov-05 at91sam9261 25.10.13 pmc interrupt enable register register name: pmc_ier access type: write-only moscs: main oscillator status interrupt enable locka: pll a lock interrupt enable lockb: pll b lock interrupt enable mckrdy: master clock ready interrupt enable pckrdyx: programmable clock ready x interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????pckrdy3pckrdy2pckrdy1pckrdy0 76543210 ??? ? mckrdy lockb locka moscs 251 6062b?atarm?15-nov-05 at91sam9261 25.10.14 pmc interrupt disable register register name: pmc_idr access type: write-only moscs: main oscillator status interrupt disable locka: pll a lock interrupt disable lockb: pll b lock interrupt disable mckrdy: master clock ready interrupt disable pckrdyx: programmable clock ready x interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????pckrdy3pckrdy2pckrdy1pckrdy0 76543210 ??? ? mckrdy lockb locka moscs 252 6062b?atarm?15-nov-05 at91sam9261 25.10.15 pmc status register register name: pmc_sr access type: read-only moscs: moscs flag status 0 = main oscillator is not stabilized. 1 = main oscillator is stabilized. locka: pll a lock status 0 = pll a is not locked 1 = pll a is locked. lockb: pll b lock status 0 = pll b is not locked. 1 = pll b is locked. mckrdy: master clock status 0 = master clock is not ready. 1 = master clock is ready. pckrdyx: programmable clock ready status 0 = programmable clock x is not ready. 1 = programmable clock x is ready. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????pckrdy3pckrdy2pckrdy1pckrdy0 76543210 ??? ? mckrdy lockb locka moscs 253 6062b?atarm?15-nov-05 at91sam9261 25.10.16 pmc interrupt mask register register name: pmc_imr access type: read-only moscs: main oscillator status interrupt mask locka: pll a lock interrupt mask lockb: pll b lock interrupt mask mckrdy: master clock ready interrupt mask pckrdyx: programmable clock ready x interrupt mask 0 = the corresponding interrupt is enabled. 1 = the corresponding interrupt is disabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????pckrdy3pckrdy2pckrdy1pckrdy0 76543210 ??? ? mckrdy lockb locka moscs 259 6062b?atarm?15-nov-05 at91sam9261 26. advanced interrupt controller (aic) 26.1 description the advanced interrupt controller (aic) is an 8- level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. it is designed to substantially reduce the software and real-time overhead in handling internal and external interrupts. the aic drives the nfiq (fast interrupt request) and the nirq (standard interrupt request) inputs of an arm processor. inputs of the aic are either internal peripheral interrupts or exter- nal interrupts coming from the product's pins. the 8-level priority controller allows the user to define the priority for each interrupt source, thus permitting higher priority interrupts to be serviced even if a lower priority interrupt is being treated. internal interrupt sources can be programmed to be level sensitive or edge triggered. external interrupt sources can be programmed to be positive-edge or negative-edge triggered or high- level or low-level sensitive. the fast forcing feature redirects any internal or external interrupt source to provide a fast interrupt rather than a normal interrupt. 26.2 block diagram figure 26-1. block diagram 26.3 application block diagram figure 26-2. description of the application block aic apb arm processor fiq irq0-irqn embedded peripheralee peripheral embedded peripheral embedded up to thirty-two sources nfiq nirq advanced interrupt controller embedded peripherals external peripherals (external interrupts) standalone applications rtos drivers hard real time tasks os-based applications os drivers general os interrupt handler 260 6062b?atarm?15-nov-05 at91sam9261 26.4 aic detailed block diagram figure 26-3. aic detailed block diagram 26.5 i/o line description 26.6 product dependencies 26.6.1 i/o lines the interrupt signals fiq and irq0 to irqn are normally multiplexed through the pio control- lers. depending on the features of the pio cont roller used in the product, the pins must be programmed in accordance with their assigned inte rrupt function. this is not applicable when the pio controller used in the product is transparent on the input path. 26.6.2 power management the advanced interrupt controller is continuously clocked. the power management controller has no effect on the advanced interrupt controller behavior. the assertion of the advanced interrupt controller outputs, either nirq or nfiq, wakes up the arm processor while it is in idle mode. the general interrupt mask feature enables the aic to wake up the processor without asserting the interrupt line of the processor, thus providing syn- chronization of the processor on an event. 26.6.3 interrupt sources the interrupt source 0 is always located at fiq. if the product does not feature an fiq pin, the interrupt source 0 cannot be used. fiq pio controller advanced interrupt controller irq0-irqn pioirq embedded peripherals external source input stage internal source input stage fast forcing interrupt priority controller fast interrupt controller arm processor nfiq nirq power management controller wake up user interface apb processor clock table 26-1. i/o line description pin name pin description type fiq fast interrupt input irq0 - irqn interrupt 0 - interrupt n input 261 6062b?atarm?15-nov-05 at91sam9261 the interrupt source 1 is always located at syst em interrupt. this is the result of the or-wir- ing of the system peripheral interrupt lines, such as the system timer, the real time clock, the power management controller and the memory controller. when a system interrupt occurs, the service routine must first distinguis h the cause of the interrupt. this is performed by reading successively the status register s of the above mentioned system peripherals. the interrupt sources 2 to 31 can either be connected to the interrupt outputs of an embedded user peripheral or to external interrupt lines. the external interrupt lines can be connected directly, or through the pio controller. the pio controllers are considered as user peripherals in the scope of interrupt handling. accordingly, the pio controller interrupt lines are connected to the interrupt sources 2 to 31. the peripheral identification defined at the pr oduct level corresponds to the interrupt source number (as well as the bit number controlling the clock of the peripheral). consequently, to simplify the description of the functional operations and the user interface, the interrupt sources are named fiq, sys, and pid2 to pid31. 26.7 functional description 26.7.1 interrupt source control 26.7.1.1 interrupt source mode the advanced interrupt controller independently programs each interrupt source. the src- type field of the corresponding aic_smr (source mode register) selects the interrupt condition of each source. the internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode. the active level of the internal interrupts is not important for the user. the external interrupt sources can be programmed either in high level-sensitive or low level- sensitive modes, or in positive edge-triggered or negative edge-triggered modes. 26.7.1.2 interrupt source enabling each interrupt source, including the fiq in source 0, can be enabled or disabled by using the command registers; aic_iecr (interrupt enable command register) and aic_idcr (inter- rupt disable command register). this set of registers conducts enabling or disabling in one instruction. the interrupt mask can be read in the aic_imr register. a disabled interrupt does not affect servicing of other interrupts. 26.7.1.3 interrupt clearing and setting all interrupt sources programmed to be edge-triggered (including the fiq in source 0) can be individually set or cleared by writing resp ectively the aic_iscr and aic_iccr registers. clearing or setting interrupt sources programmed in level-sensitive mode has no effect. the clear operation is perfunctory, as the software must perform an action to reinitialize the ?memorization? circuitry activated when the source is programmed in edge-triggered mode. however, the set operation is available for auto-test or software debug purposes. it can also be used to execute an aic-implementation of a software interrupt. the aic features an automatic clear of the current interrupt when the aic_ivr (interrupt vec- tor register) is read. only the interrupt source being detected by the aic as the current 262 6062b?atarm?15-nov-05 at91sam9261 interrupt is affected by this operation. ( see ?priority controller? on page 265. ) the automatic clear reduces the operations required by the interrupt service routine entry code to reading the aic_ivr. note that the automatic interrupt clear is disabled if the interrupt source has the fast forcing feature enabled as it is considered un iquely as a fiq source. (for further details, see ?fast forcing? on page 269. ) the automatic clear of the interrupt source 0 is performed when aic_fvr is read. 26.7.1.4 interrupt status for each interrupt, the aic operation originates in aic_ipr (interrupt pending register) and its mask in aic_imr (interrupt mask register). aic_ipr enables the actual activity of the sources, whether masked or not. the aic_isr register reads the number of the current interrupt (see ?priority controller? on page 265 ) and the register aic_cisr gives an image of the signals nirq and nfiq driven on the processor. each status referred to above can be used to optimize the interrupt handling of the systems. 26.7.1.5 internal interrupt source input stage figure 26-4. internal interrupt source input stage edge detector clear set source i aic_ipr aic_imr aic_iecr aic_idcr aic_iscr aic_iccr fast interrupt controller or priority controller ff level/ edge aic_smri (srctype) 263 6062b?atarm?15-nov-05 at91sam9261 26.7.1.6 external interrupt source input stage figure 26-5. external interrupt source input stage 26.7.2 interrupt latencies global interrupt latencies depend on several parameters, including: the time the software masks the interrupts. occurrence, either at the processor level or at the aic level. the execution time of the instruction in progress when the interrupt occurs. the treatment of higher priority interrupts and the resynchronization of the hardware signals. this section addresses only the hardware resynchronizations. it gives details of the latency times between the event on an external interrupt leading in a valid interrupt (edge or level) or the assertion of an internal interrupt source and the assertion of the nirq or nfiq line on the processor. the resynchronization time depends on the programming of the interrupt source and on its type (internal or external). for the standard interrupt, resynchronization times are given assuming there is no higher priority in progress. the pio controller multiplexing has no effect on the interrupt latencies of the external interrupt sources. edge detector clear set pos./neg. aic_iscr aic_iccr source i ff level/ edge high/low aic_smri srctype aic_ipr aic_imr aic_iecr aic_idcr fast interrupt controller or priority controller 264 6062b?atarm?15-nov-05 at91sam9261 26.7.2.1 external interrupt edge triggered source figure 26-6. external interrupt edge triggered source 26.7.2.2 external interrupt level sensitive source figure 26-7. external interrupt level sensitive source 26.7.2.3 internal interrupt edge triggered source figure 26-8. internal interrupt edge triggered source maximum fiq latency = 4 cycles maximum irq latency = 4 cycles nfiq nirq mck irq or fiq (positive edge) irq or fiq (negative edge) maximum irq latency = 3 cycles maximum fiq latency = 3 cycles mck irq or fiq (high level) irq or fiq (low level) nirq nfiq mck nirq peripheral interrupt becomes active maximum irq latency = 4.5 cycles 265 6062b?atarm?15-nov-05 at91sam9261 26.7.2.4 internal interrupt level sensitive source figure 26-9. internal interrupt level sensitive source 26.7.3 normal interrupt 26.7.3.1 priority controller an 8-level priority controller drives the nirq line of the processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 31 (except for those programmed in fast forcing). each interrupt source has a programmable priority level of 7 to 0, whic h is user-definable by writing the prior field of the corresponding aic_smr (source mode register). level 7 is the highest priority and level 0 the lowest. as soon as an interrupt condition occurs, as defined by the srctype field of the aic_svr (source vector register), the nirq line is asserted. as a new interrupt condition might have happened on other interrupt sources since the nirq has been asserted, the priority controller determines the current interrupt at the time the aic_ivr (interrupt vector register) is read. the read of aic_ivr is the entry point of the interrupt handling which allows the aic to consider that the interrupt has been taken into account by the software. the current priority level is defined as the priority level of the current interrupt. if several interrupt sources of equal priority are pending and enabled when the aic_ivr is read, the interrupt with the lowest interrupt source number is serviced first. the nirq line can be asserted only if an interrupt condition occurs on an interrupt source with a higher priority. if an interrupt condition happens (or is pending) during the interrupt treatment in progress, it is delayed until the software indicates to the aic the end of the current service by writing the aic_eoicr (end of interrupt command register). the write of aic_eoicr is the exit point of the interrupt handling . 26.7.3.2 interrupt nesting the priority controller utilizes inte rrupt nesting in order for the high priori ty interrupt to be han- dled during the service of lower priority interrupt s. this requires the interrupt service routines of the lower interrupts to re-enable the interrupt at the processor level. when an interrupt of a higher priority happens during an already occurring interrupt service routine, the nirq line is re-asserted. if the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt service routine should read the aic_ivr. at this time, the current interrupt number and its priority level are pushed into an embedded hardware mck nirq maximum irq latency = 3.5 cycles peripheral interrupt becomes active 266 6062b?atarm?15-nov-05 at91sam9261 stack, so that they are saved and restored when the higher priority interrupt servicing is fin- ished and the aic_eoicr is written. the aic is equipped with an 8-level wide hardware stack in order to support up to eight inter- rupt nestings pursuant to having eight priority levels. 26.7.3.3 interrupt vectoring the interrupt handler addresses corresponding to each interrupt source can be stored in the registers aic_svr1 to aic_svr31 (source ve ctor register 1 to 31). when the processor reads aic_ivr (interrupt vector register), the value written into aic_svr corresponding to the current interrupt is returned. this feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as aic_ivr is mapped at the absolute address 0xffff f100 and thus accessible from the arm interrupt vector at address 0x0000 0018 through the following instruction: ldr pc,[pc,# -&f20] when the processor executes this instruction, it loads the read value in aic_ivr in its program counter, thus branching the execution on the correct interrupt handler. this feature is often not used when the application is based on an operating system (either real time or not). operating systems often have a single entry point fo r all the interrupts and the first task performed is to discern the source of the interrupt. however, it is strongly recommended to port th e operating system on at91 products by sup- porting the interrupt vectoring. this can be performed by defining all the aic_svr of the interrupt source to be handled by the operating system at the address of its interrupt handler. when doing so, the interrupt vectoring permits a critical interrupt to transfer the execution on a specific very fast handler and not onto the operating system?s general interrupt handler. this facilitates the support of hard real-time tasks (input/outputs of voice/audio buff ers and software peripheral handling) to be handled efficiently and independently of the application running under an operating system. 26.7.3.4 interrupt handlers this section gives an overview of the fast interrupt handling sequence when using the aic. it is assumed that the programmer understands the architecture of the arm processor, and especially the processor interrupt modes and the associated status bits. it is assumed that: 1. the advanced interrupt controller has been programmed, aic_svr registers are loaded with corresponding interrupt service routine addresses and interrupts are enabled. 2. the instruction at the arm interrupt exception vector address is required to work with the vectoring ldr pc, [pc, # -&f20] when nirq is asserted, if the bit ?i? of cpsr is 0, the sequence is as follows: 1. the cpsr is stored in spsr _irq, the curren t value of the program counter is loaded in the interrupt link register (r14_irq) and the program counter (r15) is loaded with 0x18. in the following cycle during fetch at address 0x1c, the arm core adjusts r14_irq, decrementing it by four. 2. the arm core enters interrupt mode, if it has not already done so. 267 6062b?atarm?15-nov-05 at91sam9261 3. when the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in aic_iv r. reading the aic_ivr has the following effects: ? sets the current interrupt to be the pending and enabled interrupt with the highest priority. the current level is the priority level of the current interrupt. ? de-asserts the nirq line on the processor. even if vectoring is not used, aic_ivr must be read in order to de-assert nirq. ? automatically clears the interrupt, if it has been programmed to be edge-triggered. ? pushes the current level and the current interrupt number on to the stack. ? returns the value written in the aic_svr corresponding to the current interrupt. 4. the previous step has the effect of branc hing to the corresponding interrupt service routine. this should start by saving the link register (r14_irq) and spsr_irq. the link register must be decremented by four when it is saved if it is to be restored directly into the program counter at the end of the interrupt. for example, the instruc- tion sub pc, lr, #4 may be used. 5. further interrupts can then be unmasked by clearing the ?i? bit in cpsr, allowing re- assertion of the nirq to be taken into account by the core. this can happen if an interrupt with a higher priority than the current interrupt occurs. 6. the interrupt handler can th en proceed as required, savi ng the registers that will be used and restoring them at the end. during this phase, an interrupt of higher priority than the current leve l will restart the sequence from step 1. note: if the interrupt is programmed to be level sens itive, the source of the interrupt must be cleared during this phase. 7. the ?i? bit in cpsr must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner. 8. the end of interrupt command register (aic_eoicr) must be written in order to indicate to the aic that the current interrupt is finished. this causes the current level to be popped from the stack, restoring the previous current level if one exists on the stack. if another interrupt is pending, with lower or equal priority than the old current level but with higher priority than the new current level, the nirq line is re-asserted, but the interrupt sequence does not immediately start because the ?i? bit is set in the core. spsr_irq is restored. finally, the save d value of the link r egister is restored directly into the pc. this has the effect of returning from the interrupt to whatever was being executed before, and of loading th e cpsr with the stored spsr, masking or unmasking the interrupts depending on the state saved in spsr_irq. note: the ?i? bit in spsr is significant. if it is set, it indicates that the arm core was on the verge of masking an interrupt when the mask instruct ion was interrupted. h ence, when spsr is restored, the mask instruction is completed (interrupt is masked). 26.7.4 fast interrupt 26.7.4.1 fast interrupt source the interrupt source 0 is the only source which can raise a fast interrupt request to the proces- sor except if fast forcing is used. the interrupt source 0 is generally connected to a fiq pin of the product, either directly or through a pio controller. 26.7.4.2 fast interrupt control the fast interrupt logic of the aic has no priority controller. the mode of interrupt source 0 is programmed with the aic_smr0 and the field prior of this register is not used even if it reads what has been written. the field sr ctype of aic_smr0 enables programming the 268 6062b?atarm?15-nov-05 at91sam9261 fast interrupt source to be positive-edge triggered or negative-edge triggered or high-level sen- sitive or low-level sensitive writing 0x1 in the aic_iecr (interrupt enable command register) a nd aic_idcr (interrupt disable command register) respec tively enables and disables the fast interrupt. the bit 0 of aic_imr (interrupt mask register) indicates whet her the fast interrupt is enabled or disabled. 26.7.4.3 fast interrupt vectoring the fast interrupt handler address can be stored in aic_svr0 (source vector register 0). the value written into this register is returned when the processor reads aic_fvr (fast vec- tor register). this offers a way to branch in one single instruction to the interrupt handler, as aic_fvr is mapped at the absolute address 0x ffff f104 and thus accessible from the arm fast interrupt vector at address 0x0000 001c through the following instruction: ldr pc,[pc,# -&f20] when the processor executes th is instruction it loads the va lue read in aic_fvr in its pro- gram counter, thus branching the execution on the fast interrupt handler. it also automatically performs the clear of the fast interrupt source if it is programmed in edge-triggered mode. 26.7.4.4 fast interrupt handlers this section gives an overview of the fast interrupt handling sequence when using the aic. it is assumed that the programmer understands the architecture of the arm processor, and especially the processor interrupt modes and associated status bits. assuming that: 1. the advanced interrupt controller has been programmed, aic_svr0 is loaded with the fast interrupt service routine address, and the interrupt source 0 is enabled. 2. the instruction at address 0x1c (fiq exception vector address) is required to vector the fast interrupt: ldr pc, [pc, # -&f20] 3. the user does not need nested fast interrupts. when nfiq is asserted, if the bit "f" of cpsr is 0, the sequence is: 1. the cpsr is stored in spsr _fiq, the current va lue of the program counter is loaded in the fiq link register (r14_fiq) and the program counter (r15) is loaded with 0x1c. in the following cycle, during fetch at address 0x20, the arm core adjusts r14_fiq, decrementing it by four. 2. the arm core enters fiq mode. 3. when the instruction loaded at address 0x1c is executed, the program counter is loaded with the value read in aic_fvr. reading the aic_fvr has effect of automat- ically clearing the fast interrupt, if it has been programmed to be edge triggered. in this case only, it de-asserts the nfiq line on the processor. 4. the previous step enables branching to the corresponding interrupt service routine. it is not necessary to save the link register r14_fiq and spsr_fiq if nested fast inter- rupts are not needed. 5. the interrupt handler can then proceed as required. it is not necessary to save regis- ters r8 to r13 because fiq mode has its own dedicated registers and the user r8 to r13 are banked. the other registers, r0 to r7, must be saved before being used, and restored at the end (before the next step). note that if the fast interrupt is pro- grammed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the interrupt source 0. 269 6062b?atarm?15-nov-05 at91sam9261 6. finally, the link register r14_fiq is restored into the pc after decrementing it by four (with instruction sub pc, lr, #4 for example). this has the effect of returning from the interrupt to whatever was being executed before, loading the cpsr with the spsr and masking or unmasking the fast in terrupt depending on the state saved in the spsr. note: the "f" bit in spsr is significant. if it is se t, it indicates that the ar m core was just about to mask fiq interrupts when the mask instructio n was interrupted. hence when the spsr is restored, the interrupted instructi on is completed (fiq is masked). another way to handle the fast interrupt is to map the interrupt service routine at the address of the arm vector 0x1c. this method does not use the vectoring, so that reading aic_fvr must be performed at the very beginning of the handler operation. however, this method saves the execution of a branch instruction. 26.7.4.5 fast forcing the fast forcing feature of the advanced interrupt controller provides redirection of any nor- mal interrupt source on the fast interrupt controller. fast forcing is enabled or disabled by writ ing to the fast forcing enable register (aic_ffer) and the fast forcing disable regi ster (aic_ffdr). writing to these registers results in an update of the fast forcing status register (aic_ffsr) that controls the feature for each internal or external interrupt source. when fast forcing is disabled, the interrupt sources are handled as described in the previous pages. when fast forcing is enabled, the edge/level programming and, in certain cases, edge detec- tion of the interrupt source is st ill active but the source cannot tr igger a normal in terrupt to the processor and is not seen by the priority handler. if the interrupt source is programmed in level-sensitive mode and an active level is sampled, fast forcing results in the assertion of the nfiq line to the core. if the interrupt source is programmed in edge-triggered mode and an active edge is detected, fast forcing results in the assertion of the nfiq line to the core. the fast forcing feature does not affect the source 0 pending bit in the interrupt pending register (aic_ipr). the fast interrupt vector register (aic_fvr) reads the contents of the source vector regis- ter 0 (aic_svr0), whatever the source of the fast interrupt may be. the read of the fvr does not clear the source 0 when the fast forcing feature is used and the interrupt source should be cleared by writin g to the inte rrupt clear command register (aic_iccr). all enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in edge-triggered mode must be cleared by writing to the interrupt clear command register. in doing so, they are cleared independently and thus lost interrupts are prevented. the read of aic_ivr does not clear the source that has the fast forcing feature enabled. the source 0, reserved to the fast interrupt, continues operating normally and becomes one of the fast interrupt sources. 270 6062b?atarm?15-nov-05 at91sam9261 figure 26-10. fast forcing 26.7.5 protect mode the protect mode permits reading the interrupt vector register without performing the associ- ated automatic operations. this is necessary when working with a debug system. when a debugger, working either with a debug monitor or the arm processor's ice, stops the applica- tions and updates the opened windows, it might re ad the aic user interface and thus the ivr. this has undesirable consequences: if an enabled interrupt with a higher priority than the current one is pending, it is stacked. if there is no enabled pending interrupt, the spurious vector is returned. in either case, an end of interrupt command is necessary to acknowledge and to restore the context of the aic. this operation is generally not performed by the debug system as the debug system would become strongly intrusive and cause the application to enter an undes- ired state. this is avoided by using the protect mode. writing dbgm in aic_dcr (debug control regis- ter) at 0x1 enables the protect mode. when the protect mode is enabled, the aic performs interrupt stacking only when a write access is performed on the aic_ivr. therefore, the interrupt service routines must write (arbitrary data) to the aic_ivr just after reading it. the new context of the aic, including the value of the interrupt status register (aic_isr), is updated with the current interrupt only when aic_ivr is written. an aic_ivr read on its own (e.g., by a debugger), modifies neither the aic context nor the aic_isr. extra aic_ivr reads perform the same operations. however, it is recommended to not stop the processor between the read and the write of aic_ivr of the interrupt service rou- tine to make sure the debugger does not modify the aic context. to summarize, in normal operating mode, the read of aic_ivr performs the following opera- tions within the aic: 1. calculates active interrupt (higher than current or spurious). 2. determines and returns the vector of the active interrupt. 3. memorizes the interrupt. 4. pushes the current priority level onto the internal stack. source 0 _ fiq input stage automatic clear input stage automatic clear source n aic_ipr aic_imr aic_ffsr aic_ipr aic_imr priority manager nfiq nirq read ivr if source n is the current interrupt and if fast forcing is disabled on source n. read fvr if fast forcing is disabled on sources 1 to 31. 271 6062b?atarm?15-nov-05 at91sam9261 5. acknowledges the interrupt. however, while the protect mode is activat ed, only operations 1 to 3 are performed when aic_ivr is read. operations 4 and 5 are only performed by the aic when aic_ivr is written. software that has been written and debugged using the protect mode runs correctly in normal mode without modification. however, in normal mode the aic_ivr write has no effect and can be removed to optimize the code. 26.7.6 spurious interrupt the advanced interrupt controller features prot ection against spurious interrupts. a spurious interrupt is defined as being the assertion of an interrupt source long enough for the aic to assert the nirq, but no longer present when aic_ivr is read. this is most prone to occur when: an external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time. an internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time. (as in the case for the watchdog.) an interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the interrupt source. the aic detects a spurious interrupt at the time the aic_ivr is read while no enabled interrupt source is pending. when this happens, the aic returns the value stored by the programmer in aic_spu (spurious vector register). the programmer must store the address of a spurious interrupt handler in aic_spu as part of the application, to enable an as fast as possible return to the normal execution flow. this handler writes in aic_eoicr and performs a return from interrupt. 26.7.7 general interrupt mask the aic features a general interrupt mask bit to prevent interrupts from reaching the proces- sor. both the nirq and the nfiq lines are driven to their inactive state if the bit gmsk in aic_dcr (debug control register) is set. however, this mask does not prevent waking up the processor if it has entered idle mo de. this function facilitates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt. it is strongly recommended to use this mask with caution. 272 6062b?atarm?15-nov-05 at91sam9261 26.8 advanced interrupt controll er (aic) user interface 26.8.1 base address the aic is mapped at the address 0xffff f000 . it has a total 4-kbyte addressing space. this permits the vectoring feature, as the pc-relative load/store instructions of the arm processor support only a 4-kbyte offset. 26.8.2 register mapping note: 1. the reset value of this register depends on the level of the external interrupt source. all other sources are cleared at reset, thus not pending. table 26-2. register mapping offset register name access reset value 0000 source mode register 0 aic_smr0 read/write 0x0 0x04 source mode register 1 aic_smr1 read/write 0x0 --- --- --- --- --- 0x7c source mode register 31 aic_smr31 read/write 0x0 0x80 source vector register 0 aic_svr0 read/write 0x0 0x84 source vector register 1 aic_svr1 read/write 0x0 --- --- --- --- --- 0xfc source vector register 31 aic_svr31 read/write 0x0 0x100 interrupt vector register aic_ivr read-only 0x0 0x104 fast interrupt vector register aic_fvr read-only 0x0 0x108 interrupt status register aic_isr read-only 0x0 0x10c interrupt pending register aic_ipr read-only 0x0 (1) 0x110 interrupt mask register aic_imr read-only 0x0 0x114 core interrupt status register aic_cisr read-only 0x0 0x118 reserved --- --- --- 0x11c reserved --- --- --- 0x120 interrupt enable command register aic_iecr write-only --- 0x124 interrupt disable command register aic_idcr write-only --- 0x128 interrupt clear command register aic_iccr write-only --- 0x12c interrupt set command register aic_iscr write-only --- 0x130 end of interrupt command register aic_eoicr write-only --- 0x134 spurious interrupt vector register aic_spu read/write 0x0 0x138 debug control register aic_dcr read/write 0x0 0x13c reserved --- --- --- 0x140 fast forcing enable register aic_ffer write-only --- 0x144 fast forcing disable r egister aic_ffdr write-only --- 0x148 fast forcing status register aic_ffsr read-only 0x0 273 6062b?atarm?15-nov-05 at91sam9261 26.8.3 aic source mode register register name: aic_smr0..aic_smr31 access type: read/write reset value: 0x0 prior: priority level programs the priority level for all sources except fiq source (source 0). the priority level can be between 0 (lowest) and 7 (highest). the priority level is not used for the fi q in the related smr register aic_smrx. srctype: interrupt source type the active level or edge is not programmable for the internal interrupt sources. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? srctype ? ? prior srctype internal interrupt sources external interrupt sources 0 0 high level sensitive low level sensitive 0 1 positive edge triggered negative edge triggered 1 0 high level sensitive high level sensitive 1 1 positive edge triggered positive edge triggered 274 6062b?atarm?15-nov-05 at91sam9261 26.8.4 aic source vector register register name: aic_svr0..aic_svr31 access type: read/write reset value: 0x0 vector: source vector the user may store in these registers the addresses of the corresponding handler for each interrupt source. 26.8.5 aic interrupt vector register register name: aic_ivr access type: read-only reset value: 0 irqv: interrupt vector register the interrupt vector register contains the vector programmed by the user in the source vector register corresponding to the current interrupt. the source vector register is indexed using the current interrupt number when the interrupt vector register is read. when there is no current interrupt, the interrupt vector register reads the value stored in aic_spu. 31 30 29 28 27 26 25 24 vector 23 22 21 20 19 18 17 16 vector 15 14 13 12 11 10 9 8 vector 76543210 vector 31 30 29 28 27 26 25 24 irqv 23 22 21 20 19 18 17 16 irqv 15 14 13 12 11 10 9 8 irqv 76543210 irqv 275 6062b?atarm?15-nov-05 at91sam9261 26.8.6 aic fiq vector register register name: aic_fvr access type: read-only reset value: 0 fiqv: fiq vector register the fiq vector register contains the vector programmed by the user in the source vector register 0. when there is no fast interrupt, the fast interrupt vector register reads the value stored in aic_spu. 26.8.7 aic interrupt status register register name: aic_isr access type: read-only reset value: 0 irqid: current interrupt identifier the interrupt status register returns the current interrupt source number. 31 30 29 28 27 26 25 24 fiqv 23 22 21 20 19 18 17 16 fiqv 15 14 13 12 11 10 9 8 fiqv 76543210 fiqv 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??? irqid 276 6062b?atarm?15-nov-05 at91sam9261 26.8.8 aic interrupt pending register register name: aic_ipr access type: read-only reset value: 0 fiq, sys, pid2-pid31: interrupt pending 0 = corresponding interrupt is not pending. 1 = corresponding interrupt is pending. 26.8.9 aic interrupt mask register register name: aic_imr access type: read-only reset value: 0 fiq, sys, pid2-pid31: interrupt mask 0 = corresponding interrupt is disabled. 1 = corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq 277 6062b?atarm?15-nov-05 at91sam9261 26.8.10 aic core interrupt status register register name: aic_cisr access type: read-only reset value: 0 nfiq: nfiq status 0 = nfiq line is deactivated. 1 = nfiq line is active. nirq: nirq status 0 = nirq line is deactivated. 1 = nirq line is active. 26.8.11 aic interrupt enable command register register name: aic_iecr access type: write-only fiq, sys, pid2-pid3: interrupt enable 0 = no effect. 1 = enables corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????nirqnifq 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq 278 6062b?atarm?15-nov-05 at91sam9261 26.8.12 aic interrupt disable command register register name: aic_idcr access type: write-only fiq, sys, pid2-pid31: interrupt disable 0 = no effect. 1 = disables corresponding interrupt. 26.8.13 aic interrupt clear command register register name: aic_iccr access type: write-only fiq, sys, pid2-pid31: interrupt clear 0 = no effect. 1 = clears corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq 279 6062b?atarm?15-nov-05 at91sam9261 26.8.14 aic interrupt set command register register name: aic_iscr access type: write-only fiq, sys, pid2-pid31: interrupt set 0 = no effect. 1 = sets corresponding interrupt. 26.8.15 aic end of interrupt command register register name: aic_eoicr access type: write-only the end of interrupt command register is used by the interrupt routine to indicate that the interrupt treatment is complete. any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????? 280 6062b?atarm?15-nov-05 at91sam9261 26.8.16 aic spurious interrupt vector register register name: aic_spu access type: read/write reset value: 0 siqv: spurious interrupt vector register the user may store the address of a spurious interrupt handler in this register. the written value is returned in aic_ivr in case of a spurious interrupt and in aic_fvr in case of a spurious fast interrupt. 26.8.17 aic debug control register register name: aic_debug access type: read/write reset value: 0 prot: protection mode 0 = the protection mode is disabled. 1 = the protection mode is enabled. gmsk: general mask 0 = the nirq and nfiq lines are normally controlled by the aic. 1 = the nirq and nfiq lines are tied to their inactive state. 31 30 29 28 27 26 25 24 siqv 23 22 21 20 19 18 17 16 siqv 15 14 13 12 11 10 9 8 siqv 76543210 siqv 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????gmskprot 281 6062b?atarm?15-nov-05 at91sam9261 26.8.18 aic fast forcing enable register register name: aic_ffer access type: write-only sys, pid2-pid31: fast forcing enable 0 = no effect. 1 = enables the fast forcing feature on the corresponding interrupt. 26.8.19 aic fast forcing disable register register name: aic_ffdr access type: write-only sys, pid2-pid31: fast forcing disable 0 = no effect. 1 = disables the fast forcing feature on the corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys ? 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys ? 282 6062b?atarm?15-nov-05 at91sam9261 26.8.20 aic fast forcing status register register name: aic_ffsr access type: read-only sys, pid2-pid31: fast forcing status 0 = the fast forcing feature is disabled on the corresponding interrupt. 1 = the fast forcing feature is enabled on the corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys ? 283 6062b?atarm?15-nov-05 at91sam9261 27. debug unit (dbgu) 27.1 description the debug unit provides a single entry point fr om the processor for access to all the debug capabilities of atmel?s arm-based systems. the debug unit features a two-pin uart that can be used for several debug and trace pur- poses and offers an ideal medium for in-situ programming solutions and debug monitor communications. moreover, the association with two peripheral data controller channels per- mits packet handling for these tasks with processor time reduced to a minimum. the debug unit also makes the debug comm unication channel (dcc) signals provided by the in-circuit emulator of the arm processor visi ble to the software. these signals indicate the status of the dcc read and write registers and generate an interrupt to the arm processor, making possible the handling of the dcc under interrupt control. chip identifier registers permit recognition of the device and its revision. these registers inform as to the sizes and types of the on-chip memories, as well as the set of embedded peripherals. finally, the debug unit features a force ntrst capability that enables the software to decide whether to prevent access to the system via the in-circuit emulator. this permits protection of the code, stored in rom. 284 6062b?atarm?15-nov-05 at91sam9261 27.2 block diagram figure 27-1. debug unit functional block diagram figure 27-2. debug unit application example peripheral dma controller baud rate generator dcc handler ice access handler transmit receive chip id interrupt control peripheral bridge parallel input/ output dtxd drxd power management controller arm processor force_ntrst commrx commtx mck ntrst ice_nreset dbgu_irq apb debug unit table 27-1. debug unit pin description pin name description type drxd debug receive data input dtxd debug transmit data output debug unit rs232 drivers programming tool trace console debug console boot program debug monitor trace manager 285 6062b?atarm?15-nov-05 at91sam9261 27.3 product dependencies 27.3.1 i/o lines depending on product integration, the debug unit pins may be multiplexed with pio lines. in this case, the programmer must first configure the corresponding pio controller to enable i/o lines operations of the debug unit. 27.3.2 power management depending on product integration, the debug unit clock may be controllable through the power management controller. in this case, the programmer must first configure the pmc to enable the debug unit clock. usually, the perip heral identifier used for this purpose is 1. 27.3.3 interrupt source depending on product integration, the debug unit interrupt line is connected to one of the interrupt sources of the advanced interrupt controller. interrupt handling requires program- ming of the aic before configuring the deb ug unit. usually, the debug unit interrupt line connects to the interrupt source 1 of the aic, which may be shared with the real-time clock, the system timer interrupt lines and other system peripheral interrupts, as shown in figure 27- 1 . this sharing requires the programmer to determine the source of the interrupt when the source 1 is triggered. 27.4 uart operations the debug unit operates as a uart, (asynchronous mode only) and supports only 8-bit char- acter handling (with parity). it has no clock pin. the debug unit's uart is made up of a receiver and a transmitter that operate independently, and a common baud rate generator. receiver timeout and transmitter time guard are not implemented. however, all the implemented features are compatible with those of a standard usart. 27.4.1 baud rate generator the baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter. the baud rate clock is the master clock divided by 16 times the value (cd) written in dbgu_brgr (baud rate generator register). if dbgu_brgr is set to 0, the baud rate clock is disabled and the debug unit's uart remains inactive. the maximum allowable baud rate is master clock divided by 16. the minimu m allowable baud rate is master clock divided by (16 x 65536). baud rate mck 16 cd ---------------------- = 286 6062b?atarm?15-nov-05 at91sam9261 figure 27-3. baud rate generator 27.4.2 receiver 27.4.2.1 receiver rese t, enable and disable after device reset, the debug unit receiv er is disabled and must be enabled before being used. the receiver can be enabled by writing th e control register dbgu_cr with the bit rxen at 1. at this command, the receiver starts looking for a start bit. the programmer can disable the receiver by writ ing dbgu_cr with the bit rxdis at 1. if the receiver is waiting for a start bit, it is immediately stopped. however, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. the programmer can also put the receiver in its reset state by writing dbgu_cr with the bit rstrx at 1. in doing so, the receiver immediately stops its current operations and is disabled, whatever its current state. if rstrx is applied when data is being processed, this data is lost. 27.4.2.2 start detection and data sampling the debug unit only supports asynchronous operations, and this affects only its receiver. the debug unit receiver detects the start of a received character by sampling the drxd signal until it detects a valid start bit. a low level (space) on drxd is in terpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. hence, a space that is longer than 7/16 of the bi t period is detected as a valid start bit. a space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. when a valid start bit has been detected, the receiver samples the drxd at the theoretical midpoint of each bit. it is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0 .5-bit period) after the start of the bit. the first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected. each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. mck 16-bit counter 0 baud rate clock cd cd out divide by 16 0 1 >1 receiver sampling clock 287 6062b?atarm?15-nov-05 at91sam9261 figure 27-4. start bit detection figure 27-5. character reception 27.4.2.3 receiver ready when a complete character is received, it is transferred to the dbgu_rhr and the rxrdy status bit in dbgu_sr (status register) is set. the bit rxrdy is automatically cleared when the receive holding register dbgu_rhr is read. figure 27-6. receiver ready 27.4.2.4 receiver overrun if dbgu_rhr has not been read by the software (or the peripheral data controller) since the last transfer, the rxrdy bit is still set and a new character is received, th e ovre status bit in dbgu_sr is set. ovre is cleared when the soft ware writes the control register dbgu_cr with the bit rststa (reset status) at 1. figure 27-7. receiver overrun 27.4.2.5 parity error each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field par in dbgu_mr. it then compares the result with the received sampling clock drxd true start detection d0 baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 drxd true start detection sampling parity bit stop bit example: 8-bit, parity enabled 1 stop 1 bit period 0.5 bit period d0 d1 d2 d3 d4 d5 d6 d7 p s s d0 d1 d2 d3 d4 d5 d6 d7 p drxd read dbgu_rhr rxrdy d0 d1 d2 d3 d4 d5 d6 d7 p s s d0 d1 d2 d3 d4 d5 d6 d7 p drxd rststa rxrdy ovre stop stop 288 6062b?atarm?15-nov-05 at91sam9261 parity bit. if different, the parity error bit pare in dbgu_sr is set at the same time the rxrdy is set. the parity bit is cleared when the control register dbgu_ cr is written with the bit rststa (reset status) at 1. if a new char acter is received before the reset status com- mand is written, the pare bit remains at 1. figure 27-8. parity error 27.4.2.6 receiver framing error when a start bit is detected, it generates a c haracter reception when all the data bits have been sampled. the stop bit is also sampled and when it is detected at 0, the frame (framing error) bit in dbgu_sr is set at the same ti me the rxrdy bit is set. the bit frame remains high until the control register dbgu_cr is written with the bit rststa at 1. figure 27-9. receiver framing error 27.4.3 transmitter 27.4.3.1 transmitter reset, enable and disable after device reset, the debug unit transmitter is disabled and it must be enabled before being used. the transmitter is enabled by writing the control register dbgu_cr with the bit txen at 1. from this command, the transmitter waits for a character to be written in the transmit hold- ing register dbgu_thr before actually starting the transmission. the programmer can disable the transmitter by writing dbgu_cr with the bit txdis at 1. if the transmitter is not operating, it is immediately stopped. however, if a character is being pro- cessed into the shift register and/or a character has been written in the transmit holding register, the characters are completed before the transmitter is actually stopped. the programmer can also put the transmitter in its reset state by writing the dbgu_cr with the bit rsttx at 1. this immediately stops the transmitter, whether or not it is processing characters. 27.4.3.2 transmit format the debug unit transmitter drives the pin dtxd at the baud rate clock speed. the line is driven depending on the format defined in the mode register and the data stored in the shift register. one start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown on the following stop d0 d1 d2 d3 d4 d5 d6 d7 p s drxd rststa rxrdy pare wrong parity bit d0 d1 d2 d3 d4 d5 d6 d7 p s drxd rststa rxrdy frame stop bit detected at 0 stop 289 6062b?atarm?15-nov-05 at91sam9261 figure. the field pare in the mode register db gu_mr defines whether or not a parity bit is shifted out. when a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. figure 27-10. character transmission 27.4.3.3 transmitter control when the transmitter is enabled, the bit txrdy (transmitter ready) is set in the status regis- ter dbgu_sr. the transmission starts when the programmer writes in the transmit holding register dbgu_thr, and after the written character is transferred from dbgu_thr to the shift register. the bit txrdy re mains high until a second character is written in dbgu_thr. as soon as the first character is completed, th e last character written in dbgu_thr is trans- ferred into the shift register and txrdy rises again, showing that the holding register is empty. when both the shift register and the dbgu_thr are empty, i.e., all the characters written in dbgu_thr have been processed, the bit txempty rises after the last stop bit has been completed. figure 27-11. transmitter control 27.4.4 peripheral data controller both the receiver and the transmitter of the debug unit's uart are generally connected to a peripheral data controller (pdc) channel. the peripheral data controller channels are programmed via registers that are mapped within the debug unit user interface from the offset 0x100. the status bits are reported in the debug unit status register dbgu_sr and can generate an interrupt. d0 d1 d2 d3 d4 d5 d6 d7 dtxd start bit parity bit stop bit example: parity enabled baud rate clock dbgu_thr shift register dtxd txrdy txempty data 0 data 1 data 0 data 0 data 1 data 1 s s p p write data 0 in dbgu_thr write data 1 in dbgu_thr stop stop 290 6062b?atarm?15-nov-05 at91sam9261 the rxrdy bit triggers the pdc channel data transfer of the receiver. this results in a read of the data in dbgu_rhr. the txrdy bit trigger s the pdc channel data transfer of the trans- mitter. this results in a write of a data in dbgu_thr. 27.4.5 test modes the debug unit supports three tests modes. these modes of operation are programmed by using the field chmode (channel mode) in the mode register dbgu_mr. the automatic echo mode allows bit-by-bit retransmission. when a bit is received on the drxd line, it is sent to the dtxd line. the transmitter operates normally, but has no effect on the dtxd line. the local loopback mode allows the transmitt ed characters to be received. dtxd and drxd pins are not used and the output of the transmitter is internally connected to the input of the receiver. the drxd pin level has no effect and th e dtxd line is held high , as in idle state. the remote loopback mode directly connects th e drxd pin to the dtxd line. the transmit- ter and the receiver are disabled and have no effect. this mode allows a bit-by-bit retransmission. figure 27-12. test modes 27.4.6 debug communication channel support the debug unit handles the signals commrx and commtx that come from the debug communication channel of the arm processor and are driven by the in-circuit emulator. receiver transmitter disabled rxd txd receiver transmitter disabled rxd txd v dd disabled receiver transmitter disabled rxd txd disabled automatic echo local loopback remote loopback v dd 291 6062b?atarm?15-nov-05 at91sam9261 the debug communication channel contains two registers that are accessible through the ice breaker on the jtag side and through the coprocessor 0 on the arm processor side. as a reminder, the following instructions are used to read and write the debug communication channel: mrc p14, 0, rd, c1, c0, 0 returns the debug communication data read register into rd mcr p14, 0, rd, c1, c0, 0 writes the value in rd to the debug communication data write register. the bits commrx and commtx, which indicate, respectively, that the read register has been written by the debugger but not yet read by the processor, and that the write register has been written by the processor and not yet read by the debugger, are wired on the two highest bits of the status register dbgu_sr. these bits can generate an interrupt. this feature per- mits handling under interrupt a debug link between a debug monitor running on the target system and a debugger. 27.4.7 chip identifier the debug unit features two chip identifier registers, dbgu_cidr (chip id register) and dbgu_exid (extension id). both registers contain a hard-wired value that is read-only. the first register contains the following fields: ext - shows the use of the extension identifier register nvptyp and nvpsiz - identifies the type of embedded non-volatile memory and its size arch - identifies the set of embedded peripheral sramsiz - indicates the size of the embedded sram eproc - indicates the embedded arm processor version - gives the revision of the silicon the second register is device-dependent and reads 0 if the bit ext is 0. 27.4.8 ice access prevention the debug unit allows blockage of access to the system through the arm processor's ice interface. this feature is implemented via the register force ntrst (dbgu_fnr), that allows assertion of the ntrst signal of the ice interface. writing the bit fntrst (force ntrst) to 1 in this register prevents an y activity on the tap controller. on standard devices, the bit fntrst resets to 0 and thus does not prevent ice access. this feature is especially useful on custom rom devices for customers who do not want their on-chip code to be visible. 292 6062b?atarm?15-nov-05 at91sam9261 27.5 debug unit (dbgu) user interface table 27-2. debug unit memory map offset register name access reset value 0x0000 control register dbgu_cr write-only ? 0x0004 mode register dbgu_mr read/write 0x0 0x0008 interrupt enable register dbgu_ier write-only ? 0x000c interrupt disable register dbgu_idr write-only ? 0x0010 interrupt mask register dbgu_imr read-only 0x0 0x0014 status register dbgu_sr read-only ? 0x0018 receive holding register dbgu_rhr read-only 0x0 0x001c transmit holding register dbgu_thr write-only ? 0x0020 baud rate generator register dbgu_brgr read/write 0x0 0x0024 - 0x003c reserved ? ? ? 0x0040 chip id register dbgu_cidr read-only ? 0x0044 chip id extension register dbgu_exid read-only ? 0x0048 force ntrst register dbgu_fnr read/write 0x0 0x004c - 0x00fc reserved ? ? ? 0x0100 - 0x0124 pdc area ? ? ? 293 6062b?atarm?15-nov-05 at91sam9261 27.5.1 debug unit control register name: dbgu_cr access type: write-only rstrx: reset receiver 0 = no effect. 1 = the receiver logic is reset and disabled. if a ch aracter is being received, the reception is aborted. rsttx: reset transmitter 0 = no effect. 1 = the transmitter logic is reset and disabled. if a character is being transmitted, the transmission is aborted. rxen: receiver enable 0 = no effect. 1 = the receiver is enabled if rxdis is 0. rxdis: receiver disable 0 = no effect. 1 = the receiver is disabled. if a character is being processe d and rstrx is not set, the character is completed before the receiver is stopped. txen: transmitter enable 0 = no effect. 1 = the transmitter is ena bled if txdis is 0. txdis: transmitter disable 0 = no effect. 1 = the transmitter is disabled. if a character is being processed and a charac ter has been written the dbgu_thr and rsttx is not set, both characters are completed before the transmitter is stopped. rststa: reset status bits 0 = no effect. 1 = resets the status bits pare, frame and ovre in the dbgu_sr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????? rststa 76543210 txdis txen rxdis rxen rsttx rstrx ?? 294 6062b?atarm?15-nov-05 at91sam9261 27.5.2 debug unit mode register name: dbgu_mr access type: read/write par: parity type parity type chmode: channel mode 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 chmode ?? pa r ? 76543210 ???????? pa r 0 0 0 even parity 001odd parity 0 1 0 space: parity forced to 0 0 1 1 mark: parity forced to 1 1 x x no parity chmode mode description 00normal mode 0 1 automatic echo 1 0 local loopback 1 1 remote loopback 295 6062b?atarm?15-nov-05 at91sam9261 27.5.3 debug unit interrupt enable register name: dbgu_ier access type: write-only rxrdy: enable rxrdy interrupt txrdy: enable txrdy interrupt endrx: enable end of receive transfer interrupt endtx: enable end of transmit interrupt ovre: enable overrun error interrupt frame: enable framing error interrupt pare: enable parity error interrupt txempty: enable txempty interrupt txbufe: enable buffer empty interrupt rxbuff: enable buffer full interrupt commtx: enable commtx (from arm) interrupt commrx: enable commrx (from arm) interrupt 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 commrx commtx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy 296 6062b?atarm?15-nov-05 at91sam9261 27.5.4 debug unit interrupt disable register name: dbgu_idr access type: write-only rxrdy: disable rxrdy interrupt txrdy: disable txrdy interrupt endrx: disable end of receive transfer interrupt endtx: disable end of transmit interrupt ovre: disable overrun error interrupt frame: disable framing error interrupt pare: disable parity error interrupt txempty: disable txempty interrupt txbufe: disable buffer empty interrupt rxbuff: disable buffer full interrupt commtx: disable commtx (from arm) interrupt commrx: disable commrx (from arm) interrupt 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 commrx commtx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy 297 6062b?atarm?15-nov-05 at91sam9261 27.5.5 debug unit interrupt mask register name: dbgu_imr access type: read-only rxrdy: mask rxrdy interrupt txrdy: disable txrdy interrupt endrx: mask end of receive transfer interrupt endtx: mask end of transmit interrupt ovre: mask overrun error interrupt frame: mask framing error interrupt pare: mask parity error interrupt txempty: mask txempty interrupt txbufe: mask txbufe interrupt rxbuff: mask rxbuff interrupt commtx: mask commtx interrupt commrx: mask commrx interrupt 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 commrx commtx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy 298 6062b?atarm?15-nov-05 at91sam9261 27.5.6 debug unit status register name: dbgu_sr access type: read-only rxrdy: receiver ready 0 = no character has been received since the last re ad of the dbgu_rhr or the receiver is disabled. 1 = at least one complete character has been received, transferred to dbgu_rhr and not yet read. txrdy: transmitter ready 0 = a character has been written to dbgu_thr and not yet transferred to the shift register, or the transmitter is disabled. 1 = there is no character written to dbgu_thr not yet transferred to the shift register. endrx: end of receiver transfer 0 = the end of transfer signal from the receiver peripheral data controller channel is inactive. 1 = the end of transfer signal from the receiver peripheral data controller channel is active. endtx: end of transmitter transfer 0 = the end of transfer signal from the transmitter peripheral data controller channel is inactive. 1 = the end of transfer signal from the transmitter peripheral data controller channel is active. ovre: overrun error 0 = no overrun error has occurred since the last rststa. 1 = at least one overrun error has occurred since the last rststa. frame: framing error 0 = no framing error has occurred since the last rststa. 1 = at least one framing error has occurred since the last rststa. pare: parity error 0 = no parity error has occurred since the last rststa. 1 = at least one parity error has occurred since the last rststa. txempty: transmitter empty 0 = there are characters in dbgu_thr, or characters being processed by the transmitter, or the transmitter is disabled. 1 = there are no characters in dbgu_thr and there ar e no characters being processed by the transmitter. txbufe: transmission buffer empty 0 = the buffer empty signal from the transmitter pdc channel is inactive. 1 = the buffer empty signal from the transmitter pdc channel is active. rxbuff: receive buffer full 0 = the buffer full signal from the receiver pdc channel is inactive. 1 = the buffer full signal from the receiver pdc channel is active. 31 30 29 28 27 26 25 24 commrx commtx ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? rxbuff txbufe ? txempty ? 76543210 pare frame ovre endtx endrx ? txrdy rxrdy 299 6062b?atarm?15-nov-05 at91sam9261 commtx: debug communication channel write status 0 = commtx from the arm processor is inactive. 1 = commtx from the arm processor is active. commrx: debug communication channel read status 0 = commrx from the arm processor is inactive. 1 = commrx from the arm processor is active. 300 6062b?atarm?15-nov-05 at91sam9261 27.5.7 debug unit receiver holding register name: dbgu_rhr access type: read-only rxchr: received character last received character if rxrdy is set. 27.5.8 debug unit transmit holding register name: dbgu_thr access type: write-only txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rxchr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 txchr 301 6062b?atarm?15-nov-05 at91sam9261 27.5.9 debug unit baud ra te generator register name: dbgu_brgr access type: read/write cd: clock divisor 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cd 76543210 cd cd baud rate clock 0 disabled 1mck 2 to 65535 mck / (cd x 16) 302 6062b?atarm?15-nov-05 at91sam9261 27.5.10 debug unit chip id register name: dbgu_cidr access type: read-only version: version of the device eproc: embedded processor nvpsiz: nonvolatile program memory size 31 30 29 28 27 26 25 24 ext nvptyp arch 23 22 21 20 19 18 17 16 arch sramsiz 15 14 13 12 11 10 9 8 nvpsiz2 nvpsiz 76543210 eproc version eproc processor 0 0 1 arm946es 0 1 0 arm7tdmi 100arm920t 1 0 1 arm926ej-s nvpsiz size 0000none 00018k bytes 001016k bytes 001132k bytes 0100reserved 010164k bytes 0110reserved 0111128k bytes 1000reserved 1001256k bytes 1010512k bytes 1011reserved 11001024k bytes 1101reserved 11102048k bytes 1111reserved 303 6062b?atarm?15-nov-05 at91sam9261 nvpsiz2 second nonvolatile program memory size sramsiz: internal sram size nvpsiz2 size 0000none 00018k bytes 001016k bytes 001132k bytes 0100reserved 010164k bytes 0110reserved 0111128k bytes 1000reserved 1001256k bytes 1010512k bytes 1011reserved 11001024k bytes 1101reserved 11102048k bytes 1111reserved sramsiz size 0000reserved 00011k bytes 00102k bytes 0011reserved 0100112k bytes 01014k bytes 011080k bytes 0111160k bytes 10008k bytes 100116k bytes 101032k bytes 101164k bytes 1100128k bytes 1101256k bytes 111096k bytes 1111512k bytes 304 6062b?atarm?15-nov-05 at91sam9261 arch: architecture identifier nvptyp: nonvolatile program memory type ext: extension flag 0 = chip id has a single register definition without extension 1 = an extended chip id exists. arch architecture hex bin 0xf0 1111 0001 at75cxx series 0x40 0100 0000 at91x40 series 0x63 0110 0011 at91x63 series 0x55 0101 0101 at91x55 series 0x42 0100 0010 at91x42 series 0x92 1001 0010 at91x92 series 0x34 0011 0100 at91x34 series 0x60 0101 0000 at91sam7axx series 0x70 0111 0000 at91sam7sxx series 0x71 0111 0001 at91sam7xcxx series 0x72 0111 0010 at91sam7sexx series 0x73 0111 0011 at91sam7lxx series 0x75 0111 0101 at91sam7xxx series 0x19 0001 1001 at91sam9xx series nvptyp memory 000rom 0 0 1 romless or on-chip flash 1 0 0 sram emulating rom 0 1 0 embedded flash memory 011 rom and embedded flash memory nvpsiz is rom size nvpsiz2 is flash size 305 6062b?atarm?15-nov-05 at91sam9261 27.5.11 debug unit chip id extension register name: dbgu_exid access type: read-only exid: chip id extension reads 0 if the bit ext in dbgu_cidr is 0. 27.5.12 debug unit force ntrst register name: dbgu_fnr access t ype: read/write fntrst: force ntrst 0 = ntrst of the arm processor?s tap contro ller is driven by the ice_nreset signal. 1 = ntrst of the arm processor?s tap controller is held low. 31 30 29 28 27 26 25 24 exid 23 22 21 20 19 18 17 16 exid 15 14 13 12 11 10 9 8 exid 76543210 exid 31 30 29 28 27 26 25 24 ??????? ? 23 22 21 20 19 18 17 16 ??????? ? 15 14 13 12 11 10 9 8 ??????? ? 7654321 0 ??????? fntrst 306 6062b?atarm?15-nov-05 at91sam9261 307 6062b?atarm?15-nov-05 at91sam9261 28. parallel input/outp ut (pio) controller 28.1 description the parallel input/output (pio) controller manages up to 32 fully programmable input/output lines. each i/o line may be dedicated as a general-purpose i/o or be assigned to a function of an embedded peripheral. this assures effective optimization of the pins of a product. each i/o line is associated with a bit number in all of the 32-bit registers of the 32-bit wide user interface. each i/o line of the pio controller features: an input change interrupt enabling level change detection on any i/o line. a glitch filter providing rejection of pulses lower than one-half of clock cycle. multi-drive capability similar to an open drain i/o line. control of the the pull-up of the i/o line. input visibility and output control. the pio controller also features a synchronous output providing up to 32 bits of data output in a single write operation. 308 6062b?atarm?15-nov-05 at91sam9261 28.2 block diagram figure 28-1. block diagram figure 28-2. application block diagram embedded peripheral embedded peripheral pio interrupt pio controller up to 32 pins pmc up to 32 peripheral ios up to 32 peripheral ios pio clock apb aic data, enable pin 31 pin 1 pin 0 data, enable on-chip peripherals pio controller on-chip peripheral drivers control & command driver keyboard driver keyboard driver general purpose i/os external devices 309 6062b?atarm?15-nov-05 at91sam9261 28.3 product dependencies 28.3.1 pin multiplexing each pin is configurable, according to product definition as either a general-purpose i/o line only, or as an i/o line multiplexed with one or two peripheral i/os. as the multiplexing is hard- ware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the pio controllers required by their application. when an i/o line is general-purpose only, i.e., not multiplexed with any peripheral i/o, programming of the pio controller regarding the assignment to a peripheral has no effect and only the pio controller can control how the pi n is driven by the product. 28.3.2 external interrupt lines the interrupt signals fiq and irq0 to irqn are most generally multiplexed through the pio controllers. however, it is not necessary to assign the i/o line to the interrupt function as the pio controller has no effect on inputs and the interrupt lines (fiq or irqs) are used only as inputs. 28.3.3 power management the power management co ntroller controls the p io controller clock in order to save power. writing any of the registers of the user interface does not require the pio controller clock to be enabled. this means that the configuration of the i/o lines does not require the pio controller clock to be enabled. however, when the clock is disabled, not all of the features of the pio controller are available. note that the input change interrupt and the read of the pin level require the clock to be validated. after a hardware reset, the pio clock is disabled by default. the user must configure the power management controller before any access to the input line information. 28.3.4 interrupt generation for interrupt handling, the pio controllers are considered as user peripherals. this means that the pio controller interrupt lines are connected among the interrupt sources 2 to 31. refer to the pio controller peripheral identifier in the product description to identify the inter- rupt sources dedicated to the pio controllers. the pio controller interrupt can be generated only if the pio controller clock is enabled. 310 6062b?atarm?15-nov-05 at91sam9261 28.4 functional description the pio controller features up to 32 fully-programmable i/o lines. most of the control logic associated to each i/o is represented in figure 28-3 . in this description each signal shown represents but one of up to 32 possible indexes. figure 28-3. i/o line control logic 1 0 1 0 1 0 glitch filter peripheral b input peripheral a input 1 0 pio_ifdr[0] pio_ifsr[0] pio_ifer[0] edge detector pio_pdsr[0] pio_isr[0] pio_idr[0] pio_imr[0] pio_ier[0] pio interrupt (up to 32 possible inputs) pio_isr[31] pio_idr[31] pio_imr[31] pio_ier[31] pad 1 0 pio_pudr[0] pio_pusr[0] pio_puer[0] pio_mddr[0] pio_mdsr[0] pio_mder[0] pio_codr[0] pio_odsr[0] pio_sodr[0] pio_pdr[0] pio_psr[0] pio_per[0] 1 0 1 0 pio_bsr[0] pio_absr[0] pio_asr[0] peripheral b output enable peripheral a output enable peripheral b output peripheral a output pio_odr[0] pio_osr[0] pio_oer[0] 311 6062b?atarm?15-nov-05 at91sam9261 28.4.1 pull-up resistor control each i/o line is designed with an embedded pull- up resistor. the pull-up resistor can be enabled or disabled by writing respectively pio_puer (pull-up enable register) and pio_pudr (pull-up disable resistor). writing in these registers results in setting or clearing the corresponding bit in pio_pusr (pull-up status register). reading a 1 in pio_pusr means the pull-up is disabled and reading a 0 means the pull-up is enabled. control of the pull-up resistor is possible regardless of the configuration of the i/o line. after reset, all of the pull-ups are enabled, i.e., pio_pusr resets at the value 0x0. 28.4.2 i/o line or peripheral function selection when a pin is multiplexed with one or two perip heral functions, the selection is controlled with the registers pio_per (pio enable register) and pio_pdr (pio disable register). the reg- ister pio_psr (pio status register) is the resu lt of the set and clear registers and indicates whether the pin is controlled by the correspondi ng peripheral or by the pio controller. a value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the pio_absr (ab select status register). a value of 1 indicate s the pin is controlled by the pio controller. if a pin is used as a general purpose i/o line (n ot multiplexed with an on-chip peripheral), pio_per and pio_pdr have no effect and pio_psr returns 1 for the corresponding bit. after reset, most generally, the i/o lines are controlled by the pio controller, i.e., pio_psr resets at 1. however, in some events, it is important that pio lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low fo r booting out of an external memory). thus, the reset value of pio_psr is defined at the product level, depending on the multiplexing of the device. 28.4.3 peripheral a or b selection the pio controller provides multiplexing of up to two peripheral functions on a single pin. the selection is performed by writing pio_asr (a select register) and pio_bsr (select b regis- ter). pio_absr (ab select status register) indicates which peripheral line is currently selected. for each pin, the corresponding bit at level 0 means peripheral a is selected whereas the corresponding bit at level 1 indicates that peripheral b is selected. note that multiplexing of peripheral lines a and b only affects the output line. the peripheral input lines are always connected to the pin input. after reset, pio_absr is 0, thus indicating th at all the pio lines are configured on peripheral a. however, peripheral a generally does not drive the pin as the pio controller resets in i/o line mode. writing in pio_asr and pio_bs r manages pio_absr re gardless of the c onfiguration of the pin. however, assignment of a pin to a peripher al function requires a write in the correspond- ing peripheral selection register (pio_asr or pio_bsr) in addition to a write in pio_pdr. 28.4.4 output control when the i/0 line is assigned to a peripheral function, i.e., the corresponding bit in pio_psr is at 0, the drive of the i/o line is controlled by the peripheral. peripheral a or b, depending on the value in pio_absr, de termines whethe r the pin is driven or not. 312 6062b?atarm?15-nov-05 at91sam9261 when the i/o line is controlled by the pio contro ller, the pin can be configured to be driven. this is done by writing pio_oer (output e nable register) and pio_odr (output disable register). the results of these write operations are detected in pio_osr (output status reg- ister). when a bit in this register is at 0, the corresponding i/o line is used as an input only. when the bit is at 1, the corresponding i/o line is driven by the pio controller. the level driven on an i/o line can be determined by writing in pio_sodr (set output data register) and pio_codr (clear output data register). these write operations respectively set and clear pio_odsr (output data status register), which represents the data driven on the i/o lines. writing in pio_oer and pio_od r manages pio_osr whether the pin is con- figured to be controlled by the pio controller or assigned to a peripheral function. this enables configuration of the i/o line prior to setting it to be managed by the pio controller. similarly, writing in pio_sodr and pio_codr effects pio_odsr. this is important as it defines the first level driven on the i/o line. 28.4.5 synchronous data output controlling all parallel busses using several pios requires two successive write operations in the pio_sodr and pio_codr registers. this may lead to unexpected transient values. the pio controller offers a direct control of pio outputs by single write access to pio_odsr (out- put data status register). only bits unmasked by pio_oswsr (output write status register) are written. the mask bits in the pio_owsr are set by writing to pio_ower (out- put write enable register) and cleared by wr iting to pio_owdr (output write disable register). after reset, the synchronous data output is disa bled on all the i/o lines as pio_owsr resets at 0x0. 28.4.6 multi drive control (open drain) each i/o can be independently programmed in op en drain by using the multi drive feature. this feature permits several drivers to be connected on the i/o line which is driven low only by each device. an external pull-up resistor (or en abling of the internal one) is generally required to guarantee a high level on the line. the multi drive feature is controlled by pio_mder (multi-driver enable register) and pio_mddr (multi-driver disable register). th e multi drive can be selected whether the i/o line is controlled by the pio c ontroller or assigned to a peripheral function. pio_mdsr (multi- driver status register) indicates the pins th at are configured to support external drivers. after reset, the multi drive feature is disabled on all pins, i.e. pio_mdsr resets at value 0x0. 28.4.7 output line timings figure 28-4 shows how the outputs are driven either by writing pio_sodr or pio_codr, or by directly writing pio_odsr. this last case is valid only if the corresponding bit in pio_owsr is set. figure 28-4 also shows when the feedback in pio_pdsr is available. 313 6062b?atarm?15-nov-05 at91sam9261 figure 28-4. output line timings 28.4.8 inputs the level on each i/o line can be read through pio_pdsr (pin data status register). this register indicates the level of the i/o lines regardless of their configuration, whether uniquely as an input or driven by the pio controller or driven by a peripheral. reading the i/o line levels requires the clock of the pio controller to be enabled, otherwise pio_pdsr reads the levels present on the i/o line at the time the clock was disabled. 28.4.9 input glitch filtering optional input glitch filters are independently programmable on each i/o line. when the glitch filter is enabled, a glitch with a duration of less than 1/2 master clock (mck) cycle is automat- ically rejected, while a pulse with a duration of 1 master clock cycle or more is accepted. for pulse durations between 1/2 master clock cycl e and 1 master clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. thus for a pulse to be visible it must exceed 1 master clo ck cycle, whereas for a glitch to be reliably fil- tered out, its duration must not exceed 1/2 master clock cycle. the filter introduces one master clock cycle latency if the pin level c hange occurs before a rising edge. however, this latency does not appear if the pin level change occurs before a falling edge. this is illustrated in figure 28-5 . the glitch filters are controlled by the register set; pio_ifer (input filter enable register), pio_ifdr (input filter disable register) and pio_ifsr (input filter status register). writing pio_ifer and pio_ifdr respectively sets and cl ears bits in pio_ifsr. this last register enables the glitch filt er on the i/o lines. when the glitch filter is enabled, it does not modify the behavior of the inputs on the peripher- als. it acts only on the value read in pio_pdsr and on the input change interrupt detection. the glitch filters require that the pio controller clock is enabled. 2 cycles apb access 2 cycles apb access mck write pio_sodr write pio_odsr at 1 pio_odsr pio_pdsr write pio_codr write pio_odsr at 0 314 6062b?atarm?15-nov-05 at91sam9261 figure 28-5. input glitch filter timing 28.4.10 input change interrupt the pio controller can be programmed to generate an interrupt when it detects an input change on an i/o line. the input change interrupt is controlled by writing pio_ier (interrupt enable register) and pio_idr (interrupt disable register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in pio_imr (interrupt mask register). as input change dete ction is possible only by comparing two suc- cessive samplings of the input of the i/o line, the pio controller clock must be enabled. the input change interrupt is available, regardless of the configuration of the i/o line, i.e. config- ured as an input only, controlled by the pio controller or assigned to a peripheral function. when an input change is detected on an i/o line, the corresponding bit in pio_isr (interrupt status register) is set. if the corresponding bit in pio_imr is set, the pio controller interrupt line is asserted. the interrupt signals of the thirty-two channels are ored-wired together to generate a single interrupt signal to the advanced interrupt controller. when the software reads pio_isr, all the interrupts are automatically cleared. this signifies that all the interrupts that are pending when pio_isr is read must be handled. figure 28-6. input change interrupt timings mck pin level pio_pdsr if pio_ifsr = 0 pio_pdsr if pio_ifsr = 1 1 cycle 1 cycle 1 cycle up to 1.5 cycles 2 cycles up to 2.5 cycles up to 2 cycles 1 cycle 1 cycle mck pin level read pio_isr apb access pio_isr apb access 315 6062b?atarm?15-nov-05 at91sam9261 28.5 i/o lines programming example the programing example as shown in table 28-1 below is used to define the following configuration. 4-bit output port on i/o lines 0 to 3, (should be written in a single write operation), open- drain, with pull-up resistor four output signals on i/o lines 4 to 7 (to drive leds for example), driven high and low, no pull-up resistor four input signals on i/o lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts four input signals on i/o line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter i/o lines 16 to 19 assigned to peripheral a functions with pull-up resistor i/o lines 20 to 23 assigned to peripheral b functions, no pull-up resistor i/o line 24 to 27 assigned to peripheral a with input change interrupt and pull-up resistor table 28-1. programming example register value to be written pio_per 0x0000 ffff pio_pdr 0x0fff 0000 pio_oer 0x0000 00ff pio_odr 0x0fff ff00 pio_ifer 0x0000 0f00 pio_ifdr 0x0fff f0ff pio_sodr 0x0000 0000 pio_codr 0x0fff ffff pio_ier 0x0f00 0f00 pio_idr 0x00ff f0ff pio_mder 0x0000 000f pio_mddr 0x0fff fff0 pio_pudr 0x00f0 00f0 pio_puer 0x0f0f ff0f pio_asr 0x0f0f 0000 pio_bsr 0x00f0 0000 pio_ower 0x0000 000f pio_owdr 0x0fff fff0 316 6062b?atarm?15-nov-05 at91sam9261 28.6 parallel input/ouput (pio) controller user interface each i/o line controlled by the pio controller is associated with a bit in each of the pio con- troller user interface registers. each register is 32 bits wide. if a parallel i/o line is not defined, writing to the corresponding bits has no effect. undefined bits read zero. if the i/o line is not multiplexed with any peripheral, the i/o line is controlled by the pio controller and pio_psr returns 1 systematically. table 28-2. register mapping offset register name access reset value 0x0000 pio enable register pio_per write-only ? 0x0004 pio disable register pio_pdr write-only ? 0x0008 pio status register (1) pio_psr read-only 0x0000 0000 0x000c reserved 0x0010 output enable register pio_oer write-only ? 0x0014 output disable register pio_odr write-only ? 0x0018 output status regist er pio_osr read-only 0x0000 0000 0x001c reserved 0x0020 glitch input filter enab le register pio_ifer write-only ? 0x0024 glitch input filter disab le register pio_ifdr write-only ? 0x0028 glitch input filter status register pio_ifsr read-only 0x0000 0000 0x002c reserved 0x0030 set output data register pio_sodr write-only ? 0x0034 clear output data register pio_codr write-only ? 0x0038 output data status register (2) pio_odsr read-only 0x0000 0000 0x003c pin data status register (3) pio_pdsr read-only 0x0040 interrupt enable register pio_ier write-only ? 0x0044 interrupt disable register pio_idr write-only ? 0x0048 interrupt mask register pio_imr read-only 0x00000000 0x004c interrupt status register (4) pio_isr read-only 0x00000000 0x0050 multi-driver enable register pio_mder write-only ? 0x0054 multi-driver disable register pio_mddr write-only ? 0x0058 multi-driver status re gister pio_mdsr read-only 0x00000000 0x005c reserved 0x0060 pull-up disable register pio_pudr write-only ? 0x0064 pull-up enable register pio_puer write-only ? 0x0068 pad pull-up status regi ster pio_pusr read-only 0x00000000 0x006c reserved 317 6062b?atarm?15-nov-05 at91sam9261 notes: 1. reset value of pio_psr depends on the product implementation. 2. pio_odsr is read-only or read/write depending on pio_owsr i/o lines. 3. reset value of pio_pdsr depends on the level of the i/o lines. 4. pio_isr is reset at 0x0. however, the first read of the r egister may read a different value as input changes may have occurred. 5. only this set of registers clears the status by writing 1 in the first register and sets the st atus by writing 1 in the secon d register. 6. the reset value changes with each version of the ip block hardware. 0x0070 peripheral a select register (5) pio_asr write-only ? 0x0074 peripheral b select register (5) pio_bsr write-only ? 0x0078 ab status register (5) pio_absr read-only 0x00000000 0x007c to 0x009c reserved 0x00a0 output write enab le pio_ower write-only ? 0x00a4 output write disab le pio_owdr write-only ? 0x00a8 output write status re gister pio_owsr read-only 0x00000000 0x00ac reserved 0x00fc version register pio_version read-only ? (6) table 28-2. register mapping (continued) offset register name access reset value 318 6062b?atarm?15-nov-05 at91sam9261 28.6.1 pio controller pio enable register name: pio_per access type: write-only p0-p31: pio enable 0 = no effect. 1 = enables the pio to control the corresponding pin (disables peripheral control of the pin). 28.6.2 pio controller pio disable register name: pio_pdr access type: write-only p0-p31: pio disable 0 = no effect. 1 = disables the pio from controllin g the corresponding pin (enables peripheral contro l of the pin). 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 319 6062b?atarm?15-nov-05 at91sam9261 28.6.3 pio controller pio status register name: pio_psr access type: read-only p0-p31: pio status 0 = pio is inactive on the corresponding i/o line (peripheral is active). 1 = pio is active on the corresponding i/o line (peripheral is inactive). 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 320 6062b?atarm?15-nov-05 at91sam9261 28.6.4 pio controller output enable register name: pio_oer access type: write-only p0-p31: output enable 0 = no effect. 1 = enables the output on the i/o line. 28.6.5 pio controller output disable register name: pio_odr access type: write-only p0-p31: output disable 0 = no effect. 1 = disables the output on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 321 6062b?atarm?15-nov-05 at91sam9261 28.6.6 pio controller output status register name: pio_osr access type: read-only p0-p31: output status 0 = the i/o line is a pure input. 1 = the i/o line is enabled in output. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 322 6062b?atarm?15-nov-05 at91sam9261 28.6.7 pio controller input filter enable register name: pio_ifer access type: write-only p0-p31: input filter enable 0 = no effect. 1 = enables the input glitch filter on the i/o line. 28.6.8 pio controller input filter disable register name: pio_ifdr access type: write-only p0-p31: input filter disable 0 = no effect. 1 = disables the input glitch filter on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 323 6062b?atarm?15-nov-05 at91sam9261 28.6.9 pio controller input filter status register name: pio_ifsr access type: read-only p0-p31: input filer status 0 = the input glitch filter is disabled on the i/o line. 1 = the input glitch filter is enabled on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 324 6062b?atarm?15-nov-05 at91sam9261 28.6.10 pio controller set output data register name: pio_sodr access type: write-only p0-p31: set output data 0 = no effect. 1 = sets the data to be driven on the i/o line. 28.6.11 pio controller clear output data register name: pio_codr access type: write-only p0-p31: set output data 0 = no effect. 1 = clears the data to be driven on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 325 6062b?atarm?15-nov-05 at91sam9261 28.6.12 pio controller output data status register name: pio_odsr access type: read-only or read/write p0-p31: output data status 0 = the data to be driven on the i/o line is 0. 1 = the data to be driven on the i/o line is 1. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 326 6062b?atarm?15-nov-05 at91sam9261 28.6.13 pio controller pin data status register name: pio_pdsr access type: read-only p0-p31: output data status 0 = the i/o line is at level 0. 1 = the i/o line is at level 1. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 327 6062b?atarm?15-nov-05 at91sam9261 28.6.14 pio controller interrupt enable register name: pio_ier access type: write-only p0-p31: input change interrupt enable 0 = no effect. 1 = enables the input change interrupt on the i/o line. 28.6.15 pio controller interrupt disable register name: pio_idr access type: write-only p0-p31: input change interrupt disable 0 = no effect. 1 = disables the input change interrupt on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 328 6062b?atarm?15-nov-05 at91sam9261 28.6.16 pio controller interrupt mask register name: pio_imr access type: read-only p0-p31: input change interrupt mask 0 = input change interrupt is disabled on the i/o line. 1 = input change interrupt is enabled on the i/o line. 28.6.17 pio controller interrupt status register name: pio_isr access type: read-only p0-p31: input change interrupt status 0 = no input change has been detected on the i/o line since pio_isr was last read or since reset. 1 = at least one input change has been detected on the i/o line since pio_isr was last read or since reset. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 329 6062b?atarm?15-nov-05 at91sam9261 28.6.18 pio multi-driver enable register name: pio_mder access type: write-only p0-p31: multi drive enable. 0 = no effect. 1 = enables multi drive on the i/o line. 28.6.19 pio multi-driver disable register name: pio_mddr access type: write-only p0-p31: multi drive disable. 0 = no effect. 1 = disables multi drive on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 330 6062b?atarm?15-nov-05 at91sam9261 28.6.20 pio multi-driver status register name: pio_mdsr access type: read-only p0-p31: multi drive status. 0 = the multi drive is disabled on the i/o line. the pin is driven at high and low level. 1 = the multi drive is enabled on the i/o lin e. the pin is driven at low level only. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 331 6062b?atarm?15-nov-05 at91sam9261 28.6.21 pio pull up disable register name: pio_pudr access type: write-only p0-p31: pull up disable. 0 = no effect. 1 = disables the pull up resistor on the i/o line. 28.6.22 pio pull up enable register name: pio_puer access type: write-only p0-p31: pull up enable. 0 = no effect. 1 = enables the pull up resistor on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 332 6062b?atarm?15-nov-05 at91sam9261 28.6.23 pio pull up status register name: pio_pusr access type: read-only p0-p31: pull up status. 0 = pull up resistor is enabled on the i/o line. 1 = pull up resistor is disabled on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 333 6062b?atarm?15-nov-05 at91sam9261 28.6.24 pio peripheral a select register name: pio_asr access type: write-only p0-p31: peripheral a select. 0 = no effect. 1 = assigns the i/o line to the peripheral a function. 28.6.25 pio peripheral b select register name: pio_bsr access type: write-only p0-p31: peripheral b select. 0 = no effect. 1 = assigns the i/o line to the peripheral b function. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 334 6062b?atarm?15-nov-05 at91sam9261 28.6.26 pio peripheral a b status register name: pio_absr access type: read-only p0-p31: peripheral a b status. 0 = the i/o line is assigned to the peripheral a. 1 = the i/o line is assigned to the peripheral b. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 335 6062b?atarm?15-nov-05 at91sam9261 28.6.27 pio output write enable register name: pio_ower access type: write-only p0-p31: output write enable. 0 = no effect. 1 = enables writing pio_odsr for the i/o line. 28.6.28 pio output write disable register name: pio_owdr access type: write-only p0-p31: output write disable. 0 = no effect. 1 = disables writing pio_odsr for the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 336 6062b?atarm?15-nov-05 at91sam9261 28.6.29 pio output write status register name: pio_owsr access type: read-only p0-p31: output write status. 0 = writing pio_odsr does not affect the i/o line. 1 = writing pio_odsr affects the i/o line. 28.6.30 pio version register name: pio_version access type: read-only version reserved. value subject to change. no functionality associat ed. this is the atmel internal version of the macrocell. mfn reserved. value subject to change. no functionality associated. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ? ? 23 22 21 20 19 18 17 16 ? ? ? ? ? mfn 15 14 13 12 11 10 9 8 ? ? ? ? version 7 6 5 4 3 2 1 0 version 337 6062b?atarm?15-nov-05 at91sam9261 29. serial peripheral interface (spi) 29.1 description the serial peripheral interface (spi) circuit is a synchronous serial data link that provides communication with external devices in master or slave mode. it also enables communication between processors if an external processor is connected to the system. the serial peripheral interface is essentially a shif t register that serially transmits data bits to other spis. during a data transfer, one spi system acts as the ?master?' which controls the data flow, while the other devices act as ?slave s'' which have data shifted into and out by the master. different cpus can take turn being mast ers (multiple master protocol opposite to sin- gle master protocol where one cpu is always the master while all of the others are always slaves) and one master may simultaneously shift da ta into multiple slaves. however, only one slave may drive its output to write data back to the master at any given time. a slave device is selected when the master asse rts its nss signal. if multiple slave devices exist, the master generates a separate slav e select signal for each slave (npcs). the spi system consists of two data lines and two control lines: master out slave in (mosi): this data line supplies the output data from the master shifted into the input(s) of the slave(s). master in slave out (miso): this data line supplies the output data from a slave to the input of the master. there may be no more than one slave transmitting data during any particular transfer. serial clock (spck): this control line is driven by the master and regulates the flow of the data bits. the master may transmit data at a variety of baud rates; the spck line cycles once for each bit that is transmitted. slave select (nss): this control line allows slaves to be turned on and off by hardware. 338 6062b?atarm?15-nov-05 at91sam9261 29.2 block diagram figure 29-1. block diagram 29.3 application block diagram figure 29-2. application block diagram: single master/multiple slave implementation spi interface interrupt control pio pdc pmc mck spi interrupt spck miso mosi npcs0/nss npcs1 npcs2 npcs3 apb spi master spck miso mosi npcs0 npcs1 npcs2 spck miso mosi nss slave 0 spck miso mosi nss slave 1 spck miso mosi nss slave 2 nc npcs3 339 6062b?atarm?15-nov-05 at91sam9261 29.4 signal description 29.5 product dependencies 29.5.1 i/o lines the pins used for interfacing the compliant ex ternal devices may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the spi pins to their peripheral functions. 29.5.2 power management the spi may be clocked through the power management controller (pmc), thus the program- mer must first configure the pmc to enable the spi clock. 29.5.3 interrupt the spi interface has an interrupt line connected to the advanced interrupt controller (aic). handling the spi interrupt requires programming the aic before configuring the spi. table 29-1. signal description pin name pin description type master slave miso master in slave out input output mosi master out slave in output input spck serial clock output input npcs1-npcs3 peripheral chip selects output unused npcs0/nss peripheral chip select/slave select output input 340 6062b?atarm?15-nov-05 at91sam9261 29.6 functional description 29.6.1 modes of operation the spi operates in master mode or in slave mode. operation in master mode is programmed by wr iting at 1 the mstr bit in the mode register. the pins npcs0 to npcs3 are al l configured as outputs, the sp ck pin is driven, the miso line is wired on the receiver input and the mosi line driven as an output by the transmitter. if the mstr bit is written at 0, the spi operates in slave mode. the miso line is driven by the transmitter output, the mosi line is wired on the receiver input, the spck pin is driven by the transmitter to synchronize the receiver. the npcs0 pin becomes an input, and is used as a slave select signal (nss). the pins npcs1 to npcs3 are not driven and can be used for other purposes. the data transfers are identically programmable for both modes of operations. the baud rate generator is activated only in master mode. 29.6.2 data transfer four combinations of polarity and phase are ava ilable for data transfers. the clock polarity is programmed with the cpol bit in the chip select register. the clock phase is programmed with the ncpha bit. these two parameters dete rmine the edges of the clock signal on which data is driven and sampled. each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. thus, a master/slave pair must use the same parameter pair values to communicate. if multiple slaves are used and fixed in different configurations, the master mu st reconfigure itself each time it needs to com- municate with a different slave. table 29-2 shows the four modes and corresponding parameter settings. figure 29-3 and figure 29-4 show examples of data transfers. table 29-2. spi bus protocol mode spi mode cpol ncpha 001 100 211 310 341 6062b?atarm?15-nov-05 at91sam9261 figure 29-3. spi transfer format (ncpha = 1, 8 bits per transfer) figure 29-4. spi transfer format (ncpha = 0, 8 bits per transfer) 6 * spck (cpol = 0) spck (cpol = 1) mosi (from master) miso (from slave) nss (to slave) spck cycle (for reference) msb msb lsb lsb 6 6 5 5 4 4 3 3 2 2 1 1 * not defined, but normally msb of previous character received. 1 2345 78 6 * spck (cpol = 0) spck (cpol = 1) 1 2345 7 mosi (from master) miso (from slave) nss (to slave) spck cycle (for reference) 8 msb msb lsb lsb 6 6 5 5 4 4 3 3 1 1 * not defined but normally lsb of previous character transmitted. 2 2 6 342 6062b?atarm?15-nov-05 at91sam9261 29.6.3 master mode operations when configured in master mode, the spi operates on the clock generated by the internal pro- grammable baud rate generator. it fully controls the data transfers to and from the slave(s) connected to the spi bus. the spi drives the chip select line to the slave and the serial clock signal (spck). the spi features two holding registers, the transmit data register and the receive data reg- ister, and a single shift register. the holding registers maintain the data flow at a constant rate. after enabling the spi, a data transfer begins when the processor writes to the spi_tdr (transmit data register). the wr itten data is immediately transferred in the shift register and transfer on the spi bus starts. while the data in the shift register is shifted on the mosi line, the miso line is sampled and shifted in the shift register. transmission cannot occur without reception. before writting the tdr, the pcs field must be set in order to select a slave. if new data is written in spi_tdr du ring the transfer, it stays in it until the current transfer is completed. then, the received data is transferr ed from the shift register to spi_rdr, the data in spi_tdr is loaded in the shift register and a new transfer starts. the transfer of a data written in spi_tdr in the shift register is indicated by the tdre bit (transmit data register empty) in the status register (spi_sr). when new data is written in spi_tdr, this bit is cleared. the tdre bit is used to trigger the transmit pdc channel. the end of transfer is indicated by the txempty flag in the spi_sr register. if a transfer delay (dlybct) is greater than 0 for the last transfer, txempty is set after the completion of said delay. the master clock (mck) can be switched off at this time. the transfer of received data fr om the shift register in spi_rdr is indicated by the rdrf bit (receive data register full) in the status register (spi_sr). when the received data is read, the rdrf bit is cleared. if the spi_rdr (receive data regi ster) has not been r ead before new data is received, the overrun error bit (ovres) in spi_sr is set. as lo ng as this flag is set, no data is loaded in spi_rdr. the user has to read the status register to clear the ovres bit. figure 29-6 on page 344 shows a block diagram of the spi when operating in master mode. figure 29-6 on page 344 shows a flow chart describing how transfers are handled. 343 6062b?atarm?15-nov-05 at91sam9261 29.6.3.1 master mode block diagram figure 29-5. master mode block diagram shift register spck mosi lsb msb miso spi_rdr rd spi clock tdre spi_tdr td rdrf ovres spi_csr0..3 cpol ncpha bits mck baud rate generator spi_csr0..3 scbr npcs3 npcs0 npcs2 npcs1 npcs0 0 1 ps spi_mr pcs spi_tdr pcs modf current peripheral spi_rdr pcs spi_csr0..3 csaat pcsdec modfdis mstr 344 6062b?atarm?15-nov-05 at91sam9261 29.6.3.2 master mode flow diagram figure 29-6. master mode flow diagram s spi enable csaat ? ps ? 1 0 0 1 1 npcs = spi_tdr(pcs) npcs = spi_mr(pcs) delay dlybs serializer = spi_tdr(td) tdre = 1 data transfer spi_rdr(rd) = serializer rdrf = 1 tdre ? npcs = 0xf delay dlybcs fixed peripheral variable peripheral delay dlybct 0 1 csaat ? 0 tdre ? 1 0 ps ? 0 1 spi_tdr(pcs) = npcs ? no yes spi_mr(pcs) = npcs ? no npcs = 0xf delay dlybcs npcs = spi_tdr(pcs) npcs = 0xf delay dlybcs npcs = spi_mr(pcs), spi_tdr(pcs) fixed peripheral variable peripheral - npcs defines the current chip select - csaat, dlybs, dlybct refer to the fields of the chip select register corresponding to the current chip select - when npcs is 0xf, csaat is 0. 345 6062b?atarm?15-nov-05 at91sam9261 29.6.3.3 clock generation the spi baud rate clock is generated by dividing the master clock (mck) by a value between 1 and 255. this allows a maximum operating baud rate at up to master clock and a minimum operating baud rate of mck divided by 255. programming the scbr field at 0 is forbidden. triggering a transfer while scbr is at 0 can lead to unpredictable results. at reset, scbr is 0 and the user has to program it at a valid value before performing the first transfer. the divisor can be defined independently for each chip select, as it has to be programmed in the scbr field of the chip select registers. this allows the spi to automatically adapt the baud rate for each interfaced peripheral without reprogramming. 29.6.3.4 transfer delays figure 29-7 shows a chip select transfer change and consecutive transfers on the same chip select. three delays can be programmed to modify the transfer waveforms: the delay between chip selects, programmable only once for all the chip selects by writing the dlybcs field in the mode register. allows insertion of a delay between release of one chip select and before assertion of a new one. the delay before spck, independently programmable for each chip select by writing the field dlybs. allows the start of spck to be delayed after the chip select has been asserted. the delay between consecutive transfers, independently programmable for each chip select by writing the dlybct field. allows insertion of a delay between two transfers occurring on the same chip select these delays allow the spi to be adapted to the interfaced peripherals and their speed and bus release time. figure 29-7. programmable delays dlybcs dlybs dlybct dlybct chip select 1 chip select 2 spck 346 6062b?atarm?15-nov-05 at91sam9261 29.6.3.5 peripheral selection the serial peripherals are selected through the assertion of the npcs0 to npcs3 signals. by default, all the npcs signals are high before and after each transfer. the peripheral selection can be performed in two different ways: fixed peripheral select: spi exchanges data with only one peripheral variable peripheral select: data can be exchanged with more than one peripheral fixed peripheral select is activated by writing t he ps bit to zero in spi_mr (mode register). in this case, the current peripheral is defined by the pcs field in spi_mr and the pcs field in the spi_tdr has no effect. variable peripheral select is activated by se tting ps bit to one. the pcs field in spi_tdr is used to select the current peripheral. this means that the peripheral selection can be defined for each new data. the fixed peripheral selection allows buffer transfers with a single peripheral. using the pdc is an optimal means, as the size of the data tran sfer between the memory and the spi is either 8 bits or 16 bits. however, changing the peripheral selection requires the mode register to be reprogrammed. the variable peripheral selection allows buffer transfers with multiple peripherals without reprogramming the mode register. data written in spi_tdr is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to. using the pdc in this mode requires 32-bit wide buffers, with the data in the lsbs and the pcs and lastxfer fields in the msbs, however the spi still cont rols the number of bits (8 t o16) to be tran sferred through miso and mosi lines with the chip select conf iguration registers. this is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor. 29.6.3.6 peripheral chip select decoding the user can program the spi to operate with up to 15 peripherals by decoding the four chip select lines, npcs0 to npcs3 with an external logic. this can be enabled by writing the pcs- dec bit at 1 in the mode register (spi_mr). when operating without decoding, the spi makes sure that in any case only one chip select line is activated, i.e. dr iven low at a time. if two bits are defined low in a pcs field, only the low- est numbered chip sele ct is driven low. when operating with decoding, the spi directly outputs the value defined by the pcs field of either the mode register or the transmit data register (depending on ps). as the spi sets a default value of 0xf on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded. the spi has only four chip select registers, not 15. as a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. as an example, spi_crs0 defines the characteristics of t he externally decoded peripherals 0 to 3, corre- sponding to the pcs values 0x0 to 0x3. thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. 347 6062b?atarm?15-nov-05 at91sam9261 29.6.3.7 peripheral deselection when operating normally, as soon as the transfer of the last data written in spi_tdr is com- pleted, the npcs lines all rise. this might lead to runtime error if the processor is too long in responding to an interrupt, and thus might lead to di fficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers. to facilitate interfacing with such devices, the chip select register can be programmed with the csaat bit (chip select active after transfer) at 1. this a llows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required. figure 29-8 shows different peripheral deselection cases and the effect of the csaat bit. figure 29-8. peripheral deselection 29.6.3.8 mode fault detection a mode fault is detected when the spi is programmed in master mode and a low level is driven by an external master on the npcs0/nss si gnal. as this pin is generally configured in open-drain, it is important that a pull up resistor is connected on the npcs0 line, so that a high level is guaranteed and no spurious mode fault is detected. when a mode fault is detected, the modf bit in the spi_sr is set until the spi_sr is read and the spi is automatically disabled until re-enabled by writing the spien bit in the spi_cr (control register) at 1. a npcs[0..3] write spi_tdr tdre npcs[0..3] write spi_tdr tdre npcs[0..3] write spi_tdr tdre dlybcs pcs = a dlybcs dlybct a pcs = b b dlybcs pcs = a dlybcs dlybct a pcs = b b dlybcs dlybct pcs=a a dlybcs dlybct a pcs = a a a dlybct aa csaat = 0 dlybct aa csaat = 1 a 348 6062b?atarm?15-nov-05 at91sam9261 by default, the mode fault detection circuitry is enabled. the user can disable mode fault detection by setting the modfdis bit in the spi mode register (spi_mr). 29.6.4 spi slave mode when operating in slave mode, the spi processes data bits on the clock provided on the spi clock pin (spck). the spi waits for nss to go active before receiving the serial clock from an external master. when nss falls, the clock is validated on the se rializer, which processes the number of bits defined by the bits field of the chip select register 0 (spi_csr0). these bits are processed following a phase and a polarity defined respec tively by the ncpha and cpol bits of the spi_csr0. note that bits, cpol and ncpha of the other chip select registers have no effect when the spi is programmed in slave mode. the bits are shifted out on the miso line and sampled on the mosi line. when all the bits are processed, the received data is transferred in the receive data register and the rdrf bit rises. if rdrf is already high when the data is transferred, the overrun bit rises and the data transfer to spi_rdr is aborted. when a transfer starts, the data shifted out is the data present in the shift register. if no data has been written in the transmit data register (spi_tdr), the last data received is trans- ferred. if no data has been received since the last reset, all bits are transmitted low, as the shift register resets at 0. when a first data is written in spi_tdr, it is transferred immediately in the shift register and the tdre bit rises. if new data is written, it remains in spi_tdr until a transfer occurs, i.e. nss falls and there is a valid clock on the spck pin. when the transfer occurs, the last data written in spi_tdr is transferred in the shift register and the tdre bit rises. this enables frequent updates of critical variables with single transfers. then, a new data is loaded in the shift register from the transmit data register. in case no character is ready to be transmitted, i.e. no character has been written in spi_tdr since the last load from spi_tdr to the shift register, the shift register is not modified and the last received character is retransmitted. figure 29-9 shows a block diagram of the spi when operating in slave mode. 349 6062b?atarm?15-nov-05 at91sam9261 figure 29-9. slave mode functional block diagram shift register spck spiens lsb msb nss mosi spi_rdr rd spi clock tdre spi_tdr td rdrf ovres spi_csr0 cpol ncpha bits fload spien spidis miso 350 6062b?atarm?15-nov-05 at91sam9261 29.7 serial peripheral inte rface (spi) user interface table 29-3. spi register mapping offset register register name access reset 0x00 control register spi_cr write-only --- 0x04 mode register spi_mr read/write 0x0 0x08 receive data register spi_rdr read-only 0x0 0x0c transmit data register spi_tdr write-only --- 0x10 status register spi_sr read-only 0x000000f0 0x14 interrupt enable register spi_ier write-only --- 0x18 interrupt disable register spi_idr write-only --- 0x1c interrupt mask register spi_imr read-only 0x0 0x20 - 0x2c reserved 0x30 chip select register 0 spi_csr0 read/write 0x0 0x34 chip select register 1 spi_csr1 read/write 0x0 0x38 chip select register 2 spi_csr2 read/write 0x0 0x3c chip select register 3 spi_csr3 read/write 0x0 0x004c - 0x00f8 reserved ? ? ? 0x004c - 0x00fc reserved ? ? ? 0x100 - 0x124 reserved for the pdc 351 6062b?atarm?15-nov-05 at91sam9261 29.7.1 spi control register name: spi_cr access type: write-only spien: spi enable 0 = no effect. 1 = enables the spi to transfer and receive data. spidis: spi disable 0 = no effect. 1 = disables the spi. as soon as spidis is set, spi finishes its tranfer. all pins are set in input mode and no data is received or transmitted. if a transfer is in progress, the transfer is finished before the spi is disabled. if both spien and spidis are equal to one when the control register is written, the spi is disabled. swrst: spi software reset 0 = no effect. 1 = reset the spi. a software-triggered hardware reset of the spi interface is performed. lastxfer: last transfer 0 = no effect. 1 = the current npcs will be deasserted afte r the character written in td has been tr ansferred. when c saat is set, this allows to close the communication with the current serial periph eral by raising the correspondi ng npcs line as soon as td transfer has completed. 31 30 29 28 27 26 25 24 ???????lastxfer 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 swrst?????spidisspien 352 6062b?atarm?15-nov-05 at91sam9261 29.7.2 spi mode register name: spi_mr access type: read/write mstr: master/slave mode 0 = spi is in slave mode. 1 = spi is in master mode. ps: peripheral select 0 = fixed peripheral select. 1 = variable peripheral select. pcsdec: chip select decode 0 = the chip selects are directly connected to a peripheral device. 1 = the four chip select lines are connected to a 4- to 16-bit decoder. when pcsdec equals one, up to 15 chip select signals can be generated with the four lines using an external 4- to 16-bit decoder. the chip select registers define the characteristics of the 15 chip selects according to the following rules: spi_csr0 defines peripheral chip select signals 0 to 3. spi_csr1 defines peripheral chip select signals 4 to 7. spi_csr2 defines peripheral chip select signals 8 to 11. spi_csr3 defines peripheral chip select signals 12 to 14. modfdis: mode fault detection 0 = mode fault detection is enabled. 1 = mode fault detection is disabled. llb: local loopback enable 0 = local loopback path disabled. 1 = local loopback path enabled ( llb controls the local loopback on the data serializer for te sting in master mode only. (miso is internally connected on mosi.) pcs: peripheral chip select this field is only used if fixed peripheral select is active (ps = 0). if pcsdec = 0: pcs = xxx0 npcs[3:0] = 1110 pcs = xx01 npcs[3:0] = 1101 pcs = x011 npcs[3:0] = 1011 pcs = 0111 npcs[3:0] = 0111 31 30 29 28 27 26 25 24 dlybcs 23 22 21 20 19 18 17 16 ???? pcs 15 14 13 12 11 10 9 8 ???????? 76543210 llb ? ? modfdis pcsdec ps mstr 353 6062b?atarm?15-nov-05 at91sam9261 pcs = 1111 forbidden (no peripheral is selected) (x = don?t care) if pcsdec = 1: npcs[3:0] output signals = pcs. dlybcs: delay between chip selects this field defines the delay from npcs inactive to the ac tivation of another npcs. the dlybcs time guarantees non-over- lapping chip selects and solves bus contentions in case of peripherals having long data float times. if dlybcs is less than or eq ual to six, six mck periods will be inserted by default. otherwise, the following equat ion determines the delay: delay between chip selects dlybcs mck ---------------------- - = 354 6062b?atarm?15-nov-05 at91sam9261 29.7.3 spi receive data register name: spi_rdr access type: read-only rd: receive data data received by the spi interface is stored in this register right-justified. unused bits read zero. pcs: peripheral chip select in master mode only, these bits indicate the value on the npcs pins at the end of a transfer. otherwise, these bits read zero. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???? pcs 15 14 13 12 11 10 9 8 rd 76543210 rd 355 6062b?atarm?15-nov-05 at91sam9261 29.7.4 spi transmit data register name: spi_tdr access type: write-only td: transmit data data to be transmitted by the spi interface is stored in this register. information to be transmitted must be written to the transmit data register in a right-justified format. pcs: peripheral chip select this field is only used if variable peripheral select is active (ps = 1). if pcsdec = 0: pcs = xxx0 npcs[3:0] = 1110 pcs = xx01 npcs[3:0] = 1101 pcs = x011 npcs[3:0] = 1011 pcs = 0111 npcs[3:0] = 0111 pcs = 1111 forbidden (no peripheral is selected) (x = don?t care) if pcsdec = 1: npcs[3:0] output signals = pcs lastxfer: last transfer 0 = no effect. 1 = the current npcs will be deasserted afte r the character written in td has been tr ansferred. when c saat is set, this allows to close the communication with the current serial periph eral by raising the correspondi ng npcs line as soon as td transfer has completed. this field is only used if variable peripheral select is active (ps = 1). 31 30 29 28 27 26 25 24 ???????lastxfer 23 22 21 20 19 18 17 16 ???? pcs 15 14 13 12 11 10 9 8 td 76543210 td 356 6062b?atarm?15-nov-05 at91sam9261 29.7.5 spi status register name: spi_sr access type: read-only rdrf: receive data register full 0 = no data has been received since the last read of spi_rdr 1 = data has been received and the received data has been transferred from the serializer to spi_rdr since the last read of spi_rdr. tdre: transmit data register empty 0 = data has been written to spi_tdr and not yet transferred to the serializer. 1 = the last data written in the transmit data register has been transferred to the serializer. tdre equals zero when the spi is disabled or at reset. the spi enable command sets this bit to one. modf: mode fault error 0 = no mode fault has been detected since the last read of spi_sr. 1 = a mode fault occurred since the last read of the spi_sr. ovres: overrun error status 0 = no overrun has been detected since the last read of spi_sr. 1 = an overrun has occurred since the last read of spi_sr. an overrun occurs when spi_r dr is loaded at least twice from the serializer since the last read of the spi_rdr. endrx: end of rx buffer 0 = the receive counter register has not reached 0 since the last write in spi_rcr (1) or spi_rncr (1) . 1 = the receive counter register has reached 0 since the last write in spi_rcr (1) or spi_rncr (1) . endtx: end of tx buffer 0 = the transmit counter register has not reached 0 since the last write in spi_tcr (1) or spi_tncr (1) . 1 = the transmit counter register has reached 0 since the last write in spi_tcr (1) or spi_tncr (1) . rxbuff: rx buffer full 0 = spi_rcr (1) or spi_rncr (1) has a value other than 0. 1 = both spi_rcr (1) and spi_rncr (1) have a value of 0. txbufe: tx buffer empty 0 = spi_tcr (1) or spi_tncr (1) has a value other than 0. 1 = both spi_tcr (1) and spi_tncr (1) have a value of 0. nssr: nss rising 0 = no rising edge detected on nss pin since last read. 1 = a rising edge occurred on nss pin since last read. txempty: transmission registers empty 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????spiens 15 14 13 12 11 10 9 8 ??????txemptynssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf 357 6062b?atarm?15-nov-05 at91sam9261 0 = as soon as data is written in spi_tdr. 1 = spi_tdr and internal shifter are empty. if a transfer delay has been defined, txempty is set after the completion of such delay. spiens: spi enable status 0 = spi is disabled. 1 = spi is enabled. note: 1. spi_rcr, spi_rncr, spi_tcr, spi_tncr are physically located in the pdc. 358 6062b?atarm?15-nov-05 at91sam9261 29.7.6 spi interrupt enable register name: spi_ier access type: write-only rdrf: receive data register full interrupt enable tdre: spi transmit data regi ster empty interrupt enable modf: mode fault error interrupt enable ovres: overrun error interrupt enable endrx: end of receive buffer interrupt enable endtx: end of transmit buffer interrupt enable rxbuff: receive buffer full interrupt enable txbufe: transmit buffer empty interrupt enable txempty: transmission registers empty enable nssr: nss rising interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????txemptynssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf 359 6062b?atarm?15-nov-05 at91sam9261 29.7.7 spi interrupt disable register name: spi_idr access type: write-only rdrf: receive data register full interrupt disable tdre: spi transmit data register empty interrupt disable modf: mode fault error interrupt disable ovres: overrun error interrupt disable endrx: end of receive buffer interrupt disable endtx: end of transmit buffer interrupt disable rxbuff: receive buffer full interrupt disable txbufe: transmit buffer empty interrupt disable txempty: transmission registers empty disable nssr: nss rising interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????txemptynssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf 360 6062b?atarm?15-nov-05 at91sam9261 29.7.8 spi interrupt mask register name: spi_imr access type: read-only rdrf: receive data register full interrupt mask tdre: spi transmit data register empty interrupt mask modf: mode fault error interrupt mask ovres: overrun error interrupt mask endrx: end of receive buffer interrupt mask endtx: end of transmit buffer interrupt mask rxbuff: receive buffer full interrupt mask txbufe: transmit buffer empty interrupt mask txempty: transmission registers empty mask nssr: nss rising interrupt mask 0 = the corresponding interrupt is not enabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????txemptynssr 76543210 txbufe rxbuff endtx endrx ovres modf tdre rdrf 361 6062b?atarm?15-nov-05 at91sam9261 29.7.9 spi chip select register name: spi_csr0... spi_csr3 access type: read/write cpol: clock polarity 0 = the inactive state value of spck is logic level zero. 1 = the inactive state value of spck is logic level one. cpol is used to determine the inactive state value of the serial clock (spck). it is used with ncpha to produce the required clock/data relationship between master and slave devices. ncpha: clock phase 0 = data is changed on the leading edge of spck and captured on the following edge of spck. 1 = data is captured on the leading edge of spck and changed on the following edge of spck. ncpha determines which edge of spck causes data to c hange and which edge causes data to be captured. ncpha is used with cpol to produce the required clock/da ta relationship between master and slave devices. csaat: chip select active after transfer 0 = the peripheral chip select line rises as soon as the last transfer is achieved. 1 = the peripheral chip select does not rise after the last tr ansfer is achieved. it remains active until a new transfer is requested on a different chip select. bits: bits per transfer the bits field determines the number of data bits transferred. reserved values should not be used. 31 30 29 28 27 26 25 24 dlybct 23 22 21 20 19 18 17 16 dlybs 15 14 13 12 11 10 9 8 scbr 76543210 bits csaat ? ncpha cpol bits bits per transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 reserved 1010 reserved 1011 reserved 362 6062b?atarm?15-nov-05 at91sam9261 scbr: serial clock baud rate in master mode, the spi interface uses a modulus counter to derive the spck baud rate from the master clock mck. the baud rate is selected by writing a value from 1 to 255 in the scbr field. the following equations determine the spck baud rate: programming the scbr field at 0 is forbidden. triggering a trans fer while scbr is at 0 can le ad to unpredictable results. at reset, scbr is 0 and the user has to program it at a valid value before performing the first transfer. dlybs: delay before spck this field defines the delay from npcs valid to the first valid spck transition. when dlybs equals zero, the npcs valid to spck transition is 1/2 the spck clock period. otherwise, the following equations determine the delay: dlybct: delay between consecutive transfers this field defines the delay between two consecutive transfers with the same perip heral without removing the chip select. the delay is always inserted after each transfer and before removing the chip select if needed. when dlybct equals zero, no delay between consecutive transf ers is inserted and the clock keeps its duty cycle over the character transfers. otherwise, the following equat ion determines the delay: 1100 reserved 1101 reserved 1110 reserved 1111 reserved bits bits per transfer spck baudrate mck scbr -------------- - = delay before spck dlybs mck ------------------ - = delay between consecutive transfers 32 dlybct mck ------------------------------------- scbr 2 mck ---------------- - + = 363 6062b?atarm?15-nov-05 at91sam9261 30. two-wire interface (twi) 30.1 overview the two-wire interface (twi) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 kbits per second, based on a byte-ori- ented transfer format. it can be used with any atme l two-wire bus serial eeprom. the twi is programmable as a master with sequential or single-byte access. a configurable baud rate gen- erator permits the output data rate to be adapted to a wide range of core clock frequencies. 30.2 block diagram figure 30-1. block diagram 30.3 application block diagram figure 30-2. application block diagram apb bridge pmc mck two-wire interface pio aic twi interrupt twck twd host with twi interface twd twck at24lc16 u1 at24lc16 u2 lcd controller u3 slave 1 slave 2 slave 3 rr vdd 364 6062b?atarm?15-nov-05 at91sam9261 30.4 product dependencies 30.4.1 i/o lines description both twd and twck are bidirectional lines, connect ed to a positive supply voltage via a current source or pull-up resistor (see figure 30-2 on page 363 ). when the bus is free, both lines are high. the output stages of devices connected to the bus must have an open-drain or open-col- lector to perform the wired-and function. twd and twck pins may be multiplexed with pi o lines. to enable the twi, the programmer must perform the following steps: program the pio controller to: ? dedicate twd and twck as peripheral lines. ? define twd and twck as open-drain. 30.4.2 power management enable the peripheral clock. the twi interface may be clocked through the power management controller (pmc), thus the programmer must first configure the pmc to enable the twi clock. 30.4.3 interrupt the twi interface has an interrupt line connected to the advanced interrupt controller (aic). in order to handle interrupts, the aic must be programmed before configuring the twi. table 30-1. i/o lines description pin name pin description type twd two-wire serial data input/output twck two-wire serial clock input/output 365 6062b?atarm?15-nov-05 at91sam9261 30.5 functional description 30.5.1 transfer format the data put on the twd line must be 8 bits long. data is transferred msb first; each byte must be followed by an acknowledgement. the number of bytes per transfer is unlimited (see figure 30-4 on page 365 ). each transfer begins with a start condition and terminates with a stop condition (see figure 30-3 on page 365 ). a high-to-low transition on the twd line while twck is high defines the start condition. a low-to-high transition on the twd line while twck is high defines a stop condition. figure 30-3. start and stop conditions figure 30-4. transfer format 30.5.2 modes of operation the twi has two modes of operation: master transmitter mode master receiver mode the twi control register (twi_cr) allows configuration of the interface in master mode. in this mode, it generates the clock according to the value programmed in the clock waveform gener- ator register (twi_cwgr). this register defines the twck signal completely, enabling the interface to be adapted to a wide range of clocks. 30.5.3 transmitting data after the master initiates a start condition, it sends a 7-bit slave address, configured in the mas- ter mode register (dadr in twi_mmr), to notify the slave device. the bit following the slave address indicates the transfer direction (write or read). if this bit is 0, it indicates a write operation (transmit operation). if the bit is 1, it indica tes a request for data read (receive operation). the twi transfers require the slave to acknowledge each received byte. during the acknowl- edge clock pulse, the master releases the data line (high), enabling the slave to pull it down in order to generate the acknowledge. the master polls the data line during this clock pulse and twd twck start stop twd twck start address r/w ack data ack data ack stop 366 6062b?atarm?15-nov-05 at91sam9261 sets the nak bit in the status register if the slave does not acknowledge the byte. as with the other status bits, an interrupt can be generated if enabled in the interrupt enable register (twi_ier). after writing in the transmit-holding register (twi_thr), setting the start bit in the control register starts the transmission. the data is shifted in the internal shifter and when an acknowledge is detected, the txrdy bit is set until a new write in the twi_thr (see figure 30- 6 below). the master generates a stop condition to end the transfer. the read sequence begins by setting the start bit. when the rxrdy bit is set in the status register, a character has been received in the receive-holding register (twi_rhr). the rxrdy bit is reset when reading the twi_rhr. the twi interface performs various transfer formats (7-bit slave address, 10-bit slave address). the three internal address bytes are configurable through the master mode register (twi_mmr). if the slave device supports only a 7-bit address, iadrsz must be set to 0. for a slave address higher than 7 bits, the user must configure the address size (iadrsz ) and set the other slave address bits in the internal address register (twi_iadr). figure 30-5. master write with one, two or three bytes internal address and one data byte figure 30-6. master write with one byte internal address and multiple data bytes figure 30-7. master read with one, two or three bytes internal address and one data byte s dadr w a iadr(23:16) a iadr(15:8) a iadr(7:0) a data a p s dadr w a iadr(15:8) a iadr(7:0) a p data a a iadr(7:0) a p data a s dadr w w d three bytes internal address two bytes internal address one byte internal address w d w d a iadr(7:0) a data a s dadr w data a p data a txcomp txrdy write thr write thr write thr write thr twd s dadr w a iadr(23:16) a iadr(15:8) a iadr(7:0) a s dadr w a iadr(15:8) a iadr(7:0) a a iadr(7:0) a s dadr w data n p s dadr r a s dadr r a data n p s dadr r a data n p twd twd twd three bytes internal address two bytes internal address one byte internal address 367 6062b?atarm?15-nov-05 at91sam9261 figure 30-8. master read with one byte internal address and multiple data bytes s = start p = stop w = write r = read a = acknowledge n = not acknowledge dadr = device address iadr = internal address figure 30-9 below shows a byte write to an atmel at24lc512 eeprom. this demonstrates the use of internal addresses to access the device. figure 30-9. internal address usage 30.5.4 read/write flowcharts the following flowcharts shown in figure 30-10 on page 368 and in figure 30-11 on page 369 give examples for read and write operations in master mode. a polling or interrupt method can be used to check the status bits. the interrupt method requires that the interrupt enable register (twi_ier) be configured first. a iadr(7:0) a s dadr w s dadr r a data a data n p txcomp write start bit rxrdy write stop bit read rhr read rhr twd s t a r t m s b device address 0 l s b r / w a c k m s b w r i t e a c k a c k l s b a c k first word address second word address data s t o p 368 6062b?atarm?15-nov-05 at91sam9261 figure 30-10. twi write in master mode set twi clock: twi_cwgr = clock set the control register: - master enable twi_cr = msen set the master mode register: - device slave address - internal address size - transfer direction bit write ==> bit mread = 0 internal address size = 0? load transmit register twi_thr = data to send start the transfer twi_cr = start stop the transfer twi_cr = stop read status register txrdy = 0? data to send? read status register txcomp = 0? end start set theinternal address twi_iadr = address ye s twi_thr = data to send ye s ye s ye s 369 6062b?atarm?15-nov-05 at91sam9261 figure 30-11. twi read in master mode set twi clock: twi_cwgr = clock set the control register: - master enable - slave disable twi_cr = msen set the master mode register: - device slave address - internal address size - transfer direction bit read ==> bit mread = 0 internal address size = 0? start the transfer twi_cr = start stop the transfer twi_cr = stop read status register rxrdy = 0? data to read? read status register txcomp = 0? end start set the internal address twi_iadr = address ye s ye s ye s ye s 370 6062b?atarm?15-nov-05 at91sam9261 30.6 two-wire interface (t wi) user interface table 30-2. two-wire interface (twi) register mapping offset register name access reset value 0x0000 control register twi_cr write-only n/a 0x0004 master mode register twi_mmr read/write 0x0000 0x0008 reserved ? ? ? 0x000c internal address register twi_iadr read/write 0x0000 0x0010 clock waveform generator register twi_cwgr read/write 0x0000 0x0020 status register twi_sr read-only 0x0008 0x0024 interrupt enable register twi_ier write-only n/a 0x0028 interrupt disable register twi_idr write-only n/a 0x002c interrupt mask register twi_imr read-only 0x0000 0x0030 receive holding register twi_rhr read-only 0x0000 0x0034 transmit holding register twi_thr read/write 0x0000 0x0038-0x00fc reserved ? ? ? 371 6062b?atarm?15-nov-05 at91sam9261 30.6.1 twi control register register name :twi_cr access type: write-only start: send a start condition 0 = no effect. 1 = a frame beginning with a start bit is transmitted according to the features defined in the mode register. this action is necessary when the twi peripheral wants to read data from a slave. when configured in master mode with a write operation, a frame is sent with the mode register as soon as the user writes a character in the holding register. stop: send a stop condition 0 = no effect. 1 = stop condition is sent just after completing the current byte transmission in master read or write mode. in single data byte master read or write, the start and stop must both be set. in multiple data bytes master read or write, the stop must be set before ack/nack bit transmission. in master read mode, if a nack bit is received, the stop is automatically performed. in multiple data write operation, when both thr and shift register are empty, a stop condition is automatically sent. msen: twi master transfer enabled 0 = no effect. 1 = if msdis = 0, the master data transfer is enabled. msdis: twi master transfer disabled 0 = no effect. 1 = the master data transfer is disabled, all pending data is tr ansmitted. the shifter and holding characters (if they contain data) are transmitted in case of write operation. in read operation, the character being transferred must be completely received before disabling. swrst: software reset 0 = no effect. 1 = equivalent to a system reset. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 swrst ? ? ? msdis msen stop start 372 6062b?atarm?15-nov-05 at91sam9261 30.6.2 twi master mode register register name :twi_mmr address type : read/write iadrsz: internal device address size mread: master read direction 0 = master write direction. 1 = master read direction. dadr: device address the device address is used in master mode to access slave devices in read or write mode. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?dadr 15 14 13 12 11 10 9 8 ???mread?? iadrsz 76543210 ???????? iadrsz[9:8] 0 0 no internal device address (byte command protocol) 0 1 one-byte internal device address 1 0 two-byte internal device address 1 1 three-byte internal device address 373 6062b?atarm?15-nov-05 at91sam9261 30.6.3 twi internal address register register name :twi_iadr access type : read/write iadr: internal address 0, 1, 2 or 3 bytes depending on iadrsz. ? low significant byte address in 10-bit mode addresses. 30.6.4 twi clock waveform generator register register name : twi_cwgr access type : read/write cldiv: clock low divider the scl low period is defined as follows: chdiv: clock high divider the scl high period is defined as follows: ckdiv: clock divider the ckdiv is used to increase both scl high and low periods. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 iadr 15 14 13 12 11 10 9 8 iadr 76543210 iadr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????? ckdiv 15 14 13 12 11 10 9 8 chdiv 76543210 cldiv t low cldiv ( 2 ckdiv () 3 ) t mck t high chdiv ( 2 ckdiv () 3 ) t mck 374 6062b?atarm?15-nov-05 at91sam9261 30.6.5 twi status register register name :twi_sr access type : read-only txcomp: transmission completed 0 = in master, during the length of the current frame. in slave, from start received to stop received. 1 = when both holding and shift registers are empty and stop condition has been sent (in master) or when msen is set (enable twi). rxrdy: receive hold ing register ready 0 = no character has been received since the last twi_rhr read operation. 1 = a byte has been received in the twi_rhr since the last read. txrdy: transmit holding register ready 0 = the transmit holding register has not been transferred into shift register. set to 0 when writing into twi_thr register. 1 = as soon as data byte is transferred from twi_thr to internal shifter or if a nack error is detected, txrdy is set at the same time as txcomp and nack. txrdy is also set when msen is set (enable twi). ovre: overrun error 0 = twi_rhr has not been loaded while rxrdy was set 1 = twi_rhr has been loaded while rxrdy was set. reset by read in twi_sr when txcomp is set. unre: underrun error 0 = no underrun error 1 = no valid data in twi_thr (txrdy set) while trying to load the data shifter. this action automatically generated a stop bit in master mode. reset by read in twi_sr when txcomp is set. nack: not acknowledged 0 = each data byte has been correctly received by the far-end side twi slave component. 1 = a data byte has not been acknowledged by the slave compon ent. set at the same time as txcomp. reset after read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????nack 76543210 unre ovre ? ? ? txrdy rxrdy txcomp 375 6062b?atarm?15-nov-05 at91sam9261 30.6.6 twi interrupt enable register register name :twi_ier access type: write-only txcomp: transmission completed rxrdy: receive hold ing register ready txrdy: transmit holding register ready ovre: overrun error unre: underrun error nack: not acknowledge 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????nack 76543210 unre ovre ? ? ? txrdy rxrdy txcomp 376 6062b?atarm?15-nov-05 at91sam9261 30.6.7 twi interrupt disable register register name :twi_idr access type: write-only txcomp: transmission completed rxrdy: receive hold ing register ready txrdy: transmit holding register ready ovre: overrun error unre: underrun error nack: not acknowledge 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????nack 76543210 unre ovre ? ? ? txrdy rxrdy txcomp 377 6062b?atarm?15-nov-05 at91sam9261 30.6.8 twi interrupt mask register register name :twi_imr access type : read-only txcomp: transmission completed rxrdy: receive hold ing register ready txrdy: transmit holding register ready ovre: overrun error unre: underrun error nack: not acknowledge 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????nack 76543210 unre ovre ? ? ? txrdy rxrdy txcomp 378 6062b?atarm?15-nov-05 at91sam9261 30.6.9 twi receive holding register register name : twi_rhr access type : read-only rxdata: master or slave receive holding data 30.6.10 twi transmit holding register register name :twi_thr access type: read/write txdata: master or slave transmit holding data 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rxdata 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 txdata 379 6062b?atarm?15-nov-05 at91sam9261 31. universal synchronous/asyn chronous receiver/transmitter 31.1 description the universal synchronous asynchronous receiv er transceiver (usart) provides one full duplex universal synchronous asynchronous serial link. data frame format is widely program- mable (data length, parity, number of stop bits) to support a maximum of standards. the receiver implements parity error, framing error and overrun error detection. the receiver time- out enables handling variable-length fr ames and the trans mitter timeguard facilitates commu- nications with slow remote devices. multidrop communications are also supported through address bit handling in reception and transmission. the usart features three test modes: remote loopback, local loopback and automatic echo. the usart supports specific operating modes providing interfaces on rs485 buses, with iso7816 t = 0 or t = 1 smart card slots and infrared transceivers. the hardware handshaking feature enables an out-of-band flow control by automatic management of the pins rts and cts. the usart supports the connection to the peripheral dma controller, which enables data transfers to the transmitter and from the receiver. the pdc provides chained buffer manage- ment without any intervention of the processor. 380 6062b?atarm?15-nov-05 at91sam9261 31.2 block diagram figure 31-1. usart block diagram peripheral dma controller channel channel aic receiver usart interrupt rxd txd sck usart pio controller cts rts transmitter baud rate generator user interface pmc mck slck div mck/div apb 381 6062b?atarm?15-nov-05 at91sam9261 31.3 application block diagram figure 31-2. application block diagram 31.4 i/o lines description table 31-1. i/o line description name description type active level sck serial clock i/o txd transmit serial data i/o rxd receive serial data input cts clear to send input low rts request to send output low smart card slot usart rs485 drivers differential bus irda transceivers field bus driver emv driver irda driver irlap rs232 drivers serial port serial driver ppp 382 6062b?atarm?15-nov-05 at91sam9261 31.5 product dependencies 31.5.1 i/o lines the pins used for interfacing the usart may be multiplexed with the pio lines. the program- mer must first program the pio controller to assign the desired usart pins to their peripheral function. if i/o lines of the usart are not used by the application, they can be used for other purposes by the pio controller. 31.5.2 power management the usart is not continuously clocked. the programmer must first enable the usart clock in the power management controller (pmc) before using the usart. however, if the applica- tion does not require usart operations, the usart clock can be stopped when not needed and be restarted later. in this case, the usart will resume its op erations where it left off. configuring the usart does not require the usart clock to be enabled. 31.5.3 interrupt the usart interrupt line is connected on one of the internal sources of the advanced inter- rupt controller. using the usart interrupt requires the aic to be programmed first. note that it is not recommended to use the usart interrupt line in edge sensitive mode. 383 6062b?atarm?15-nov-05 at91sam9261 31.6 functional description the usart is capable of managing several ty pes of serial synchronous or asynchronous communications. it supports the following communication modes: 5- to 9-bit full-duplex asynchronous serial communication ? msb- or lsb-first ? 1, 1.5 or 2 stop bits ? parity even, odd, marked, space or none ? by 8 or by 16 over-sampling receiver frequency ? optional hardware handshaking ? optional break management ? optional multidrop serial communication high-speed 5- to 9-bit full-duplex synchronous serial communication ? msb- or lsb-first ? 1 or 2 stop bits ? parity even, odd, marked, space or none ? by 8 or by 16 over-sampling frequency ? optional hardware handshaking ? optional break management ? optional multidrop serial communication rs485 with driver control signal iso7816, t0 or t1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit infrared irda modulation and demodulation test modes ? remote loopback, local loopback, automatic echo 31.6.1 baud rate generator the baud rate generator provides the bit period clock named the baud rate clock to both the receiver and the transmitter. the baud rate generator clock source can be selected by setting the usclks field in the mode register (us_mr) between: the master clock mck a division of the master clock, the divider being product dependent, but generally set to 8 the external clock, available on the sck pin the baud rate generator is based upon a 16-bit divider, which is programmed with the cd field of the baud rate generator register (us_brgr). if cd is programmed at 0, the baud rate generator does not generate any clock. if cd is programmed at 1, the divider is bypassed and becomes inactive. if the external sck clock is selected, the duratio n of the low and high levels of the signal pro- vided on the sck pin must be longer than a master clock (mck) period. the frequency of the signal provided on sck must be at least 4.5 times lower than mck. 384 6062b?atarm?15-nov-05 at91sam9261 figure 31-3. baud rate generator 31.6.1.1 baud rate in asynchronous mode if the usart is programmed to operate in asynchronous mode, the selected clock is first divided by cd, which is field programmed in th e baud rate generator register (us_brgr). the resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the over bit in us_mr. if over is set to 1, the receiver sampling is 8 times higher than the baud rate clock. if over is cleared, the sampling is performed at 16 times the baud rate clock. the following formula performs the calculation of the baud rate. this gives a maximum baud rate of mck divided by 8, assuming that mck is the highest pos- sible clock and that over is programmed at 1. baud rate calculation example table 31-2 shows calculations of cd to obtain a baud rate at 38400 bauds for different source clock frequencies. this table also shows the actual resulting baud rate and the error. mck/div 16-bit counter 0 baud rate clock cd cd sampling divider 0 1 >1 sampling clock reserved mck sck usclks over sck sync sync usclks = 3 1 0 2 3 0 1 0 1 fidi baudrate selectedclock 82 over ? () cd () table 31-2. baud rate example (over = 0) source clock expected baud rate calculation result cd actual baud rate error mhz bit/s bit/s 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.00% 8 000 000 38 400 13.02 13 38 461.54 0.16% 12 000 000 38 400 19.53 20 37 500.00 2.40% 12 288 000 38 400 20.00 20 38 400.00 0.00% 385 6062b?atarm?15-nov-05 at91sam9261 the baud rate is calculated with the following formula: the baud rate error is calculated with the following formula. it is not recommended to work with an error higher than 5%. 31.6.1.2 baud rate in synchronous mode if the usart is programmed to operate in sync hronous mode, the selected clock is simply divided by the field cd in us_brgr. in synchronous mode, if the external clock is selected (usclks = 3), the clock is provided directly by the signal on the usart sck pin. no division is active. the value written in us_brgr has no effect. the external clock frequency must be at least 4.5 times lower than the system clock. when either the external clock sck or the inte rnal clock divided (mck/div) is selected, the value programmed in cd must be even if the user has to ensure a 50:50 mark/space ratio on the sck pin. if the internal clock mck is sele cted, the baud rate generator ensures a 50:50 duty cycle on the sck pin, even if the value programmed in cd is odd. 31.6.1.3 baud rate in iso 7816 mode the iso7816 specification defines the bit rate with the following formula: 14 318 180 38 400 23.30 23 38 908.10 1.31% 14 745 600 38 400 24.00 24 38 400.00 0.00% 18 432 000 38 400 30.00 30 38 400.00 0.00% 24 000 000 38 400 39.06 39 38 461.54 0.16% 24 576 000 38 400 40.00 40 38 400.00 0.00% 25 000 000 38 400 40.69 40 38 109.76 0.76% 32 000 000 38 400 52.08 52 38 461.54 0.16% 32 768 000 38 400 53.33 53 38 641.51 0.63% 33 000 000 38 400 53.71 54 38 194.44 0.54% 40 000 000 38 400 65.10 65 38 461.54 0.16% 50 000 000 38 400 81.38 81 38 580.25 0.47% 60 000 000 38 400 97.66 98 38 265.31 0.35% 70 000 000 38 400 113.93 114 38 377.19 0.06% table 31-2. baud rate example (over = 0) (continued) source clock expected baud rate calculation result cd actual baud rate error b audrate mck cd 1 6 ? error 1 expectedbaudrate actualbaudrate -------------------------------------------------- - ?? ?? baudrate selectedclock cd ------------------------------------- - = b di fi ----- - f 386 6062b?atarm?15-nov-05 at91sam9261 where: b is the bit rate di is the bit-rate adjustment factor fi is the clock frequency division factor f is the iso7816 clock frequency (hz) di is a binary value encoded on a 4-bit field, named di, as represented in table 31-3 . fi is a binary value encoded on a 4-bi t field, named fi, as represented in table 31-4 . table 31-5 shows the resulting fi/di ratio, which is the ratio between the iso7816 clock and the baud rate clock. if the usart is configured in iso7816 mode, the clock selected by the usclks field in the mode register (us_mr) is first divided by the value programmed in the field cd in the baud rate generator register (us_brgr). the resulting clock can be provided to the sck pin to feed the smart card clock inputs. this means that the clko bit can be set in us_mr. this clock is then divided by the value programmed in the fi_di_ratio field in the fi_di_ratio register (us_fidi). this is performed by the sampling divider, which performs a division by up to 2047 in iso7816 mode. the non-integer values of the fi/di ratio are not sup- ported and the user must program the fi_di_rati o field to a value as close as possible to the expected value. the fi_di_ratio field resets to the value 0x174 (372 in decimal) and is the most common divider between the iso7816 clock and the bit rate (fi = 372, di = 1). figure 31-4 shows the relation between the elementary time unit, corresponding to a bit time, and the iso 7816 clock. table 31-3. binary and decimal values for d di field 0001 0010 0011 0100 0101 0110 1000 1001 di (decimal)1 2 4 8 163212 20 table 31-4. binary and decimal values for f fi field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 fi (decimal 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048 table 31-5. possible values for the fi/di ratio fi/di 372 558 774 1116 1488 1806 512 768 1024 1536 2048 1 372 558 744 1116 1488 1860 512 768 1024 1536 2048 2 186 279 372 558 744 930 256 384 512 768 1024 4 93 139.5 186 279 372 465 128 192 256 384 512 8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256 16 23.25 34.87 46.5 69.75 93 116.2 32 48 64 96 128 32 11.62 17.43 23.25 34.87 46.5 58.13 16 24 32 48 64 12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6 20 18.6 27.9 37.2 55.8 74.4 93 25.6 38.4 51.2 76.8 102.4 387 6062b?atarm?15-nov-05 at91sam9261 figure 31-4. elementary time unit (etu) 31.6.2 receiver and transmitter control after reset, the receiver is disabled. the user mu st enable the receiver by setting the rxen bit in the control register (us_cr). however, th e receiver registers can be programmed before the receiver clock is enabled. after reset, the transmitter is di sabled. the user must enable it by setting the txen bit in the control register (us_cr). however, the transmitter registers can be programmed before being enabled. the receiver and the transmitter can be enabled together or independently. at any time, the software can perform a reset on the receiver or the transmitter of the usart by setting the corresponding bit, rstrx and rs ttx respectively, in the control register (us_cr). the reset commands have the same effect as a hardware reset on the correspond- ing logic. regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. the user can also independently disable the rece iver or the transmitter by setting rxdis and txdis respectively in us_cr. if the receiver is disabled during a character reception, the usart waits until the end of reception of the current character, then the reception is stopped. if the transmitter is disabled while it is operat ing, the usart waits the end of transmission of both the current character and character being stored in the transmit holding register (us_thr). if a timeguard is programmed, it is handled normally. 31.6.3 synchronous and asynchronous modes 31.6.3.1 transmitter operations the transmitter performs the same in both synchronous and asynchronous operating modes (sync = 0 or sync = 1). one start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the txd pin at each falling edge of the programmed serial clock. the number of data bits is selected by the chrl field and the mode9 bit in the mode regis- ter (us_mr). nine bits are selected by setting the mode 9 bit regardless of the chrl field. the parity bit is set according to the par fiel d in us_mr. the even, odd, space, marked or none parity bit can be configured. the msbf fi eld in us_mr configures which data bit is sent first. if written at 1, the most significant bit is sent first. at 0, the less significant bit is sent first. the number of stop bits is selected by the nbstop field in us_mr. the 1.5 stop bit is sup- ported in asynchronous mode only. 1 etu iso7816 clock on sck iso7816 i/o line on txd fi_di_ratio iso7816 clock cycles 388 6062b?atarm?15-nov-05 at91sam9261 figure 31-5. character transmit the characters are sent by writing in the tr ansmit holding register (us_thr). the transmit- ter reports two status bits in the channel status register (us_csr): txrdy (transmitter ready), which indicates that us_thr is empt y and txempty, which indicates that all the characters written in us_thr have been proces sed. when the current character processing is completed, the last character written in us_thr is transferred into the shift register of the transmitter and us_thr becomes empty, thus txrdy raises. both txrdy and txempty bits are low since the transmitter is disabled. writing a character in us_thr while txrdy is active has no ef fect and the written character is lost. figure 31-6. transmitter status 31.6.3.2 asynchronous receiver if the usart is programmed in asynchronous operating mode (sync = 0), the receiver over- samples the rxd input line. the oversampling is either 16 or 8 times the baud rate clock, depending on the over bit in the mode register (us_mr). the receiver samples the rxd line. if the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bi ts are successively sampled on the bit rate clock. if the oversampling is 16, (over at 0), a start is detected at the eighth sample at 0. then, data bits, parity bit and stop bit are sampled on ea ch 16 sampling clock cycle. if the oversampling is 8 (over at 1), a start bit is detected at the fourth sample at 0. then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. the number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively chrl, mo de9, msbf and par. the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field nbstop, d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit example: 8-bit, parity enabled one stop baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock start bit write us_thr d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit txrdy txempty 389 6062b?atarm?15-nov-05 at91sam9261 so that resynchronization between the receiver and the transmitter can occur. moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchro- nization can also be accomplished when the transmitter is operating with one stop bit. figure 31-7 and figure 31-8 illustrate start detection and character reception when usart operates in asynchronous mode. figure 31-7. asynchronous start detection figure 31-8. asynchronous character reception 31.6.3.3 synchronous receiver in synchronous mode (sync = 1), the receiver samples the rxd signal on each rising edge of the baud rate clock. if a low level is detected, it is considered as a start. all data bits, the par- ity bit and the stop bits are sampled and the receiver waits for the next start bit. synchronous mode operations provide a hi gh speed trans fer capability. configuration fields and bits are the same as in asynchronous mode. figure 31-9 illustrates a character rece ption in synchronous mode. sampling clock (x16) rxd start detection sampling baud rate clock rxd start rejection sampling 12345678 12345670 1234 12345678 9 10111213141516 d0 sampling d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit stop bit example: 8-bit, parity enabled baud rate clock start detection 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 390 6062b?atarm?15-nov-05 at91sam9261 figure 31-9. synchronous mode character reception 31.6.3.4 receiver operations when a character reception is completed, it is transferred to the receive holding register (us_rhr) and the rxrdy bit in the status regi ster (us_csr) rises. if a character is com- pleted while the rxrdy is set, the ovre (overrun error) bit is set. the last character is transferred into us_rhr and overwrites the previ ous one. the ovre bit is cleared by writing the control register (us_cr) with the rststa (reset status) bit at 1. figure 31-10. receiver status d0 d1 d2 d3 d4 d5 d6 d7 rxd start sampling parity bit stop bit example: 8-bit, parity enabled 1 stop baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit parity bit stop bit baud rate clock write us_cr rxrdy ovre d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit rststa = 1 read us_rhr 391 6062b?atarm?15-nov-05 at91sam9261 31.6.3.5 parity the usart supports five parity modes selected by programming the par field in the mode register (us_mr). the par field also enables the multidrop mode, see ?multidrop mode? on page 392 . even and odd parity bit generation and error detection are supported. if even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, a nd at 1 if the number of 1s is odd. accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. if odd parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the samp led parity bit does not correspond. if the mark parity is used, the parity generator of the transmitte r drives the parity bit at 1 for all characters. the receiver parity checker reports an error if the parity bit is sampled at 0. if the space parity is used, the parity generator of the transmitter driv es the parity bit at 0 for all characters. the receiver parity checker reports an error if the parity bit is sampled at 1. if parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. table 31-6 shows an example of the parity bit for the character 0x41 (character ascii ?a?) depending on the configuration of the usart. because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. when the receiver detects a parity error, it sets the pare (parity error) bit in the channel sta- tus register (us_csr). the pare bit can be cleared by writing the control register (us_cr) with the rststa bit at 1. figure 31-11 illustrates the parity bit st atus setting and clearing. table 31-6. parity bit examples character hexa binary parity bit parity mode a 0x41 0100 0001 1 odd a 0x41 0100 0001 0 even a 0x41 0100 0001 1 mark a 0x41 0100 0001 0 space a 0x41 0100 0001 none none 392 6062b?atarm?15-nov-05 at91sam9261 figure 31-11. parity error 31.6.3.6 multidrop mode if the par field in the mode register (us_mr) is programmed to the value 0x6 or 0x07, the usart runs in multidrop mode. this mode differentiates the data characters and the address characters. data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. if the usart is configured in multidrop mode, the receiver sets the pare parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the control register is written with the senda bit at 1. to handle parity error, the pare bit is cleared when the control register is written with the bit rststa at 1. the transmitter sends an address byte (parity bi t set) when senda is written to us_cr. in this case, the next byte written to us_thr is transmitted as an address. any character written in us_thr without having written the command senda is transmitted normally with the parity at 0. 31.6.3.7 transmitter timeguard the timeguard feature enables the usar t interface with slow remote devices. the timeguard function enables the transmitter to insert an idle state on the txd line between two characters. this idle state actually acts as a long stop bit. the duration of the idle state is programmed in the tg field of the transmitter timeguard reg- ister (us_ttgr). when this field is pr ogrammed at zero no timeguard is generated. otherwise, the transmitter holds a high level on txd after each transmitted byte during the number of bit periods programmed in tg in addition to the number of stop bits. as illustrated in figure 31-12 , the behavior of txrdy and txempty status bits is modified by the programming of a timeguard. txrdy rises only when the start bit of the next character is sent, and thus remains at 0 during the timegua rd transmission if a character has been written in us_thr. txempty remains low until the timeguard transmission is completed as the time- guard is part of the current character being transmitted. d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit bad parity bit stop bit baud rate clock write us_cr pare rxrdy rststa = 1 393 6062b?atarm?15-nov-05 at91sam9261 figure 31-12. timeguard operations table 31-7 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the baud rate. 31.6.3.8 receiver time-out the receiver time-out provides support in handling variable-length frames. this feature detects an idle condition on the rxd line. when a time-out is detected, the bit timeout in the channel status register (us_csr) rises and can generate an interrupt, thus indicating to the driver an end of frame. the time-out delay period (during which the receiver waits for a new character) is programmed in the to field of the receiver time-out register (us_rtor). if the to field is programmed at 0, the receiver time-out is disabled and no time-out is detected. the timeout bit in us_csr remains at 0. otherwis e, the receiver loads a 16-bit counter with the value pro- grammed in to. this counter is decremented at each bit period and reloaded each time a new character is received. if the c ounter reaches 0, the timeout bit in the status register rises. the user can either: d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock start bit tg = 4 write us_thr d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit txrdy txempty tg = 4 table 31-7. maximum timeguard length depending on baud rate baud rate bit time timeguard bit/sec s ms 1 200 833 212.50 9 600 104 26.56 14400 69.4 17.71 19200 52.1 13.28 28800 34.7 8.85 33400 29.9 7.63 56000 17.9 4.55 57600 17.4 4.43 115200 8.7 2.21 394 6062b?atarm?15-nov-05 at91sam9261 obtain an interrupt when a time-out is detected after having received at least one character. this is performed by writing the control register (us_cr) with the sttto (start time-out) bit at 1. obtain a periodic interrupt while no characte r is received. this is performed by writing us_cr with the retto (reload and start time-out) bit at 1. if sttto is performed, the counter clock is stopped until a first character is received. the idle state on rxd before the start of the frame does not provide a time-out. this prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on rxd is detected. if retto is performed, the counter starts counting down immediately from the value to. this enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. figure 31-13 shows the block diagram of the receiver time-out feature. figure 31-13. receiver time-out block diagram table 31-8 gives the maximum time-out period for some standard baud rates. 16-bit time-out counter 0 to timeout baud rate clock = character received retto load clock 16-bit value sttto dq 1 clear table 31-8. maximum time-out period baud rate bit time time-out bit/sec s ms 600 1 667 109 225 1 200 833 54 613 2 400 417 27 306 4 800 208 13 653 9 600 104 6 827 14400 69 4 551 19200 52 3 413 28800 35 2 276 33400 30 1 962 56000 18 1 170 57600 17 1 138 200000 5 328 395 6062b?atarm?15-nov-05 at91sam9261 31.6.3.9 framing error the receiver is capable of detecting framing er rors. a framing error happens when the stop bit of a received character is detected at level 0. this can occur if the receiver and the transmitter are fully desynchronized. a framing error is reported on the frame bit of the channel status register (us_csr). the frame bit is asserted in the middle of the stop bi t as soon as the framing error is detected. it is cleared by writing the control regist er (us_cr) with the rststa bit at 1. figure 31-14. framing error status 31.6.3.10 transmit break the user can request the transmitter to generate a break condition on the txd line. a break condition drives the txd line low during at least one complete character. it appears the same as a 0x00 character sent with the parity and the stop bits at 0. however, the transmitter holds the txd line at least during one character until t he user requests the break condition to be removed. a break is transmitted by writing the control regi ster (us_cr) with the sttbrk bit at 1. this can be performed at any time, either while the transmitter is empty (no character in either the shift register or in us_thr) or when a character is being transmitted. if a break is requested while a character is being shifted out, the characte r is first completed before the txd line is held low. once sttbrk command is requested further sttbrk commands are ignored until the end of the break is completed. the break condition is removed by writing us_cr with the stpbrk bit at 1. if the stpbrk is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. the transmitter considers the break as though it is a character, i.e. the sttbrk and stpbrk commands are taken into account only if the txrdy bit in us_csr is at 1 and the start of the break condition clears the txrdy and txempty bits as if a character is processed. writing us_cr with the both sttbrk and stpb rk bits at 1 can lead to an unpredictable result. all stpbrk commands requested without a previous sttbrk command are ignored. a byte written into the transmit holding register while a break is pending, but not started, is ignored. d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit parity bit stop bit baud rate clock write us_cr frame rxrdy rststa = 1 396 6062b?atarm?15-nov-05 at91sam9261 after the break condition, the transmitter returns the txd line to 1 for a minimum of 12 bit times. thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. if the timeguard is programmed with a value higher than 12, the txd line is held high for the timeguard period. after holding the txd line for this period, the transmitter resumes normal operations. figure 31-15 illustrates the effect of both the start break (sttbrk) and stop break (stp- brk) commands on the txd line. figure 31-15. break transmission 31.6.3.11 receive break the receiver detects a break condition when all data, parity and stop bits are low. this corre- sponds to detecting a framing error with data at 0x00, but frame remains low. when the low stop bit is detected, the receiver asserts the rxbrk bit in us_csr. this bit may be cleared by writing the control re gister (us_cr) with the bit rststa at 1. an end of receive break is detected by a high level for at least 2/16 of a bit period in asynchro- nous operating mode or one sample at high level in synchronous operating mode. the end of break detection also asserts the rxbrk bit. 31.6.3.12 hardware handshaking the usart features a hardware handshaking out-of-band flow control. the rts and cts pins are used to connect with the remote device, as shown in figure 31-16 . figure 31-16. connection with a remote device for hardware handshaking setting the usart to operate with hardware handshaking is performed by writing the usart_mode field in the mode register (us_mr) to the value 0x2. d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock write us_cr txrdy txempty stpbrk = 1 sttbrk = 1 break transmission end of break usart txd cts remote device rxd txd rxd rts rts cts 397 6062b?atarm?15-nov-05 at91sam9261 the usart behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, exce pt that the receiver drives the rts pin as described below and the level on the cts pin modifies the behavior of the transmitter as described below. using this mode requires using the pdc channel for reception. the transmit- ter can handle hardware handshaking in any case. figure 31-17 shows how the receiver operates if ha rdware handshaking is enabled. the rts pin is driven high if the receiver is disabled and if the status rxbuff (receive buffer full) coming from the pdc channel is high. normally, the remote device does not start transmitting while its cts pin (driven by rts) is high. as soon as the receiver is enabled, the rts falls, indicating to the remote device that it can start transmitting. defining a new buffer to the pdc clears the status bit rxbuff and, as a result, asserts the pin rts low. figure 31-17. receiver behavior when operating with hardware handshaking figure 31-18 shows how the transmitter operates if hardware handshaking is enabled. the cts pin disables the transmitter. if a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character hap- pens as soon as the pin cts falls. figure 31-18. transmitter behavior when operating with hardware handshaking 31.6.4 iso7816 mode the usart features an iso7816-compatible operating mode. this mode permits interfacing with smart cards and security access modules (sam) communicating through an iso7816 link. both t = 0 and t = 1 protocols defined by the iso7816 specification are supported. setting the usart in iso7816 mode is performed by writing the usart_mode field in the mode register (us_mr) to the value 0x4 for protocol t = 0 and to the value 0x5 for protocol t = 1. 31.6.4.1 iso7816 mode overview the iso7816 is a half duplex communication on only one bidirectional line. the baud rate is determined by a division of the clock provided to the remote device (see ?baud rate genera- tor? on page 383 ). the usart connects to a smart card as shown in figure 31-19 . the txd line becomes bidi- rectional and the baud rate generator feeds the iso7816 clock on the sck pin. as the txd pin becomes bidirectional, its output remains dr iven by the output of the transmitter but only rts rxbuff write us_cr rxen = 1 rxd rxdis = 1 cts txd 398 6062b?atarm?15-nov-05 at91sam9261 when the transmitter is active wh ile its input is directed to the input of the receiver. the usart is considered as the master of the communication as it generates the clock. figure 31-19. connection of a smart card to the usart when operating in iso7816, either in t = 0 or t = 1 modes, the character format is fixed. the configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values pro- grammed in the chrl, mode9, par and chmo de fields. msbf can be used to transmit lsb or msb first. the usart cannot operate concurrently in both receiver and transmitter modes as the com- munication is unidirectional at a time. it has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. enabling both the receiver and the transmitter at the same time in iso7816 mode may lead to unpredictable results. the iso7816 specification defines an inverse trans mission format. data bits of the character must be transmitted on the i/o line at their negative value. the usart does not support this format and the user has to perform an exclusive or on the data before writing it in the trans- mit holding register (us_thr) or after reading it in the receive hold ing register (us_rhr). 31.6.4.2 protocol t = 0 in t = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. the transmitter shifts out the bits and does not drive the i/o line during the guard time. if no parity error is detected, the i/o line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in figure 31-20 . if a parity error is detected by the receiver, it drives the i/o line at 0 during the guard time, as shown in figure 31-21 . this error bit is also named nack, for non acknowledge. in this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. when the usart is the receiver and it detects an error, it does not load the erroneous charac- ter in the receive holding register (us_rhr). it appropriately sets the pare bit in the status register (us_sr) so that the software can handle the error. figure 31-20. t = 0 protocol without parity error smart card sck clk txd i/o usart d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit baud rate clock start bit guard time 1 next start bit guard time 2 399 6062b?atarm?15-nov-05 at91sam9261 figure 31-21. t = 0 protocol with parity error receive error counter the usart receiver also records the total number of errors. this can be read in the number of error (us_ner) register. the nb_errors field can record up to 255 errors. reading us_ner automatically clears the nb_errors field. receive nack inhibit the usart can also be configur ed to inhibit an error. this can be achieved by setting the inack bit in the mode register (us_mr). if inack is at 1, no error signal is driven on the i/o line even if a parity bit is detected, but the inac k bit is set in the status register (us_sr). the inack bit can be cleared by writing the control register (us_cr) with the rstnack bit at 1. moreover, if inack is set, the erroneous received character is stored in the receive holding register, as if no error occurred. however, the rxrdy bit does not raise. transmit character repetition when the usart is transmitting a character and gets a nack, it can automatically repeat the character before moving on to the next one. repetition is enabled by writing the max_iteration field in the mode register (us_mr) at a value higher than 0. each charac- ter can be transmitted up to eight times; the first transmission plus seven repetitions. if max_iteration does not equal zero, the u sart repeats the character as many times as the value loaded in max_iteration. when the usart repetition number reaches m ax_iteration, the iterat ion bit is set in the channel status register (us_csr). if the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. the iteration bit in us_csr can be cleared by writing the control register with the rsit bit at 1. disable successive receive nack the receiver can limit the number of successive nacks sent back to the remote transmitter. this is programmed by setting the bit dsnack in the mode register (us_mr). the maximum number of nack transmitted is programmed in the max_iteration field. as soon as max_iteration is reached, the character is cons idered as correct, an acknowledge is sent on the line and the iteration bit in the channel status register is set. 31.6.4.3 protocol t = 1 when operating in iso7816 protocol t = 1, the transmission is similar to an asynchronous for- mat with only one stop bit. the parity is generated when transmitting and checked when receiving. parity error detection sets the pare bit in the channel status register (us_csr). d0 d1 d2 d3 d4 d5 d6 d7 i/o parity bit baud rate clock start bit guard time 1 start bit guard time 2 d0 d1 error repetition 400 6062b?atarm?15-nov-05 at91sam9261 31.6.5 irda mode the usart features an irda mode supplying half-duplex point-to-point wireless communica- tion. it embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in figure 31-22 . the modulator and demodulator are compli- ant with the irda specification version 1.1 and support data transfer speeds ranging from 2.4 kb/s to 115.2 kb/s. the usart irda mode is enabled by setting t he usart_mode field in the mode register (us_mr) to the value 0x8. the irda filter register (us_if) allows configuring the demodula- tor filter. the usart transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. note that the modulator and the demodulator are activated. figure 31-22. connection to irda transceivers the receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. 31.6.5.1 irda modulation for baud rates up to and including 115.2 kbits/sec, the rzi modulation scheme is used. ?0? is represented by a light pulse of 3/16th of a bit time. some examples of signal pulse duration are shown in table 31-9 . figure 31-23 shows an example of character transmission. irda transceivers rxd rx txd tx usart demodulator modulator receiver transmitter table 31-9. irda pulse duration baud rate pulse duration (3/16) 2.4 kb/s 78.13 s 9.6 kb/s 19.53 s 19.2 kb/s 9.77 s 38.4 kb/s 4.88 s 57.6 kb/s 3.26 s 115.2 kb/s 1.63 s 401 6062b?atarm?15-nov-05 at91sam9261 figure 31-23. irda modulation 31.6.5.2 irda baud rate table 31-10 gives some examples of cd values, baud rate error and pulse duration. note that the requirement on the maximum acceptable error of 1.87% must be met. bit period bit period 3 16 start bit data bits stop bit 0 0 0 0 0 1 1 1 1 1 transmitter output txd table 31-10. irda baud rate error peripheral clock baud rate cd baud rate error pulse time 3 686 400 115 200 2 0.00% 1.63 20 000 000 115 200 11 1.38% 1.63 32 768 000 115 200 18 1.25% 1.63 40 000 000 115 200 22 1.38% 1.63 3 686 400 57 600 4 0.00% 3.26 20 000 000 57 600 22 1.38% 3.26 32 768 000 57 600 36 1.25% 3.26 40 000 000 57 600 43 0.93% 3.26 3 686 400 38 400 6 0.00% 4.88 20 000 000 38 400 33 1.38% 4.88 32 768 000 38 400 53 0.63% 4.88 40 000 000 38 400 65 0.16% 4.88 3 686 400 19 200 12 0.00% 9.77 20 000 000 19 200 65 0.16% 9.77 32 768 000 19 200 107 0.31% 9.77 40 000 000 19 200 130 0.16% 9.77 3 686 400 9 600 24 0.00% 19.53 20 000 000 9 600 130 0.16% 19.53 32 768 000 9 600 213 0.16% 19.53 40 000 000 9 600 260 0.16% 19.53 3 686 400 2 400 96 0.00% 78.13 20 000 000 2 400 521 0.03% 78.13 32 768 000 2 400 853 0.04% 78.13 402 6062b?atarm?15-nov-05 at91sam9261 31.6.5.3 irda demodulator the demodulator is based on the irda receive filter comprised of an 8-bit down counter which is loaded with the value progra mmed in us_if. when a falling e dge is detected on the rxd pin, the filter counter starts counting down at the master clock (mck) speed. if a rising edge is detected on the rxd pin, the counter stops and is reloaded with us_if. if no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. figure 31-24 illustrates the operations of the irda demodulator. figure 31-24. irda demodulator operations as the irda mode uses the same logic as the iso7816, note that the fi_di_ratio field in us_fidi must be set to a value higher than 0 in order to assure irda communications operate correctly. mck rxd receiver input pulse rejected 65432 6 1 driven low during 16 baud rate clock cycles 65432 0 pulse accepted counter value 403 6062b?atarm?15-nov-05 at91sam9261 31.6.6 rs485 mode the usart features the rs485 mode to enable line driver control. while operating in rs485 mode, the usart behaves as though in asynchronous or synchronous mode and configura- tion of all the parameters is possible. the differenc e is that the rts pin is driven high when the transmitter is operating. the behavior of the rts pin is controlled by the txempty bit. a typ- ical connection of the usart to a rs485 bus is shown in figure 31-25 . figure 31-25. typical connection to a rs485 bus the usart is set in rs485 mode by programm ing the usart_mode field in the mode reg- ister (us_mr) to the value 0x1. the rts pin is at a level inverse to the txempty bit. significantly, the rts pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion. figure 31-26 gives an example of the rts waveform during a character transmis- sion when the timeguard is enabled. figure 31-26. example of rts drive with timeguard usart rts txd rxd differential bus d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock tg = 4 write us_thr txrdy txempty rts 404 6062b?atarm?15-nov-05 at91sam9261 31.6.7 test modes the usart can be programmed to operate in three different test modes. the internal loop- back capability allows on-board diagnostics. in the loopback mode the usart interface pins are disconnected or not and reconfigured for loopback internally or externally. 31.6.7.1 normal mode normal mode connects the rxd pin on the receiver input and the transmitter output on the txd pin. figure 31-27. normal mode configuration 31.6.7.2 automatic echo mode automatic echo mode allows bit-by-bit retransmission. when a bit is received on the rxd pin, it is sent to the txd pin, as shown in figure 31-28 . programming the transmitter has no effect on the txd pin. the rxd pin is still connected to the receiver input, thus the receiver remains active. figure 31-28. automatic echo mode configuration 31.6.7.3 local loopback mode local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in figure 31-29 . the txd and rxd pins are not used. the rxd pin has no effect on the receiver and the txd pin is continuously driven high, as in idle state. figure 31-29. local loopback mode configuration receiver transmitter rxd txd receiver transmitter rxd txd receiver transmitter rxd txd 1 405 6062b?atarm?15-nov-05 at91sam9261 31.6.7.4 remote loopback mode remote loopback mode directly connects the rxd pin to the txd pin, as shown in figure 31- 30 . the transmitter and the receiver are disabled an d have no effect. this mode allows bit-by- bit retransmission. figure 31-30. remote loopback mode configuration receiver transmitter rxd txd 1 406 6062b?atarm?15-nov-05 at91sam9261 31.7 usart user interface table 31-11. usart memory map offset register name access reset state 0x0000 control register us_cr write-only ? 0x0004 mode register us_mr read/write ? 0x0008 interrupt enable register us_ier write-only ? 0x000c interrupt disable register us_idr write-only ? 0x0010 interrupt mask register us_imr read-only 0x0 0x0014 channel status register us_csr read-only ? 0x0018 receiver holding register us_rhr read-only 0x0 0x001c transmitter holding register us_thr write-only ? 0x0020 baud rate generator register us_brgr read/write 0x0 0x0024 receiver time-out register us_rtor read/write 0x0 0x0028 transmitter timeguard register us_ttgr read/write 0x0 0x2c - 0x3c reserved ? ? ? 0x0040 fi di ratio register us_fidi read/write 0x174 0x0044 number of errors register us_ner read-only ? 0x0048 reserved ? ? ? 0x004c irda filter register us_if read/write 0x0 0x5c - 0xfc reserved ? ? ? 0x100 - 0x128 reserved for pdc registers ? ? ? 407 6062b?atarm?15-nov-05 at91sam9261 31.7.1 usart control register name: us_cr access type: write-only rstrx: reset receiver 0: no effect. 1: resets the receiver. rsttx: reset transmitter 0: no effect. 1: resets the transmitter. rxen: receiver enable 0: no effect. 1: enables the receiver, if rxdis is 0. rxdis: receiver disable 0: no effect. 1: disables the receiver. txen: transmitter enable 0: no effect. 1: enables the transmitter if txdis is 0. txdis: transmitter disable 0: no effect. 1: disables the transmitter. rststa: reset status bits 0: no effect. 1: resets the status bits pare, frame, ovre and rxbrk in the us_csr. sttbrk: start break 0: no effect. 1: starts transmission of a break after the characters present in us_thr and the transmit shi ft register have been trans- mitted. no effect if a break is already being transmitted. stpbrk: stop break 0: no effect. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????rtsdisrtsen?? 15 14 13 12 11 10 9 8 retto rstnack rstit senda sttto stpbrk sttbrk rststa 76543210 txdis txen rxdis rxen rsttx rstrx ? ? 408 6062b?atarm?15-nov-05 at91sam9261 1: stops transmission of the break after a minimum of one char acter length and transmits a high level during 12-bit periods. no effect if no break is being transmitted. sttto: start time-out 0: no effect 1: starts waiting for a character before clocking the time-out counter. senda: send address 0: no effect. 1: in multidrop mode only, the next character written to the us_thr is sent with the address bit set. rstit: reset iterations 0: no effect. 1: resets iteration in us_csr. no e ffect if the iso7816 is not enabled. rstnack: reset non acknowledge 0: no effect 1: resets nack in us_csr. retto: rearm time-out 0: no effect 1: restart time-out rtsen: request to send enable 0: no effect. 1: drives the pin rts to 0. rtsdis: request to send disable 0: no effect. 1: drives the pin rts to 1. 409 6062b?atarm?15-nov-05 at91sam9261 31.7.2 usart mode register name: us_mr access type: read/write usart_mode usclks: clock selection 31 30 29 28 27 26 25 24 ? ? ? filter ? max_iteration 23 22 21 20 19 18 17 16 ? ? dsnack inack over clko mode9 msbf 15 14 13 12 11 10 9 8 chmode nbstop par sync 76543210 chrl usclks usart_mode usart_mode mode of the usart 0000normal 0001rs485 0 0 1 0 hardware handshaking 0011reserved 0 1 0 0 is07816 protocol: t = 0 0101reserved 0 1 1 0 is07816 protocol: t = 1 0111reserved 1000irda 11xxreserved usclks selected clock 00mck 01mck / div 10reserved 11sck 410 6062b?atarm?15-nov-05 at91sam9261 chrl: character length. sync: synchronous mode select 0: usart operates in asynchronous mode. 1: usart operates in synchronous mode. par: parity type nbstop: number of stop bits chmode: channel mode msbf: bit order 0: least significant bit is sent/received first. 1: most significant bit is sent/received first. chrl character length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits par parity type 0 0 0 even parity 001odd parity 0 1 0 parity forced to 0 (space) 0 1 1 parity forced to 1 (mark) 1 0 x no parity 1 1 x multidrop mode nbstop asynchronous (sync = 0) synchronous (sync = 1) 0 0 1 stop bit 1 stop bit 0 1 1.5 stop bits reserved 1 0 2 stop bits 2 stop bits 1 1 reserved reserved chmode mode description 0 0 normal mode 0 1 automatic echo. receiver input is connected to the txd pin. 1 0 local loopback. transmitter output is connected to the receiver input.. 1 1 remote loopback. rxd pin is internally connected to the txd pin. 411 6062b?atarm?15-nov-05 at91sam9261 mode9: 9-bit character length 0: chrl defines character length. 1: 9-bit character length. cklo: clock output select 0: the usart does not drive the sck pin. 1: the usart drives the sck pin if usclks does not select the external clock sck. over: oversampling mode 0: 16x oversampling. 1: 8x oversampling. inack: inhibit non acknowledge 0: the nack is generated. 1: the nack is not generated. dsnack: disable successive nack 0: nack is sent on the iso line as soon as a parity erro r occurs in the received character (unless inack is set). 1: successive parity errors are counted up to the value spec ified in the max_iteration field. these parity errors gener- ate a nack on the iso line. as soon as this value is reac hed, no additional nack is sent on the iso line. the flag iteration is asserted. max_iteration defines the maximum number of iterations in mode iso7816, protocol t= 0. filter: infrared receive line filter 0: the usart does not filter the receive line. 1: the usart filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority). 412 6062b?atarm?15-nov-05 at91sam9261 31.7.3 usart interrupt enable register name: us_ier access type: write-only rxrdy: rxrdy interrupt enable txrdy: txrdy interrupt enable rxbrk: receiver break interrupt enable endrx: end of receive transfer interrupt enable endtx: end of transmit interrupt enable ovre: overrun error interrupt enable frame: framing error interrupt enable pare: parity error interrupt enable timeout: time-out interrupt enable txempty: txempty interrupt enable iteration: iteration interrupt enable txbufe: buffer empty interrupt enable rxbuff: buffer full interrupt enable nack: non acknowledge interrupt enable ctsic: clear to send input change interrupt enable mane: manchester error interrupt enable 0: no effect. 1: enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? mane ctsic ? ? ? 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iteration txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy 413 6062b?atarm?15-nov-05 at91sam9261 31.7.4 usart interrupt disable register name: us_idr access type: write-only rxrdy: rxrdy interrupt disable txrdy: txrdy interrupt disable rxbrk: receiver bre ak interrupt disable endrx: end of receive transfer interrupt disable endtx: end of transmit interrupt disable ovre: overrun error interrupt disable frame: framing error interrupt disable pare: parity error interrupt disable timeout: time-out interrupt disable txempty: txempty interrupt disable iteration: iteration interrupt disable txbufe: buffer empty interrupt disable rxbuff: buffer full interrupt disable nack: non acknowledge interrupt disable ctsic: clear to send input change interrupt disable 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????ctsic ? ? ? 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iteration txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy 414 6062b?atarm?15-nov-05 at91sam9261 31.7.5 usart interrupt mask register name: us_imr access type: read-only rxrdy: rxrdy interrupt mask txrdy: txrdy interrupt mask rxbrk: receiver break interrupt mask endrx: end of receive transfer interrupt mask endtx: end of transmit interrupt mask ovre: overrun error interrupt mask frame: framing error interrupt mask pare: parity error interrupt mask timeout: time-out interrupt mask txempty: txempty interrupt mask iteration: iteration interrupt mask txbufe: buffer empty interrupt mask rxbuff: buffer full interrupt mask nack: non acknowledge interrupt mask ctsic: clear to send input change interrupt mask 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????ctsic ? ? ? 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iteration txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy 415 6062b?atarm?15-nov-05 at91sam9261 31.7.6 usart channel status register name: us_csr access type: read-only rxrdy: receiver ready 0: no complete character has been received since the last read of us_rhr or the receiver is disabled. if characters were being received when the receiver was disabled, rx rdy changes to 1 when the receiver is enabled. 1: at least one complete char acter has been rece ived and us_rhr has not yet been read. txrdy: transmitter ready 0: a character is in the us_thr waiting to be transferred to the transmit shift register, or an sttbrk command has been requested, or the transmitter is disabled. as soon as the transmitter is enabled, txrdy becomes 1. 1: there is no char acter in the us_thr. rxbrk: break received/end of break 0: no break received or end of break detected since the last rststa. 1: break received or end of break detected since the last rststa. endrx: end of receiver transfer 0: the end of transfer signal from the receive pdc channel is inactive. 1: the end of transfer signal from the receive pdc channel is active. endtx: end of transmitter transfer 0: the end of transfer signal from the transmit pdc channel is inactive. 1: the end of transfer signal from the transmit pdc channel is active. ovre: overrun error 0: no overrun error has occurred since the last rststa. 1: at least one overrun error has occurred since the last rststa. frame: framing error 0: no stop bit has been detected low since the last rststa. 1: at least one stop bit has been detected low since the last rststa. pare: parity error 0: no parity error has been detected since the last rststa. 1: at least one parity error has been detected since the last rststa. timeout: receiver time-out 0: there has not been a time-out since the last start time-out command or the time-out register is 0. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 cts ? ? ? ctsic ? ? ? 15 14 13 12 11 10 9 8 ? ? nack rxbuff txbufe iteration txempty timeout 76543210 pare frame ovre endtx endrx rxbrk txrdy rxrdy 416 6062b?atarm?15-nov-05 at91sam9261 1: there has been a time-out since the last start time-out command. txempty: transmitter empty 0: there are characters in either us_thr or the tr ansmit shift register, or the transmitter is disabled. 1: there is at least one character in either us_thr or the transmit shift register. iteration: max number of repetitions reached 0: maximum number of repetitions has not been reached since the last rsit. 1: maximum number of repetitions has been reached since the last rsit. txbufe: transmission buffer empty 0: the signal buffer empty from the transmit pdc channel is inactive. 1: the signal buffer empty from the transmit pdc channel is active. rxbuff: reception buffer full 0: the signal buffer full from the receive pdc channel is inactive. 1: the signal buffer full from th e receive pdc channel is active. nack: non acknowledge 0: no non acknowledge has not been detected since the last rstnack. 1: at least one non acknowledge has been detected since the last rstnack. ctsic: clear to send input change flag 0: no input change has been detected on the cts pin since the last read of us_csr. 1: at least one input change has been detected on the cts pin since the last read of us_csr. cts: image of cts input 0: cts is at 0. 1: cts is at 1. 417 6062b?atarm?15-nov-05 at91sam9261 31.7.7 usart receive holding register name: us_rhr access type: read-only rxchr: received character last character received if rxrdy is set. rxsynh: received sync 0: last character received is a data. 1: last character received is a command. 31.7.8 usart transmit holding register name: us_thr access type: write-only txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. txsynh: sync field to be transmitted 0: the next character sent is encoded as a data. start frame delimiter is data sync. 1: the next character sent is encoded as a command. start frame delimiter is command sync. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rxsynh ??????rxchr 76543210 rxchr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 txsynh ??????txchr 76543210 txchr 418 6062b?atarm?15-nov-05 at91sam9261 31.7.9 usart baud rate generator register name: us_brgr access type: read/write cd: clock divider 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????? ? 15 14 13 12 11 10 9 8 cd 76543210 cd cd usart_mode iso7816 usart_mode = iso7816 sync = 0 sync = 1 over = 0 over = 1 0 baud rate clock disabled 1 to 65535 baud rate = selected clock/16/cd baud rate = selected clock/8/cd baud rate = selected clock /cd baud rate = selected clock/cd/fi_di_ratio 419 6062b?atarm?15-nov-05 at91sam9261 31.7.10 usart receiver time-out register name: us_rtor access type: read/write to: time-out value 0: the receiver time-out is disabled. 1 - 65535: the receiver time-out is enabled and the time-out delay is to x bit period. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 to 76543210 to 420 6062b?atarm?15-nov-05 at91sam9261 31.7.11 usart transmitter timeguard register name: us_ttgr access type: read/write tg: timeguard value 0: the transmitter timeguard is disabled. 1 - 255: the transmitter timeguard is enabled and the timeguard delay is tg x bit period. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 tg 421 6062b?atarm?15-nov-05 at91sam9261 31.7.12 usart fi di ratio register name: us_fidi access type: read/write reset value : 0x174 fi_di_ratio: fi over di ratio value 0: if iso7816 mode is selected, the baud rate generator generates no signal. 1 - 2047: if iso7816 mode is selected, the baud rate is the clock provided on sck divided by fi_di_ratio. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????? fi_di_ratio 76543210 fi_di_ratio 422 6062b?atarm?15-nov-05 at91sam9261 31.7.13 usart number of errors register name: us_ner access type: read-only nb_errors: number of errors total number of errors that occurred during an iso7816 transfer. this register automatically clears when read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 nb_errors 423 6062b?atarm?15-nov-05 at91sam9261 31.7.14 usart irda filter register name: us_if access type: read/write irda_filter: irda filter sets the filter of the irda demodulator. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 irda_filter 424 6062b?atarm?15-nov-05 at91sam9261 32. synchronous serial controller (ssc) 32.1 overview the atmel synchronous serial controller (ssc) provides a synchronous communication link with external devices. it supports many serial synchronous communication protocols generally used in audio and telecom applications such as i2s, short frame sync, long frame sync, etc. the ssc contains an independent receiver and transmitter and a common clock divider. the receiver and the transmitter each interface with three signals: the td/rd signal for data, the tk/rk signal for the clock and the tf/rf signal for the frame sync. the transfers can be pro- grammed to start automatically or on different events detected on the frame sync signal. the ssc?s high-level of progra mmability and its two dedicated pdc channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention. featuring connection to two pdc channels, the ssc permits interfacing with low processor overhead to the following: codec?s in master or slave mode dac through dedicated serial interface, particularly i2s magnetic card reader 425 6062b?atarm?15-nov-05 at91sam9261 32.2 block diagram figure 32-1. block diagram 32.3 application block diagram figure 32-2. application block diagram ssc interface pio pdc apb bridge mck asb apb tf tk td rf rk rd interrupt control ssc interrupt pmc interrupt management power management test management ssc serial audio os or rtos driver codec frame management line interface time slot management 426 6062b?atarm?15-nov-05 at91sam9261 32.4 pin name list 32.5 product dependencies 32.5.1 i/o lines the pins used for interfacing the compliant ex ternal devices may be multiplexed with pio lines. before using the ssc receiver, the pio controller must be configured to dedicate the ssc receiver i/o lines to the ssc peripheral mode. before using the ssc transmitter, the pio contro ller must be configured to dedicate the ssc transmitter i/o lines to the ssc peripheral mode. 32.5.2 power management the ssc is not continuously clocked. the ssc interface may be clocked through the power management controller (pmc), therefore the programmer must first configure the pmc to enable the ssc clock. 32.5.3 interrupt the ssc interface has an interrupt line connected to the advanced interrupt controller (aic). handling interrupts requires programming the aic before configuring the ssc. all ssc interrupts can be enabled/disabled conf iguring the ssc interrupt mask register. each pending and unmasked ssc interr upt will assert the ssc interrupt line. th e ssc interrupt ser- vice routine can get the interrupt origin by reading the ssc interrupt status register. 32.6 functional description this chapter contains the functional description of the following: ssc functional block, clock management, data format, start, transmitter, receiver and frame sync. the receiver and transmitter operate separately. however, they can work synchronously by programming the receiver to use the transmit cloc k and/or to start a data transfer when trans- mission starts. alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. the transmitter and the receiver can be programmed to operate with the clo ck signals provided on either the tk or rk pins. this allows the ssc to support many slave-mode data transfers. the maximum clock speed allowed on the tk and rk pins is the master clock divided by 2. table 32-1. i/o lines description pin name pin description type rf receiver frame synchro input/output rk receiver clock input/output rd receiver data input tf transmitter frame synchro input/output tk transmitter clock input/output td transmitter data output 427 6062b?atarm?15-nov-05 at91sam9261 figure 32-3. ssc functional block diagram 32.6.1 clock management the transmitter clock can be generated by: an external clock received on the tk i/o pad the receiver clock the internal clock divider the receiver clock can be generated by: an external clock received on the rk i/o pad the transmitter clock the internal clock divider furthermore, the transmitter block can generate an external clock on the tk i/o pad, and the receiver block can generate an external clock on the rk i/o pad. this allows the ssc to support many master and slave mode data transfers. interrupt control aic user interface apb mck receive clock controller start selector tx clock rk input rf tf clock output controller frame sync controller transmit clock controller transmit shift register start selector transmit sync holding register transmit holding register load shift rx clock tx clock tk input tf tx pdc rf rd rf rk clock output controller frame sync controller receive shift register receive sync holding register receive holding register load shift td tf tk rx clock rx pdc receiver pdc transmitter clock divider 428 6062b?atarm?15-nov-05 at91sam9261 32.6.1.1 clock divider figure 32-4. divided clock block diagram the master clock divider is determined by the 12-bit field div counter and comparator (so its maximal value is 4095) in the clock mode regi ster ssc_cmr, allowing a master clock divi- sion by up to 8190. the divided clock is provided to both the receiver and transmitter. when this field is programmed to 0, the clock divider is not used an d remains inactive. when div is set to a value equal to or greater than 1, the divided clock has a frequency of master clock divided by 2 times div. each level of the divided clock has a duration of the master clock multiplied by div. this ensures a 50% duty cycle for the divided clock regard- less of whether the div value is even or odd. figure 32-5. divided clock generation 32.6.1.2 transmitter clock management the transmitter clock is generated from the receiv er clock or the divider clock or an external clock scanned on the tk i/o pad. the transmitte r clock is selected by the cks field in ssc_tcmr (transmit clock mode register). transmit clock can be inverted independently by the cki bits in ssc_tcmr. the transmitter can also drive the tk i/o pad continuously or be limited to the actual data transfer. the clock output is configured by the ssc_tcmr register. the transmit clock inver- sion (cki) bits have no effect on the clock outputs. programming the tcmr register to select mck divided clock clock divider / 2 12-bit counter ssc_cmr master clock divided clock div = 1 master clock divided clock div = 3 divided clock frequency = mck/2 divided clock frequency = mck/6 table 32-2. maximum minimum mck / 2 mck / 8190 429 6062b?atarm?15-nov-05 at91sam9261 tk pin (cks field) and at the same time contin uous transmit clock (cko field) might lead to unpredictable results. figure 32-6. transmitter clock management 32.6.1.3 receiver clock management the receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the rk i/o pad. the receive clock is selected by the cks field in ssc_rcmr (receive clock mode register). receive clocks can be inverted independently by the cki bits in ssc_rcmr. the receiver can also drive the rk i/o pad continuously or be limited to the actual data trans- fer. the clock output is configured by the ss c_rcmr register. the receive clock inversion (cki) bits have no effect on the clock outputs. programming the rcmr register to select rk pin (cks field) and at the same time continuous receive clock (cko field) can lead to unpre- dictable results. figure 32-7. receiver clock management tk (pin) receiver clock divider clock cks cko data transfer cki ckg transmitter clock clock output mux tri_state controller tri-state controller inv mux rk (pin) transmitter clock divider clock cks cko data transfer cki ckg receiver clock clock output mux tri-state controller tri-state controller inv mux 430 6062b?atarm?15-nov-05 at91sam9261 32.6.1.4 serial clock ratio considerations the transmitter and the receiver can be programmed to operate with the clock signals pro- vided on either the tk or rk pins. this allo ws the ssc to support many slave-mode data transfers. in this case, the maximum clock speed allowed on the rk pin is: ? master clock divided by 2 if receiver frame synchro is input ? master clock divided by 3 if receiver frame synchro is output in addition, the maximum clock s peed allowed on the tk pin is: ? master clock divided by 6 if transmit frame synchro is input ? master clock divided by 2 if transmit frame synchro is output 32.6.2 transmitter operations a transmitted frame is triggered by a start even t and can be followed by synchronization data before data transmission. the start event is configured by setting the transmit clock mode register (ssc_tcmr). see ?start? on page 431. the frame synchronization is configured setting the transmit frame mode register (ssc_tfmr). see ?frame sync? on page 433. to transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in the ssc_tcmr. data is written by the application to the ssc_thr register then transferred to the shift register according to the data format selected. when both the ssc_thr and the transmit shift register are empty, the status flag txempty is set in ssc_sr. when the transmit holding regi ster is transferred in the transmit shift reg- ister, the status flag txrdy is set in ssc_sr and additional data can be loaded in the holding register. figure 32-8. transmitter block diagram transmit shift register start selector ssc_tshr ssc_thr transmitter clock td ssc_tfmr.fslen ssc_tfmr.datlen ssc_cr.txen ssc_cr.txdis ssc_tcmr.sttdly ssc_tfmr.fsden ssc_tfmr.datnb ssc_sr.txen ssc_tfmr.datdef ssc_tfmr.msbf ssc_tcmr.sttdly ssc_tfmr.fsden 0 1 1 0 rf tf 431 6062b?atarm?15-nov-05 at91sam9261 32.6.3 receiver operations a received frame is triggered by a start event and can be followed by synchronization data before data transmission. the start event is configured setting the receive clock mode register (ssc_rcmr). see ?start? on page 431. the frame synchronization is configured setting the receive frame mode register (ssc_rfmr). see ?frame sync? on page 433. the receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the ssc_rcmr. the data is transferred from the shift register depending on the data format selected. when the receiver shift register is full, the ssc transfers this data in the holding register, the status flag rxrdy is set in ssc_sr and the data can be read in the receiver holding register. if another transfer occurs before read of the rh r register, the status flag overun is set in ssc_sr and the receiver shift register is transferred in the rhr register. figure 32-9. receiver block diagram 32.6.4 start the transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the transmit start se lection (start) field of ssc_tcmr and in the receive start selection (start) field of ssc_rcmr. under the following conditions the start event is independently programmable: continuous. in this case, the transmission starts as soon as a word is written in ssc_thr and the reception starts as soon as the receiver is enabled. synchronously with the transmitter/receiver on detection of a falling/rising edge on tf/rf on detection of a low level/high level on tf/rf on detection of a level change or an edge on tf/rf receive shift register start selector ssc_rhr ssc_rshr receiver clock rd ssc_rfmr.fslen ssc_rfmr.datlen rf ssc_cr.rxen ssc_cr.rxdis ssc_sr.rxen ssc_rfmr.msbf ssc_rcmr.sttdly ssc_rfmr.datnb tf 432 6062b?atarm?15-nov-05 at91sam9261 a start can be programmed in the same manner on either side of the transmit/receive clock register (rcmr/tcmr). thus, the start coul d be on tf (transmit) or rf (receive). moreover, the receiver can start when data is detected in the bit stream with the compare functions. detection on tf/rf input/output is done by the field fsos of the transmit/receive frame mode register (tfmr/rfmr). figure 32-10. transmit start mode figure 32-11. receive pulse/ed ge start modes x tk tf (input) td (output) td (output) td (output) td (output) td (output) td (output) xbob1 x bo b1 bo b1 bo b1 bo b1 bo b1 bo b1 b1 bo x x x sttdly sttdly sttdly sttdly sttdly sttdly start = falling edge on tf start = rising edge on tf start = low level on tf start = high level on tf start = any edge on tf start = level change on tf x rk rf (input) rd (input) rd (input) rd (input) rd (input) rd (input) rd (input) xbob1 x bo b1 bo b1 bo b1 bo b1 bo b1 bo b1 b1 bo x x x sttdly sttdly sttdly sttdly sttdly sttdly start = falling edge on rf start = rising edge on rf start = low level on rf start = high level on rf start = any edge on rf start = level change on rf 433 6062b?atarm?15-nov-05 at91sam9261 32.6.5 frame sync the transmitter and receiver frame sync pins, tf and rf, can be programmed to generate different kinds of frame synchronization signals. the frame sync output selection (fsos) field in the receive frame mode register (ssc_rfmr) and in the transmit frame mode register (ssc_tfmr) are used to select the required waveform. programmable low or high levels during data transfer are supported. programmable high levels before the start of data transfers or toggling are also supported. if a pulse waveform is selected, the frame sync length (fslen) field in ssc_rfmr and ssc_tfmr programs the length of the pulse, from 1 bit time up to 16 bit time. the periodicity of the receive and transmit frame sync pulse output can be programmed through the period divider selection ( period) field in ssc_rcmr and ssc_tcmr. 32.6.5.1 frame sync data frame sync data transmits or receives a specific tag during the frame sync signal. during the frame sync signal, the receiver can sample the rd line and store the data in the receive sync holding register and the transmit ter can transfer transmit sync holding regis- ter in the shifter register. the data length to be sampled/shifted out during the frame sync signal is programmed by the fslen field in ssc_rfmr/ssc_tfmr. concerning the receive frame sync data operation, if the frame sync length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the receive sync holding register through the receive shift register. the transmit frame sync operation is performed by the transmitter only if the bit frame sync data enable (fsden) in ssc_tfmr is set. if the frame sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the transmit sync holding register is transferred in the transmit register, then shifted out. 32.6.5.2 frame sync edge detection the frame sync edge detection is programmed by the fsedge field in ssc_rfmr/ssc_tfmr. this sets the corres ponding flags rxsyn/txsyn in the ssc sta- tus register (ssc_sr) on frame synchro edge detection (signals rf/tf). 32.6.6 receive compare modes figure 32-12. receive compare modes cmp0 cmp3 cmp2 cmp1 ignored b0 b2 b1 start rk rd (input) fslen up to 16 bits (4 in this example) stdly datlen 434 6062b?atarm?15-nov-05 at91sam9261 32.6.6.1 compare functions compare 0 can be one start event of the receiver. in this case, the receiver compares at each new sample the last fslen bits received at t he fslen lower bit of the data contained in the compare 0 register (ssc_rc0r). when this start event is selected, the user can program the receiver to start a new data transfer either by writing a new compare 0, or by receiving continuously until compare 1 occurs. this se lection is done with the bit (stop) in ssc_rcmr. 32.6.7 data format the data framing format of both the transmitter and the receiver are programmable through the transmitter frame mode register (ssc_tfmr) and the receiver frame mode register (ssc_rfmr). in either case, the user can independently select: the event that starts the data transfer (start) the delay in number of bit periods between the start event and the first data bit ( sttdly ) the length of the data (datlen) the number of data to be transferred for each start event (datnb). the length of synchronization transferred for each start event (fslen) the bit sense: most or lowest significant bit first (msbf). additionally, the transmitter can be used to transfer synchronization and select the level driven on the td pin while not in data transfer operati on. this is done respectively by the frame sync data enable (fsden) and by the data default value (datdef) bits in ssc_tfmr. 435 6062b?atarm?15-nov-05 at91sam9261 figure 32-13. transmit and receive frame format in edge/pulse start modes note: 1. example of input on falling edge of tf/rf. table 32-3. data frame registers transmitter receiver field length comment ssc_tfmr ssc_rfmr datlen up to 32 size of word ssc_tfmr ssc_rfmr datnb up to 16 number of words transmitted in frame ssc_tfmr ssc_rfmr msbf most significant bit first ssc_tfmr ssc_rfmr fslen up to 16 size of synchro data register ssc_tfmr datdef 0 or 1 data default value ended ssc_tfmr fsden enable send ssc_tshr ssc_tcmr ssc_rcmr period up to 512 frame size ssc_tcmr ssc_rcmr sttdly up to 255 size of transmit start delay sync data default sttdly sync data ignored rd default data datlen data data data datlen data data default default ignored sync data sync data fslen tf/rf (1) start start from ssc_tshr from ssc_thr from ssc_thr from ssc_thr from ssc_thr to ssc_rhr to ssc_rhr to ssc_rshr td (if fsden = 0) td (if fsden = 1) datnb period fromdatdef fromdatdef from datdef from datdef 436 6062b?atarm?15-nov-05 at91sam9261 figure 32-14. transmit frame format in continuous mode note: 1. sttdly is set to 0. in this example, ssc_thr is loaded twice. fsden value has no effect on the transmission. syncdata cannot be output in continuous mode. figure 32-15. receive frame format in continuous mode note: 1. sttdly is set to 0. 32.6.8 loop mode the receiver can be programmed to receive transmissions from the transmitter. this is done by setting the loop mode (loop) bit in ssc_rfm r. in this case, rd is connected to td, rf is connected to tf and rk is connected to tk. 32.6.9 interrupt most bits in ssc_sr have a corresponding bit in interrupt management registers. the ssc can be programmed to generate an interrupt when it detects an event. the interrupt is controlled by writing ssc_ier (interrupt enable register) and ssc_idr (interrupt disable register) these registers enable and disable, re spectively, the corresponding interrupt by set- ting and clearing the corresponding bit in ssc_im r (interrupt mask register), which controls the generation of interrupts by asserting the ssc interrupt line connected to the aic. datlen data datlen data default start from ssc_thr from ssc_thr td start: 1. txempty set to 1 2. write into the ssc_thr data datlen data datlen start = enable receiver to ssc_rhr to ssc_rhr rd 437 6062b?atarm?15-nov-05 at91sam9261 figure 32-16. interrupt block diagram 32.7 ssc application examples the ssc can support several serial communicati on modes used in audio or high speed serial links. some standard applications are shown in th e following figures. all se rial link applications supported by the ssc are not listed here. figure 32-17. audio application block diagram ssc_imr pdc interrupt control ssc interrupt set rxrdy ovrun rxsync receiver transmitter txrdy txempty txsync txbufe endtx rxbuff endrx clear ssc_ier ssc_idr ssc rk rf rd td tf tk clock sck word select ws data sd i2s receiver clock sck word select ws data sd right channel left channel msb msb lsb 438 6062b?atarm?15-nov-05 at91sam9261 figure 32-18. codec application block diagram figure 32-19. time slot application block diagram ssc rk rf rd td tf tk serial data clock (sclk) frame sync (fsync) serial data out serial data in codec serial data clock (sclk) frame sync (fsync) serial data out serial data in first time slot dstart dend ssc rk rf rd td tf tk sclk fsync data out data in codec first time slot serial data clock (sclk) frame sync (fsync) serial data out serial data in codec second time slot first time slot second time slot dstart dend 439 6062b?atarm?15-nov-05 at91sam9261 32.8 synchronous serial contro ller (ssc) user interface table 32-4. register mapping offset register register name access reset 0x0 control register ssc_cr write ? 0x4 clock mode register ssc_cmr read/write 0x0 0x8 reserved ? ? ? 0xc reserved ? ? ? 0x10 receive clock mode register ssc_rcmr read/write 0x0 0x14 receive frame mode register ssc_rfmr read/write 0x0 0x18 transmit clock mode register ssc_tcmr read/write 0x0 0x1c transmit frame mode register ssc_tfmr read/write 0x0 0x20 receive holding register ssc_rhr read 0x0 0x24 transmit holding register ssc_thr write ? 0x28 reserved ? ? ? 0x2c reserved ? ? ? 0x30 receive sync. holding register ssc_rshr read 0x0 0x34 transmit sync. holding register ssc_tshr read/write 0x0 0x38 receive compare 0 register ssc_rc0r read/write 0x0 0x3c receive compare 1 register ssc_rc1r read/write 0x0 0x40 status register ssc_sr read 0x000000cc 0x44 interrupt enable register ssc_ier write ? 0x48 interrupt disable register ssc_idr write ? 0x4c interrupt mask register ssc_imr read 0x0 0x50-0xfc reserved ? ? ? 0x100- 0x124 reserved for peripheral data controller (pdc) ? ? ? 440 6062b?atarm?15-nov-05 at91sam9261 32.8.1 ssc control register name: ssc_cr access type: write-only rxen: receive enable 0: no effect. 1: enables receive if rxdis is not set. rxdis: receive disable 0: no effect. 1: disables receive. if a character is currently being re ceived, disables at end of current character reception. txen: transmit enable 0: no effect. 1: enables transmit if txdis is not set. txdis: transmit disable 0: no effect. 1: disables transmit. if a character is currently being transmitted, disables at end of current character transmission. swrst: software reset 0: no effect. 1: performs a software reset. has priority on any other bit in ssc_cr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 swrst?????txdistxen 76543210 ??????rxdisrxen 441 6062b?atarm?15-nov-05 at91sam9261 32.8.2 ssc clock mode register name: ssc_cmr access type: read/write div: clock divider 0: the clock divider is not active. any other value: the divided clock equals the master clock divided by 2 times div. the maximum bit rate is mck/2. the minimum bit rate is mck/2 x 4095 = mck/8190. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???? div 76543210 div 442 6062b?atarm?15-nov-05 at91sam9261 32.8.3 ssc receive clock mode register name: ssc_rcmr access type: read/write cks: receive clock selection cko: receive clock output mode selection cki: receive clock inversion 0: the data inputs (data and frame sync signals) are sample d on receive clock falling edge . the frame sync signal out- put is shifted out on receive clock rising edge. 1: the data inputs (data and frame sync signals) are sample d on receive clock rising edge. the frame sync signal out- put is shifted out on receive clock falling edge. cki affects only the receive clock and not the output clock signal. 31 30 29 28 27 26 25 24 period 23 22 21 20 19 18 17 16 stddly 15 14 13 12 11 10 9 8 ? ? ? stop start 76543210 ckg cki cko cks cks selected receive clock 0x0 divided clock 0x1 tk clock signal 0x2 rk pin 0x3 reserved cko receive clock output mode rk pin 0x0 none input-only 0x1 continuous receive clock output 0x2 receive clock only during data transfers output 0x3-0x7 reserved 443 6062b?atarm?15-nov-05 at91sam9261 ckg: receive clock gating selection start: receive start selection stop: receive stop selection 0: after completion of a data transfer when starting with a compare 0, the receiver stops the data transfer and waits for a new compare 0. 1: after starting a receive with a compare 0, the receiver operates in a continuous mode until a compare 1 is detected. sttdly: receive start delay if sttdly is not 0, a delay of sttdly clock cycles is inserted between the start event and the actual start of reception. when the receiver is programmed to start synchronously with the transmitter, the delay is also applied. note: it is very important that sttdly be set carefully. if sttdly must be set, it should be done in relation to tag (receive sync data) reception. period: receive period divider selection this field selects the divider to apply to the selected receive clock in order to generate a new frame sync signal. if 0, no period signal is generated. if not 0, a period sig nal is generated each 2 x (period+1) receive clock. ckg receive clock gating 0x0 none, continuous clock 0x1 receive clock enabled only if rf low 0x2 receive clock enabled only if rf high 0x3 reserved start receive start 0x0 continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 0x1 transmit start 0x2 detection of a low level on rf signal 0x3 detection of a high level on rf signal 0x4 detection of a falling edge on rf signal 0x5 detection of a rising edge on rf signal 0x6 detection of any level change on rf signal 0x7 detection of any edge on rf signal 0x8 compare 0 0x9-0xf reserved 444 6062b?atarm?15-nov-05 at91sam9261 32.8.4 ssc receive frame mode register name: ssc_rfmr access type: read/write datlen: data length 0: forbidden value (1-bit data length not supported). any other value: the bit stream contains datlen + 1 data bits. moreover, it defines the transfer size performed by the pdc2 assigned to the receiver. if datlen is lower or equal to 7, data transfers are in bytes. if datlen is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. loop: loop mode 0: normal operating mode. 1: rd is driven by td, rf is driven by tf and tk drives rk. msbf: most significant bit first 0: the lowest significant bit of the data register is sampled first in the bit stream. 1: the most significant bit of the data register is sampled first in the bit stream. datnb: data number per frame this field defines the number of data words to be received after each transfer start, which is equal to (datnb + 1). fslen: receive frame sync length this field defines the length of the receive frame sync signal and the number of bits sampled and stored in the receive sync data register. when this mode is selected by the start field in the receive clock mode register, it also deter- mines the length of the sampled data to be compared to the compare 0 or compare 1 register. pulse length is equal to (fslen + 1) receive clock periods. th us, if fslen is 0, the receive frame sync signal is gener- ated during one receive clock period. 31 30 29 28 27 26 25 24 ???????fsedge 23 22 21 20 19 18 17 16 ? fsos fslen 15 14 13 12 11 10 9 8 ???? datnb 76543210 msbf ? loop datlen 445 6062b?atarm?15-nov-05 at91sam9261 fsos: receive frame sync output selection fsedge: frame sync edge detection determines which edge on frame sy nc will generate the in terrupt rxsyn in the ssc status register. fsos selected receive frame sync signal rf pin 0x0 none input-only 0x1 negative pulse output 0x2 positive pulse output 0x3 driven low during data transfer output 0x4 driven high during data transfer output 0x5 toggling at each start of data transfer output 0x6-0x7 reserved undefined fsedge frame sync edge detection 0x0 positive edge detection 0x1 negative edge detection 446 6062b?atarm?15-nov-05 at91sam9261 32.8.5 ssc transmit clock mode register name: ssc_tcmr access type: read/write cks: transmit clock selection cko: transmit clock output mode selection cki: transmit clock inversion 0: the data outpu ts (data and frame sync signals) are shifted out on tr ansmit clock falling edge . the frame sync signal input is sampled on transmit clock rising edge. 1: the data outputs (data and frame sync signals) are shifted out on transmit clock rising edge. the frame sync signal input is sampled on tran smit clock falling edge. cki affects only the transmit clock and not the output clock signal. ckg: transmit clock gating selection 31 30 29 28 27 26 25 24 period 23 22 21 20 19 18 17 16 sttdly 15 14 13 12 11 10 9 8 ???? start 76543210 ckg cki cko cks cks selected transmit clock 0x0 divided clock 0x1 rk clock signal 0x2 tk pin 0x3 reserved cko transmit clock output mode tk pin 0x0 none input-only 0x1 continuous transmit clock output 0x2 transmit clock only during data transfers output 0x3-0x7 reserved ckg transmit clock gating 0x0 none, continuous clock 0x1 transmit clock enabled only if tf low 0x2 transmit clock enabled only if tf high 0x3 reserved 447 6062b?atarm?15-nov-05 at91sam9261 start: transmit start selection sttdly: transmit start delay if sttdly is not 0, a delay of sttdly clock cycles is insert ed between the start event and the actual start of transmission of data. when the transmitter is programmed to start sync hronously with the receiver, the delay is also applied. note: sttdly must be set carefully. if sttdly is too short in respect to tag (transmit sync data) emission, data is emit- ted instead of the end of tag. period: transmit period divider selection this field selects the divider to apply to the selected transmi t clock to generate a new frame sync signal. if 0, no period signal is generated. if not 0, a period signal is generated at each 2 x (period+1) transmit clock. start transmit start 0x0 continuous, as soon as a word is written in the ssc_thr register (if transmit is enabled), and immediately after the end of transfer of the previous data. 0x1 receive start 0x2 detection of a low level on tf signal 0x3 detection of a high level on tf signal 0x4 detection of a falling edge on tf signal 0x5 detection of a rising edge on tf signal 0x6 detection of any level change on tf signal 0x7 detection of any edge on tf signal 0x8 - 0xf reserved 448 6062b?atarm?15-nov-05 at91sam9261 32.8.6 ssc transmit frame mode register name: ssc_tfmr access type: read/write datlen: data length 0: forbidden value (1-bit data length not supported). any other value: the bit stream contains datlen + 1 data bits. moreover, it defines the transfer size performed by the pdc2 assigned to the transmit. if datlen is lower or equal to 7, data transfers are bytes, if datlen is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. datdef: data default value this bit defines the level driven on the td pin while out of tran smission. note that if the pin is defined as multi-drive by th e pio controller, the pin is enabled only if the scc td output is 1. msbf: most significant bit first 0: the lowest significant bit of the data register is shifted out first in the bit stream. 1: the most significant bit of the data register is shifted out first in the bit stream. datnb: data number per frame this field defines the number of data words to be transferred after each transfer start, which is equal to (datnb +1). fslen: transmit frame sync length this field defines the length of the transmit frame sync signal and the number of bits shifted out from the transmit sync data register if fsden is 1. pulse length is equal to (fslen + 1) transmit clock periods, i.e., the pulse length can range from 1 to 16 transmit clock periods. if fslen is 0, the transmit frame sync signal is generated during one transmit clock period. 31 30 29 28 27 26 25 24 ???????fsedge 23 22 21 20 19 18 17 16 fsden fsos fslen 15 14 13 12 11 10 9 8 ???? datnb 76543210 m s b f ? dat d e f dat l e n 449 6062b?atarm?15-nov-05 at91sam9261 fsos: transmit frame sync output selection fsden: frame sync data enable 0: the td line is driven with the default va lue during the transmi t frame sync signal. 1: ssc_tshr value is shifted out during the tran smission of the transmit frame sync signal. fsedge: frame sync edge detection determines which edge on frame sync will gene rate the interrupt tx syn (status register). fsos selected transmit frame sync signal tf pin 0x0 none input-only 0x1 negative pulse output 0x2 positive pulse output 0x3 driven low during data transfer output 0x4 driven high during data transfer output 0x5 toggling at each start of data transfer output 0x6-0x7 reserved undefined fsedge frame sync edge detection 0x0 positive edge detection 0x1 negative edge detection 450 6062b?atarm?15-nov-05 at91sam9261 32.8.7 ssc receive holding register name: ssc_rhr access type: read-only rdat: receive data right aligned regardless of the number of data bits defined by datlen in ssc_rfmr. 32.8.8 ssc transmit holding register name: ssc_thr access type: write-only tdat: transmit data right aligned regardless of the number of data bits defined by datlen in ssc_tfmr. 31 30 29 28 27 26 25 24 rdat 23 22 21 20 19 18 17 16 rdat 15 14 13 12 11 10 9 8 rdat 76543210 rdat 31 30 29 28 27 26 25 24 tdat 23 22 21 20 19 18 17 16 tdat 15 14 13 12 11 10 9 8 tdat 76543210 tdat 451 6062b?atarm?15-nov-05 at91sam9261 32.8.9 ssc receive synchronization holding register name: ssc_rshr access type: read-only rsdat: receive synchronization data 32.8.10 ssc transmit synchronization holding register name: ssc_tshr access type: read/write tsdat: transmit synchronization data 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rsdat 76543210 rsdat 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 tsdat 76543210 tsdat 452 6062b?atarm?15-nov-05 at91sam9261 32.8.11 ssc receive compare 0 register name: ssc_rc0r access type: read/write cp0: receive compare data 0 32.8.12 ssc receive compare 1 register name: ssc_rc1r access type: read/write cp1: receive compare data 1 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cp0 76543210 cp0 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cp1 76543210 cp1 453 6062b?atarm?15-nov-05 at91sam9261 32.8.13 ssc status register name: ssc_sr access type: read-only txrdy: transmit ready 0: data has been loaded in ssc_thr and is waiting to be loaded in the transmit shift register (tsr). 1: ssc_thr is empty. txempty: transmit empty 0: data remains in ssc_thr or is currently transmitted from tsr. 1: last data written in ssc_thr has been loaded in tsr and last data loaded in tsr has been transmitted. endtx: end of transmission 0: the register ssc_tcr has not reached 0 since the last write in ssc_tcr or ssc_tncr. 1: the register ssc_tcr has reached 0 sinc e the last write in ssc_tcr or ssc_tncr. txbufe: transmit buffer empty 0: ssc_tcr or ssc_tncr have a value other than 0. 1: both ssc_tcr and ssc_tncr have a value of 0. rxrdy: receive ready 0: ssc_rhr is empty. 1: data has been received and loaded in ssc_rhr. ovrun: receive overrun 0: no data has been loaded in ssc_rhr wh ile previous data has not been read since the last read of the status register. 1: data has been loaded in ssc_rhr while previous data has not yet been read since the last read of the status register. endrx: end of reception 0: data is written on the receive counter register or receive ne xt counter register. 1: end of pdc transfer when receive counter register has arrived at zero. rxbuff: receive buffer full 0: ssc_rcr or ssc_rncr have a value other than 0. 1: both ssc_rcr and ssc_rncr have a value of 0. cp0: compare 0 0: a compare 0 has not occurred since the last read of the status register. 1: a compare 0 has occurred since the last read of the status register. cp1: compare 1 0: a compare 1 has not occurred since the last read of the status register. 1: a compare 1 has occurred since the last read of the status register. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ??????rxentxen 15 14 13 12 11 10 9 8 ????rxsynt xsyn cp1 cp0 76543210 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy 454 6062b?atarm?15-nov-05 at91sam9261 txsyn: transmit sync 0: a tx sync has not occurred since the last read of the status register. 1: a tx sync has occurred since the last read of the status register. rxsyn: receive sync 0: an rx sync has not occurred since the last read of the status register. 1: an rx sync has occurred since the last read of the status register. txen: transmit enable 0: transmit is disabled. 1: transmit is enabled. rxen: receive enable 0: receive is disabled. 1: receive is enabled. 455 6062b?atarm?15-nov-05 at91sam9261 32.8.14 ssc interrupt enable register name: ssc_ier access type: write-only txrdy: transmit ready interrupt enable 0: no effect. 1: enables the transmit ready interrupt. txempty: transmit empty interrupt enable 0: no effect. 1: enables the transmit empty interrupt. endtx: end of transmission interrupt enable 0: no effect. 1: enables the end of transmission interrupt. txbufe: transmit buffer empty interrupt enable 0: no effect. 1: enables the transmit buffer empty interrupt rxrdy: receive ready interrupt enable 0: no effect. 1: enables the receive ready interrupt. ovrun: receive overrun interrupt enable 0: no effect. 1: enables the receive overrun interrupt. endrx: end of reception interrupt enable 0: no effect. 1: enables the end of reception interrupt. rxbuff: receive buffer full interrupt enable 0: no effect. 1: enables the receive buffer full interrupt. cp0: compare 0 interrupt enable 0: no effect. 1: enables the compare 0 interrupt. cp1: compare 1 interrupt enable 0: no effect. 1: enables the compare 1 interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????rxsynt xsyn cp1 cp0 76543210 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy 456 6062b?atarm?15-nov-05 at91sam9261 txsyn: tx sync interrupt enable 0: no effect. 1: enables the tx sync interrupt. rxsyn: rx sync interrupt enable 0: no effect. 1: enables the rx sync interrupt. 457 6062b?atarm?15-nov-05 at91sam9261 32.8.15 ssc interrupt disable register name: ssc_idr access type: write-only txrdy: transmit ready interrupt disable 0: no effect. 1: disables the transmit ready interrupt. txempty: transmit empty interrupt disable 0: no effect. 1: disables the transmit empty interrupt. endtx: end of transmission interrupt disable 0: no effect. 1: disables the end of transmission interrupt. txbufe: transmit buffer empty interrupt disable 0: no effect. 1: disables the transmit buffer empty interrupt. rxrdy: receive ready interrupt disable 0: no effect. 1: disables the rece ive ready interrupt. ovrun: receive overrun interrupt disable 0: no effect. 1: disables the receive overrun interrupt. endrx: end of reception interrupt disable 0: no effect. 1: disables the end of reception interrupt. rxbuff: receive buffer full interrupt disable 0: no effect. 1: disables the receiv e buffer full interrupt. cp0: compare 0 interrupt disable 0: no effect. 1: disables the compare 0 interrupt. cp1: compare 1 interrupt disable 0: no effect. 1: disables the compare 1 interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????rxsynt xsyn cp1 cp0 76543210 rxbuff endrx ovrun rxrdy txbufe endtx txempty txrdy 458 6062b?atarm?15-nov-05 at91sam9261 txsyn: tx sync interrupt enable 0: no effect. 1: disables the tx sync interrupt. rxsyn: rx sync interrupt enable 0: no effect. 1: disables the rx sync interrupt. 459 6062b?atarm?15-nov-05 at91sam9261 32.8.16 ssc interrupt mask register name: ssc_imr access type: read-only txrdy: transmit ready interrupt mask 0: the transmit ready interrupt is disabled. 1: the transmit ready interrupt is enabled. txempty: transmit empty interrupt mask 0: the transmit empty interrupt is disabled. 1: the transmit empty interrupt is enabled. endtx: end of transmission interrupt mask 0: the end of transmission interrupt is disabled. 1: the end of transmission interrupt is enabled. txbufe: transmit buffer empty interrupt mask 0: the transmit buffer empty interrupt is disabled. 1: the transmit buffer empty interrupt is enabled. rxrdy: receive ready interrupt mask 0: the receive ready interrupt is disabled. 1: the receive ready interrupt is enabled. ovrun: receive overrun interrupt mask 0: the receive overrun interrupt is disabled. 1: the receive overrun interrupt is enabled. endrx: end of reception interrupt mask 0: the end of reception interrupt is disabled. 1: the end of reception interrupt is enabled. rxbuff: receive buffer full interrupt mask 0: the receive buffer full interrupt is disabled. 1: the receive buffer full interrupt is enabled. cp0: compare 0 interrupt mask 0: the compare 0 interrupt is disabled. 1: the compare 0 interrupt is enabled. cp1: compare 1 interrupt mask 0: the compare 1 interrupt is disabled. 1: the compare 1 interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????rxsynt xsyn cp1 cp0 76543210 rxbuf endrx ovrun rxrdy txbufe endtx txempty txrdy 460 6062b?atarm?15-nov-05 at91sam9261 txsyn: tx sync interrupt mask 0: the tx sync interrupt is disabled. 1: the tx sync interrupt is enabled. rxsyn: rx sync interrupt mask 0: the rx sync interrupt is disabled. 1: the rx sync interrupt is enabled. 461 6062b?atarm?15-nov-05 at91sam9261 33. timer/counter (tc) 33.1 overview the timer/counter (tc) includes three identical 16-bit timer/counter channels. each channel can be independently programmed to perform a wide range of functions includ- ing frequency measurement, event counting, interval measurem ent, pulse generation, delay timing and pulse width modulation. each channel has three external clock inputs, fi ve internal clock inputs and two multi-purpose input/output signals which can be configured by the user. each channel drives an internal interrupt signal which can be programmed to generate processor interrupts. the timer/counter block has two global registers which act upon all three tc channels. the block control register allows the three ch annels to be started simultaneously with the same instruction. the block mode register defines the external clock inputs for each channel, allowing them to be chained. 33.2 block diagram figure 33-1. timer/counter block diagram timer/counter channel 0 timer/counter channel 1 timer/counter channel 2 sync parallel i/o controller tc1xc1s tc0xc0s tc2xc2s int0 int1 int2 tioa0 tioa1 tioa2 tiob0 tiob1 tiob2 xc0 xc1 xc2 xc0 xc1 xc2 xc0 xc1 xc2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tioa1 tioa2 tioa0 tioa2 tioa0 tioa1 advanced interrupt controller tclk0 tclk1 tclk2 tioa0 tiob0 tioa1 tiob1 tioa2 tiob2 timer counter tioa tiob tioa tiob tioa tiob sync sync timer_clock2 timer_clock3 timer_clock4 timer_clock5 timer_clock1 462 6062b?atarm?15-nov-05 at91sam9261 33.3 pin name list 33.4 product dependencies 33.4.1 i/o lines the pins used for interfacing the compliant ex ternal devices may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the tc pins to their peripheral functions. 33.4.2 power management the tc is clocked through the power management controller (pmc), thus the programmer must first configure the pmc to enable the timer/counter clock. 33.4.3 interrupt the tc has an interrupt line connected to the advanced interrupt controller (aic). handling the tc interrupt requires programming the aic before configuring the tc. table 33-1. signal name description block/channel signal name description channel signal xc0, xc1, xc2 external clock inputs tioa capture mode: timer/counter input waveform mode: timer/counter output tiob capture mode: timer/counter input waveform mode: timer/counter input/output int interrupt signal output sync synchronization input signal table 33-2. tc pin list pin name description type tclk0-tclk2 external clock input input tioa0-tioa2 i/o line a i/o tiob0-tiob2 i/o line b i/o 463 6062b?atarm?15-nov-05 at91sam9261 33.5 functional description 33.5.1 tc description the three channels of the timer/counter are independent and identical in operation. the reg- isters for channel programming are listed in table 33-4 on page 476 . 33.5.1.1 16-bit counter each channel is organized around a 16-bit counter. the value of the counter is incremented at each positive edge of the selected clock. when the counter has reached the value 0xffff and passes to 0x0000, an overflow occurs and th e covfs bit in tc_sr (status register) is set. the current value of the counter is accessible in real time by reading the counter value regis- ter, tc_cv. the counter can be reset by a trigger . in this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 33.5.1.2 clock selection at block level, input clock signals of each channel can either be connected to the external inputs tclk0, tclk1 or tclk2, or be connected to the configurable i/o signals tioa0, tioa1 or tioa2 for chaining by programming the tc_bmr (block mode). see figure 33-2 . each channel can independently select an internal or external clock source for its counter: internal clock signals: timer_cl ock1, timer_clock2, timer_clock3, timer_clock4, timer_clock5 external clock signals: xc0, xc1 or xc2 this selection is made by the tcclks bits in the tc channel mode register. the selected clock can be inverted with the clki bit in tc_cmr. this allows counting on the opposite edges of the clock. the burst function allows the clock to be vali dated when an external signal is high. the burst parameter in the mode register defines this signal (none, xc0, xc1, xc2). note: in all cases, if an external clock is used, the duration of each of its levels must be longer than the master clock period. the external clock frequency must be at least 2.5 times lower than the master clock 464 6062b?atarm?15-nov-05 at91sam9261 figure 33-2. clock selection 33.5.1.3 clock control the clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. see figure 33-3 . the clock can be enabled or disabled by the user with the clken and the clkdis commands in the control register. in capture mode it can be disabled by an rb load event if ldbdis is set to 1 in tc_cmr. in waveform mode, it can be disabled by an rc compare event if cpcdis is set to 1 in tc_cmr. when disabled, the start or the stop actions have no effect: only a clken command in the control register can re-enable the clock. when the clock is enabled, the clksta bit is set in the status register. the clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. the clock can be stopped by an rb load event in capture mode (ldbstop = 1 in tc_cmr) or a rc compare event in waveform mode (cpcstop = 1 in tc_cmr). the start and the stop commands have effect only if the clock is enabled. timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 tcclks clki burst 1 selected clock 465 6062b?atarm?15-nov-05 at91sam9261 figure 33-3. clock control 33.5.1.4 tc operating modes each channel can independently operate in two different modes: capture mode provides measurement on signals. waveform mode provides wave generation. the tc operating mode is programmed with the wave bit in the tc channel mode register. in capture mode, tioa and tiob are configured as inputs. in waveform mode, tioa is always configured to be an output and tiob is an output if it is not selected to be the external trigger. 33.5.1.5 trigger a trigger resets the counter and starts the coun ter clock. three types of triggers are common to both modes, and a fourth external trigger is available to each mode. the following triggers are common to both modes: software trigger: each channel has a software trigger, available by setting swtrg in tc_ccr. sync: each channel has a synchronization signal sync. when asserted, this signal has the same effect as a software trigger. the sync signals of all channels are asserted simultaneously by writing tc_bcr (block control) with sync set. compare rc trigger: rc is implemented in each channel and can provide a trigger when the counter value matches the rc valu e if cpctrg is set in tc_cmr. the channel can also be configured to have an external trigger. in capture mode, the external trigger signal can be selected between tioa and tiob. in waveform mode, an external event can be programmed on one of the following signal s: tiob, xc0, xc1 or xc2. this external event can then be programmed to perform a trigger by setting enetrg in tc_cmr. if an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. qs r s r q clksta clken clkdis stop event disable event counter clock selected clock trigger 466 6062b?atarm?15-nov-05 at91sam9261 regardless of the trigger used, it will be taken in to account at the followin g active edge of the selected clock. this means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. 33.5.2 capture operating mode this mode is entered by cleari ng the wave parameter in tc_cmr (channel mode register). capture mode allows the tc channel to perf orm measurements such as pulse timing, fre- quency, period, duty cycle and phase on tioa and tiob signals which are considered as inputs. figure 33-4 shows the configuration of the tc channel when programmed in capture mode. 33.5.2.1 capture registers a and b registers a and b (ra and rb) are used as captur e registers. this means that they can be loaded with the counter value when a programmable event occurs on the signal tioa. the ldra parameter in tc_cmr defines the tioa edge for the loading of register a, and the ldrb parameter defines the tioa edge for the loading of register b. ra is loaded only if it has not been loaded since the last trigger or if rb has been loaded since the last loading of ra. rb is loaded only if ra has been loaded sinc e the last trigger or t he last loading of rb. loading ra or rb before the read of the last value loaded sets the overrun error flag (lovrs) in tc_sr (status register). in this case, the old value is overwritten. 33.5.2.2 trigger conditions in addition to the sync signal, the software trigger and the rc compare trigger, an external trigger can be defined. the abetrg bit in tc_cmr select s tioa or tiob input signal as an external trigger. the etrgedg parameter defines the e dge (rising, falling or both) de tected to gene rate an exter- nal trigger. if etrgedg = 0 (none), the external trigger is disabled. 467 6062b?atarm?15-nov-05 at91sam9261 figure 33-4. capture mode timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 tcclks clki qs r s r q clksta clken clkdis burst tiob register c capture register a capture register b compare rc = 16-bit counter abetrg swtrg etrgedg cpctrg tc1_imr trig ldrbs ldras etrgs tc1_sr lovrs covfs sync 1 mtiob tioa mtioa ldra ldbstop if ra is not loaded or rb is loaded if ra is loaded ldbdis cpcs int edge detector edge detector ldrb edge detector clk ovf reset timer/counter channel 468 6062b?atarm?15-nov-05 at91sam9261 33.5.3 waveform operating mode waveform operating mode is entered by setting the wave par ameter in tc_cmr (channel mode register). in waveform operating mode the tc channel generates 1 or 2 pwm signals with the same frequency and independently programmable duty cycles , or generates different types of one- shot or repetitive pulses. in this mode, tioa is configured as an output and tiob is defined as an output if it is not used as an external event ( eevt parameter in tc_cmr). figure 33-5 shows the configuration of the tc channel when programmed in waveform oper- ating mode. 33.5.3.1 waveform selection depending on the wavsel parameter in tc_cmr (channel mode register), the behavior of tc_cv varies. with any selection, ra, rb and rc can all be used as compare registers. ra compare is used to control the tioa output, rb compare is used to control the tiob out- put (if correctly configured) and rc compare is used to control tioa and/or tiob outputs. 469 6062b?atarm?15-nov-05 at91sam9261 figure 33-5. waveform mode tcclks clki qs r s r q clksta clken clkdis cpcdis burst tiob register a register b register c compare ra = compare rb = compare rc = cpcstop 16-bit counter eevt eevtedg sync swtrg enetrg wavsel tc1_imr trig acpc acpa aeevt aswtrg bcpc bcpb beevt bswtrg tioa mtioa tiob mtiob cpas covfs etrgs tc1_sr cpcs cpbs clk ovf reset output controller output controller int 1 edge detector timer/counter channel timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 wavsel 470 6062b?atarm?15-nov-05 at91sam9261 wavsel = 00 when wavsel = 00, the value of tc_cv is in cremented from 0 to 0xffff. once 0xffff has been reached, the value of tc_cv is reset. incrementation of tc_cv starts again and the cycle continues. see figure 33-6 . an external event trigger or a software trigger can reset the value of tc_cv. it is important to note that the trigger may occur at any time. see figure 33-7 . rc compare cannot be programmed to generate a trigger in this configuration. at the same time, rc compare can stop the counter clock (cpcstop = 1 in tc_cmr) and/or disable the counter clock (cpcdis = 1 in tc_cmr). figure 33-6. wavsel= 00 without trigger time counter value r c r b r a tiob tioa counter cleared by compare match with 0xffff 0xffff waveform examples 471 6062b?atarm?15-nov-05 at91sam9261 figure 33-7. wavsel= 00 with trigger wavsel = 10 when wavsel = 10, the value of tc_cv is increm ented from 0 to the value of rc, then auto- matically reset on a rc compare. once the value of tc_cv has been reset, it is then incremented and so on. see figure 33-8 . it is important to note that tc_cv can be reset at any time by an external event or a software trigger if both are programmed correctly. see figure 33-9 . in addition, rc compare can stop the counte r clock (cpcstop = 1 in tc_cmr) and/or dis- able the counter clock (cpcdis = 1 in tc_cmr). figure 33-8. wavsel = 10 without trigger time counter value r c r b r a tiob tioa counter cleared by compare match with 0xffff 0xffff waveform examples counter cleared by trigger time counter value r c r b r a tiob tioa counter cleared by compare match with rc 0xffff waveform examples 472 6062b?atarm?15-nov-05 at91sam9261 figure 33-9. wavsel = 10 with trigger wavsel = 01 when wavsel = 01, the value of tc_cv is incremented from 0 to 0xffff. once 0xffff is reached, the value of tc_cv is decremented to 0, then re-incremented to 0xffff and so on. see figure 33-10 . a trigger such as an external event or a software trigger can modify tc_cv at any time. if a trigger occurs while tc_cv is incrementing, tc_cv then decrements. if a trigger is received while tc_cv is decrementing, tc_cv then increments. see figure 33-11 . rc compare cannot be programmed to generate a trigger in this configuration. at the same time, rc compare can stop the counter clock (cpcstop = 1) and/or disable the counter clock (cpcdis = 1). time counter value r c r b r a tiob tioa counter cleared by compare match with rc 0xffff waveform examples counter cleared by trigger 473 6062b?atarm?15-nov-05 at91sam9261 figure 33-10. wavsel = 01 without trigger figure 33-11. wavsel = 01 with trigger wavsel = 11 when wavsel = 11, the value of tc_cv is incremented from 0 to rc. once rc is reached, the value of tc_cv is decremented to 0, then re-incremented to rc and so on. see figure 33-12 . a trigger such as an external event or a software trigger can modify tc_cv at any time. if a trigger occurs while tc_cv is incrementing, tc_cv then decrements. if a trigger is received while tc_cv is decrementing, tc_cv then increments. see figure 33-13 . rc compare can stop the counter clock (cpcstop = 1) and/or disable the counter clock (cpcdis = 1). time counter value r c r b r a tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples time counter value tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples counter decremented by trigger counter incremented by trigger r c r b r a 474 6062b?atarm?15-nov-05 at91sam9261 figure 33-12. wavsel = 11 without trigger figure 33-13. wavsel = 11 with trigger 33.5.3.2 external event/trigger conditions an external event can be programmed to be det ected on one of the clock sources (xc0, xc1, xc2) or tiob. the external event selected can then be used as a trigger. the parameter eevt parameter in tc_cmr se lects the external trigger. the eevtedg parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). if eevtedg is cleared (no ne), no external event is defined. if tiob is defined as an external event signal (eevt = 0), tiob is no longer used as an output and the tc channel can only generate a waveform on tioa. time counter value r c r b r a tiob tioa counter decremented by compare match with rc 0xffff waveform examples time counter value tiob tioa counter decremented by compare match with rc 0xffff waveform examples counter decremented by trigger counter incremented by trigger r c r b r a 475 6062b?atarm?15-nov-05 at91sam9261 when an external event is defined, it can be used as a trigger by setting bit enetrg in tc_cmr. as in capture mode, the sync signal and the softw are trigger are also available as triggers. rc compare can also be used as a tr igger depending on the parameter wavsel. 33.5.3.3 output controller the output controller defines the output level changes on tioa and tiob following an event. tiob control is used only if tiob is defin ed as output (not as an external event). the following events control tioa and tiob: so ftware trigger, external event and rc com- pare. ra compare controls tioa and rb comp are controls tiob. each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in tc_cmr. 476 6062b?atarm?15-nov-05 at91sam9261 33.6 timer/counter (tc) user interface 33.6.1 global register mapping tc_bcr (block control register) and tc_bmr (block mode register) control the whole tc block. tc channels are controlled by the registers listed in table 33-4 . the offset of each of the channel registers in table 33-4 is in relation to the offset of the corresponding channel as men - tioned in table 33-4 . 33.6.2 channel memory mapping note: 1. read only if wave = 0 table 33-3. timer/counter (tc) global register map offset channel/register name access reset value 0x00 tc channel 0 see table 33-4 0x40 tc channel 1 see table 33-4 0x80 tc channel 2 see table 33-4 0xc0 tc block control register tc_bcr write-only ? 0xc4 tc block mode register tc_bmr read/write 0 table 33-4. timer/counter (tc) channel memory mapping offset register name access reset value 0x00 channel control register tc_ccr write-only ? 0x04 channel mode register tc_cmr read/write 0 0x08 reserved ? ? ? 0x0c reserved ? ? ? 0x10 counter value tc_cv read-only 0 0x14 register a tc_ra read/write (1) 0 0x18 register b tc_rb read/write (1) 0 0x1c register c tc_rc read/write 0 0x20 status register tc_sr read-only 0 0x24 interrupt enable register tc_ier write-only ? 0x28 interrupt disable register tc_idr write-only ? 0x2c interrupt mask register tc_imr read-only 0 0x30-0xfc reserved ? ? ? 477 6062b?atarm?15-nov-05 at91sam9261 33.6.3 tc block control register register name: tc_bcr access type: write-only sync: synchro command 0 = no effect. 1 = asserts the sync signal which generates a software trigger simultaneously for each of the channels. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????sync 478 6062b?atarm?15-nov-05 at91sam9261 33.6.4 tc block mode register register name: tc_bmr access type: read/write tc0xc0s: external clock signal 0 selection tc1xc1s: external clock signal 1 selection tc2xc2s: external clock signal 2 selection 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? tc2xc2s tcxc1s tc0xc0s tc0xc0s signal connected to xc0 00tclk0 0 1 none 10tioa1 11tioa2 tc1xc1s signal connected to xc1 00tclk1 0 1 none 10tioa0 11tioa2 tc2xc2s signal connected to xc2 00tclk2 0 1 none 10tioa0 11tioa1 479 6062b?atarm?15-nov-05 at91sam9261 33.6.5 tc channel control register register name: tc_ccr access type: write-only clken: counter clock enable command 0 = no effect. 1 = enables the clock if clkdis is not 1. clkdis: counter clock disable command 0 = no effect. 1 = disables the clock. swtrg: software trigger command 0 = no effect. 1 = a software trigger is performed: the counter is reset and the clock is started. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????swtrgclkdisclken 480 6062b?atarm?15-nov-05 at91sam9261 33.6.6 tc channel mode register: capture mode register name: tc_cmr access type: read/write tcclks: clock selection clki: clock invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock. burst: burst signal selection ldbstop: counter clock stopped with rb loading 0 = counter clock is not stopped when rb loading occurs. 1 = counter clock is stopped when rb loading occurs. ldbdis: counter clock disable with rb loading 0 = counter clock is not disabl ed when rb loading occurs. 1 = counter clock is disabled when rb loading occurs. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? ? ldrb ldra 15 14 13 12 11 10 9 8 wave = 0 cpctrg ? ? ? abetrg etrgedg 76543210 ldbdis ldbstop burst clki tcclks tcclks clock selected 000timer_clock1 001timer_clock2 010timer_clock3 011timer_clock4 100timer_clock5 101xc0 110xc1 111xc2 burst 0 0 the clock is not gated by an external signal. 0 1 xc0 is anded with the selected clock. 1 0 xc1 is anded with the selected clock. 1 1 xc2 is anded with the selected clock. 481 6062b?atarm?15-nov-05 at91sam9261 etrgedg: external trigger edge selection abetrg: tioa or tiob external trigger selection 0 = tiob is used as an external trigger. 1 = tioa is used as an external trigger. cpctrg: rc compare trigger enable 0 = rc compare has no effect on the counter and its clock. 1 = rc compare resets the counter and starts the counter clock. wave 0 = capture mode is enabled. 1 = capture mode is disabled (waveform mode is enabled). ldra: ra loading selection ldrb: rb loading selection etrgedg edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge ldra edge 0 0 none 0 1 rising edge of tioa 1 0 falling edge of tioa 1 1 each edge of tioa ldrb edge 0 0 none 0 1 rising edge of tioa 1 0 falling edge of tioa 1 1 each edge of tioa 482 6062b?atarm?15-nov-05 at91sam9261 33.6.7 tc channel mode register: waveform mode register name: tc_cmr access type: read/write tcclks: clock selection clki: clock invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock. burst: burst signal selection cpcstop: counter clock stopped with rc compare 0 = counter clock is not stopped when counter reaches rc. 1 = counter clock is stopped when counter reaches rc. cpcdis: counter clock disable with rc compare 0 = counter clock is not disabl ed when counter reaches rc. 1 = counter clock is disabled when counter reaches rc. 31 30 29 28 27 26 25 24 bswtrg beevt bcpc bcpb 23 22 21 20 19 18 17 16 aswtrg aeevt acpc acpa 15 14 13 12 11 10 9 8 wave = 1 wavsel enetrg eevt eevtedg 76543210 cpcdis cpcstop burst clki tcclks tcclks clock selected 0 0 0 timer_clock1 0 0 1 timer_clock2 0 1 0 timer_clock3 0 1 1 timer_clock4 1 0 0 timer_clock5 101xc0 110xc1 111xc2 burst 0 0 the clock is not gated by an external signal. 0 1 xc0 is anded with the selected clock. 1 0 xc1 is anded with the selected clock. 1 1 xc2 is anded with the selected clock. 483 6062b?atarm?15-nov-05 at91sam9261 eevtedg: external ev ent edge selection eevt: external event selection note: 1. if tiob is chosen as the external event signal, it is configured as an input and no longer generates waveforms . enetrg: external event trigger enable 0 = the external event has no effect on the counter and its clock. in this case, the selected external event only controls the tioa output. 1 = the external event resets the counter and starts the counter clock. wavsel: waveform selection wave = 1 0 = waveform mode is disabled (capture mode is enabled). 1 = waveform mode is enabled. acpa: ra compare effect on tioa eevtedg edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge eevt signal selected as exte rnal event tiob direction 0 0 tiob input (1) 01xc0 output 10xc1 output 11xc2 output wavsel effect 0 0 up mode without automatic trigger on rc compare 1 0 up mode with automa tic trigger on rc compare 0 1 updown mode without automatic trigger on rc compare 1 1 updown mode with automatic trigger on rc compare acpa effect 0 0 none 0 1 set 1 0 clear 1 1 toggle 484 6062b?atarm?15-nov-05 at91sam9261 acpc: rc compare effect on tioa aeevt: external event effect on tioa aswtrg: software trigger effect on tioa bcpb: rb compare effect on tiob bcpc: rc compare effect on tiob acpc effect 0 0 none 0 1 set 1 0 clear 1 1 toggle aeevt effect 0 0 none 0 1 set 1 0 clear 1 1 toggle aswtrg effect 0 0 none 0 1 set 1 0 clear 1 1 toggle bcpb effect 0 0 none 0 1 set 1 0 clear 1 1 toggle bcpc effect 0 0 none 0 1 set 1 0 clear 1 1 toggle 485 6062b?atarm?15-nov-05 at91sam9261 beevt: external event effect on tiob bswtrg: software trigger effect on tiob beevt effect 0 0 none 0 1 set 1 0 clear 1 1 toggle bswtrg effect 0 0 none 0 1 set 1 0 clear 1 1 toggle 486 6062b?atarm?15-nov-05 at91sam9261 33.6.8 tc counter value register register name: tc_cv access type: read-only cv: counter value cv contains the counter value in real time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cv 76543210 cv 487 6062b?atarm?15-nov-05 at91sam9261 33.6.9 tc register a register name: tc_ra access type: read-only if wave = 0, read/write if wave = 1 ra: register a ra contains the register a value in real time. 33.6.10 tc register b register name: tc_rb access type: read-only if wave = 0, read/write if wave = 1 rb: register b rb contains the register b value in real time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ra 76543210 ra 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rb 76543210 rb 488 6062b?atarm?15-nov-05 at91sam9261 33.6.11 tc register c register name: tc_rc access type: read/write rc: register c rc contains the register c value in real time. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rc 76543210 rc 489 6062b?atarm?15-nov-05 at91sam9261 33.6.12 tc status register register name: tc_sr access type: read-only covfs: counter overflow status 0 = no counter overflow has occurred since the last read of the status register. 1 = a counter overflow has occurred since the last read of the status register. lovrs: load overrun status 0 = load overrun has not occurred since the last read of the status register or wave = 1. 1 = ra or rb have been loaded at least twice without any read of the corresponding register since the last read of the sta- tus register, if wave = 0. cpas: ra compare status 0 = ra compare has not occurred since the last read of the status register or wave = 0. 1 = ra compare has occurred since the last read of the status register, if wave = 1. cpbs: rb compare status 0 = rb compare has not occurred since the last read of the status register or wave = 0. 1 = rb compare has occurred since the last read of the status register, if wave = 1. cpcs: rc compare status 0 = rc compare has not occurred since the last read of the status register. 1 = rc compare has occurred since the last read of the status register. ldras: ra loading status 0 = ra load has not occurred si nce the last read of the status register or wave = 1. 1 = ra load has occurred since the last re ad of the status register, if wave = 0. ldrbs: rb loading status 0 = rb load has not occurred si nce the last read of the status register or wave = 1. 1 = rb load has occurred since the last re ad of the status register, if wave = 0. etrgs: external trigger status 0 = external trigger has not occurred since the last read of the status register. 1 = external trigger has occurred since the last read of the status register. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?????mtiobmtioaclksta 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs 490 6062b?atarm?15-nov-05 at91sam9261 clksta: clock enabling status 0 = clock is disabled. 1 = clock is enabled. mtioa: tioa mirror 0 = tioa is low. if wave = 0, this mean s that tioa pin is low. if wave = 1, this means that tioa is driven low. 1 = tioa is high. if wave = 0, this mean s that tioa pin is high. if wave = 1, this means that ti oa is driven high. mtiob: tiob mirror 0 = tiob is low. if wave = 0, this mean s that tiob pin is low. if wave = 1, this means that tiob is driven low. 1 = tiob is high. if wave = 0, this mean s that tiob pin is high. if wave = 1, this means that ti ob is driven high. 491 6062b?atarm?15-nov-05 at91sam9261 33.6.13 tc interrupt enable register register name: tc_ier access type: write-only covfs: counter overflow 0 = no effect. 1 = enables the counter overflow interrupt. lovrs: load overrun 0 = no effect. 1 = enables the load overrun interrupt. cpas: ra compare 0 = no effect. 1 = enables the ra compare interrupt. cpbs: rb compare 0 = no effect. 1 = enables the rb compare interrupt. cpcs: rc compare 0 = no effect. 1 = enables the rc compare interrupt. ldras: ra loading 0 = no effect. 1 = enables the ra load interrupt. ldrbs: rb loading 0 = no effect. 1 = enables the rb load interrupt. etrgs: external trigger 0 = no effect. 1 = enables the external trigger interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs 492 6062b?atarm?15-nov-05 at91sam9261 33.6.14 tc interrupt disable register register name: tc_idr access type: write-only covfs: counter overflow 0 = no effect. 1 = disables the counter overflow interrupt. lovrs: load overrun 0 = no effect. 1 = disables the load overru n interrupt (if wave = 0). cpas: ra compare 0 = no effect. 1 = disables the ra compare interrupt (if wave = 1). cpbs: rb compare 0 = no effect. 1 = disables the rb compare interrupt (if wave = 1). cpcs: rc compare 0 = no effect. 1 = disables the rc compare interrupt. ldras: ra loading 0 = no effect. 1 = disables the ra load interrupt (if wave = 0). ldrbs: rb loading 0 = no effect. 1 = disables the rb load interrupt (if wave = 0). etrgs: external trigger 0 = no effect. 1 = disables the external trigger interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs 493 6062b?atarm?15-nov-05 at91sam9261 33.6.15 tc interrupt mask register register name: tc_imr access type: read-only covfs: counter overflow 0 = the counter overflow interrupt is disabled. 1 = the counter overflow interrupt is enabled. lovrs: load overrun 0 = the load overrun interrupt is disabled. 1 = the load overrun interrupt is enabled. cpas: ra compare 0 = the ra compare interrupt is disabled. 1 = the ra compare interrupt is enabled. cpbs: rb compare 0 = the rb compare interrupt is disabled. 1 = the rb compare interrupt is enabled. cpcs: rc compare 0 = the rc compare interrupt is disabled. 1 = the rc compare interrupt is enabled. ldras: ra loading 0 = the load ra interrupt is disabled. 1 = the load ra interrupt is enabled. ldrbs: rb loading 0 = the load rb interrupt is disabled. 1 = the load rb interrupt is enabled. etrgs: external trigger 0 = the external trigger interrupt is disabled. 1 = the external trigger interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs 494 6062b?atarm?15-nov-05 at91sam9261 495 6062b?atarm?15-nov-05 at91sam9261 34. multimedia card interface (mci) 34.1 overview the multimedia card interface (mci) supports the multimediacard (mmc) specification v2.2 and the sd memory card specification v1.0. the mci includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead. the mci supports stream, block and multi-block data read and write, and is compatible with the peripheral data controller channels, minimizing processor intervention for large buffer transfers. the mci operates at a rate of up to master clock divided by 2 and supports the interfacing of one slot(s). each slot may be used to interface with a multimediacard bus (up to 30 cards) or with a sd memory card. only one slot can be selected at a time (slots are multiplexed). a bit field in the sd card register performs this selection. the sd memory card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the multimediacard on a 7-pin interface (clock, command, one data, three power lines and one reserved for future use). the sd memory card interface also supports multimedia card operations. the main differ- ences between sd and multimedia cards are the initialization process and the bus topology. 34.2 block diagram figure 34-1. block diagram mci interface interrupt control pio pdc apb bridge pmc mck mci interrupt mcck mccda mcda0 mcda1 mcda2 mcda3 apb 496 6062b?atarm?15-nov-05 at91sam9261 34.3 application block diagram figure 34-2. application block diagram 34.4 pin name list note: 1. i: input, o: output, pp: push/pull, od: open drain. 23456 17 mmc 23456 17 8 sdcard 9 physical layer mci interface application layer ex: file system, audio, security, etc. table 34-1. i/o lines description pin name pin description type (1) comments mccda command/response i/o/pp/od cmd of an mmc or sd card mcck clock i/o clk of an mmc or sd card mcda0 - mcda3 data 0..3 of slot a i/o/pp dat0 of an mmc dat[0..3] of an sd card 497 6062b?atarm?15-nov-05 at91sam9261 34.5 product dependencies 34.5.1 i/o lines the pins used for interfacing the multimedia cards or sd cards may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the peripheral func- tions to mci pins. 34.5.2 power management the mci may be clocked through the power management controller (pmc), so the program- mer must first to configure the pmc to enable the mci clock. 34.5.3 interrupt the mci interface has an interrupt line connected to the advanced interrupt controller (aic). handling the mci interrupt requires programming the aic before configuring the mci. 34.6 bus topology figure 34-3. multimedia memory card bus topology the multimedia card communication is based on a 7-pin serial bus interface. it has three com- munication lines and four supply lines. note: 1. i: input, o: output, pp : push/pull, od: open drain. table 34-2. bus topology pin number name type (1) description mci pin name (slot x) 1 rsv nc not connected 2 cmd i/o/pp/od command/response mccdx 3 vss1 s supply voltage ground vss 4 vdd s supply voltage vdd 5 clk i/o clock mcck 6 vss2 s supply voltage ground vss 7 dat[0] i/o/pp data 0 mcdx0 23456 17 mmc 498 6062b?atarm?15-nov-05 at91sam9261 figure 34-4. mmc bus connections (one slot) figure 34-5. sd memory card bus topology the sd memory card bus includes the signals listed in table 34-3 . note: 1. i: input, o: output, pp: push pull, od: open drain figure 34-6. sd card bus connections with one slot when the mci is configured to operate with sd me mory cards, the width of the data bus can be selected in the mci_sdcr register. clearing th e sdcbus bit in this register means that 23456 1 7 23456 1 7 23456 17 mccda mcda0 mcck mmc1 mmc2 mmc3 mci table 34-3. sd memory card bus signals pin number name type (1) description mci pin name (slot x) 1 cd/dat[3] i/o/pp card detect/ data line bit 3 mcdx3 2 cmd pp command/response mccdx 3 vss1 s supply voltage ground vss 4 vdd s supply voltage vdd 5 clk i/o clock mcck 6 vss2 s supply voltage ground vss 7 dat[0] i/o/pp data line bit 0 mcdx0 8 dat[1] i/o/pp data line bit 1 mcdx1 9 dat[2] i/o/pp data line bit 2 mcdx2 23456 17 8 sd card 9 23456 17 mcda0 - mcda3 mccda mcck 8 sd card 9 499 6062b?atarm?15-nov-05 at91sam9261 the width is one bit; setting it means that the width is four bits. in the ca se of multimedia cards, only the data line 0 is used. the other data lines can be used as independent pios. 34.7 multimedia card operations after a power-on reset, the cards are initialized by a special message-based multimedia card bus protocol. each message is represented by one of the following tokens: command: a command is a token that starts an operation. a command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). a command is transferred serially on the cmd line. response: a response is a token which is s ent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. a response is transferred serially on the cmd line. data: data can be transferred from the card to the host or vice versa. data is transferred via the data line. card addressing is implemented using a sessi on address assigned during the initialization phase by the bus controller to all currently c onnected cards. their unique cid number identi- fies individual cards. the structure of commands, responses and data blocks is described in the multimedia-card system specification version 2.2. see also table 34-4 on page 500 . multimediacard bus data transfers are composed of these tokens. there are different types of operations. addressed operations always contain a command and a response token. in addition, some operations have a data token; the others transfer their information directly within the command or response structure. in this case, no data token is present in an operation. the bits on the dat and the cmd lines are transferred synchronous to the clock mcck. two types of data transfer commands are defined: sequential commands: these commands initiate a continuous data stream. they are terminated only when a stop command follows on the cmd line. this mode reduces the command overhead to an absolute minimum. block-oriented commands: th ese commands send a data block succeeded by crc bits. both read and write operations allow either single or multiple block transmission. a multiple block transmission is terminated when a stop command follows on the cmd line similarly to the sequential read. the mci provides a set of registers to perform the entire range of multimedia card operations. 34.7.1 command - response operation after reset, the mci is disabled and becomes valid after setting the mcien bit in the mci_cr control register. the bit pwsen saves power by dividing the mci clock by 2 pwsdiv + 1 when the bus is inactive. the command and the response of the card are clocked out with the rising edge of the mcck. all the timings for multimedia card are defined in the multimediacard system specification version 2.2. the two bus modes (open drain and push/pull) needed to process all the operations are defined in the mci command register. the mci_cmdr allows a command to be carried out. 500 6062b?atarm?15-nov-05 at91sam9261 for example, to perform an all_send_cid command: the command all_send_cid and the fields and values for the mci_cmdr control register are described in table 34-4 and table 34-5 . note: bcr means broadcast command with response. the mci_argr contains the argument field of the command. to send a command, the user must perform the following steps: fill the argument regi ster (mci_argr) with the command argument. set the command register (mci_cmdr) (see table 34-5 ). the command is sent immediately after writ ing the command register. the status bit cmdrdy in the status register (mci_sr) is asserted when the command is completed. if the command requires a response, it can be read in the mci response register (mci_rspr). the response size can be from 48 bits up to 136 bits depending on the command. the mci embeds an error detection to prevent any corrupted data during the transfer. the following flowchart shows how to send a command to the card and read the response if needed. in this example, the status register bits are polled but setting the appropriate bits in the interrupt enable register (mci_ier) allows using an interrupt method. host command n id cycles cid cmd s t content crc e z ****** z s t content z z z table 34-4. all_send_cid command description cmd index type argument resp abbreviation command description cmd2 bcr [31:0] stuff bits r2 all_send_cid asks all cards to send their cid numbers on the cmd line table 34-5. fields and values for mci_cmdr command register field value cmdnb (command number) 2 (cmd2) rsptyp (response type) 2 (r2: 136 bits response) spcmd (special command) 0 (not a special command) opcmd (open drain command) 1 maxlat (max latency for command to re sponse) 0 (nid cycles ==> 5 cycles) trcmd (transfer command) 0 (no transfer) trdir (transfer direction) x (available only in transfer command) trtyp (transfer type) x (available only in transfer command) 501 6062b?atarm?15-nov-05 at91sam9261 figure 34-7. command/response functional flow diagram note: 1. if the command is send_op_cond, the crc error flag is always present (refer to r3 response in the multimediacard specification). 34.7.2 data transfer operation the multimedia card allows seve ral read/write operations (single block, multiple blocks, stream, etc.). these operations can be done using the features of the peripheral data controller (pdc). if the pdcmode bit is set in mci_mr, then all reads and writes use the pdc facilities. in all cases, the block length must be defined in the mode register. 34.7.3 read operation the following flowchart shows how to read a single block with or without use of pdc facilities. in this example (see figure 34-8 ), a polling method is used to wait for the end of read. simi- larly, the user can configure the interrupt enable register (mci_ier) to trigger an interrupt at the end of read. these two methods can be applied for all multimedia card read functions. return ok return error (1) set the command argument mci_argr = argument (1) set the command mci_cmdr = command read mci_sr cmdrdy status error flags? read response if required ye s wait for command ready status flag check error bits in the status register (1) 0 1 502 6062b?atarm?15-nov-05 at91sam9261 figure 34-8. read functional flow diagram note: 1. this command is supposed to have been correctly sent (see figure 34-7 ). read status register mci_sr send command sel_desel_card to select the card send command set_blocklen read with pdc reset the pdcmode bit mci_mr &= ~pdcmode set the block length (in bytes) mci_mr |= (blocklenght <<16) number of words to read = 0 ? poll the bit rxrdy = 0? read data = mci_rdr number of words to read = number of words to read -1 send command read_single_block (1) ye s set the pdcmode bit mci_mr |= pdcmode set the block length (in bytes) mci_mr |= (blocklength << 16) configure the pdc channel mci_rpr = data buffer address mci_rcr = blocklength/4 mci_ptcr = rxten send command read_single_block (1) read status register mci_sr poll the bit endrx = 0? ye s return return ye s no no no ye s no number of words to read = blocklength/4 503 6062b?atarm?15-nov-05 at91sam9261 34.7.4 write operation in write operation, the mci mode register (mci_mr) is used to define the padding value when writing non-multiple block size. if the bit pd cpadv is 0, then 0x00 value is used when pad- ding data, otherwise 0xff is used. if set, the bit pdcmode enables pdc transfer. the following flowchart shows how to write a single block with or without use of pdc facilities (see figure 34-9 ). polling or interrup t method can be used to wait for the end of write acco rding to the contents of the interrupt mask register (mci_imr). this flowchart can be adapted to perform all the multimedia card write functions. 504 6062b?atarm?15-nov-05 at91sam9261 figure 34-9. write functional flow diagram note: 1. this command is supposed to have been correctly sent (see figure 34-7 ). send command sel_desel_card to select the card send command set_blocklen write using pdc reset the pdcmode bit mci_mr &= ~pdcmode set the block length mci_mr |= (blocklenght <<16) send command write_single_block (1) set the pdcmode bit mci_mr |= pdcmode set the block length mci_mr |= (blocklength << 16) configure the pdc channel mci_tpr = data buffer address to write mci_tcr = blocklength/4 send command write_single_block (1) read status register mci_sr poll the bit endtx = 0? ye s return no ye s no read status register mci_sr number of words to write = 0 ? poll the bit txrdy = 0? mci_tdr = data to write number of words to write = number of words to write -1 ye s return no ye s no number of words to write = blocklength/4 mci_ptcr = txten 505 6062b?atarm?15-nov-05 at91sam9261 34.8 sd card operations the multimedia card interface allows processing of sd memory card (secure digital memory card) commands. the sd memory card includes a copyright protection mechanism that com- plies with the security requirements of the sdmi standard (secure digital music initiative), is faster and applicable to higher memory capacity. the physical form factor, pin assignment and dat a transfer protocol are forward-com-patible with the multimedia card with some additions. the sd memory card communication is based on a 9-pin interface (clock, command, 4 x data and 3 x power lines). the communication protocol is defined as a part of this specifi- cation. the main difference between the sd memory card and the multimedia card is the initialization process. the sd card register (mci_sd cr) allows selection of the card slot and the data bus width. the sd card bus allows dynamic configuration of the number of data lines. after power up, by default, the sd memory card uses only dat0 for data transfer. after initialization, the host can change the bus width (number of active data lines). 506 6062b?atarm?15-nov-05 at91sam9261 34.9 multimedia card inte rface (mci) user interface note: 1. the response register can be read by n accesses at th e same mci_rspr or at consecutive addresses (0x20 to 0x2c). n depends on the size of the response. table 34-6. mci register mapping offset register register name read/write reset 0x00 control register mci_cr write ? 0x04 mode register mci_mr read/write 0x0 0x08 data timeout register mci_dtor read/write 0x0 0x0c sd card register mci_sdcr read/write 0x0 0x10 argument register mci_argr read/write 0x0 0x14 command register mci_cmdr write ? 0x18 - 0x1c reserved ? ? ? 0x20 response register (1) mci_rspr read 0x0 0x24 response register (1) mci_rspr read 0x0 0x28 response register (1) mci_rspr read 0x0 0x2c response register (1) mci_rspr read 0x0 0x30 receive data register mci_rdr read 0x0 0x34 transmit data register mci_tdr write ? 0x38 - 0x3c reserved ? ? ? 0x40 status register mci_sr read 0xc0e5 0x44 interrupt enable register mci_ier write ? 0x48 interrupt disable register mci_idr write ? 0x4c interrupt mask register mci_imr read 0x0 0x50-0xfc reserved ? ? ? 0x100-0x124 reserved for the pdc ? ? ? 507 6062b?atarm?15-nov-05 at91sam9261 34.9.1 mci control register name: mci_cr access type: write-only mcien: multi-media interface enable 0 = no effect. 1 = enables the multi-media interface if mcdis is 0. mcidis: multi-media interface disable 0 = no effect. 1 = disables the multi-media interface. pwsen: power save mode enable 0 = no effect. 1 = enables the power saving mode if pwsdis is 0. warning: before enabling this mode, the user must set a value different from 0 in the pwsdiv field (mode register mci_mr) . pwsdis: power save mode disable 0 = no effect. 1 = disables the power saving mode. swrst: software reset 0 = no effect. 1 = resets the mci. a software triggered hardware reset of the mci interface is performed. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 swrst ? ? ? pwsdis pwsen mcidis mcien 508 6062b?atarm?15-nov-05 at91sam9261 34.9.2 mci mode register name: mci_mr access type: read/write clkdiv: clock divider multimedia card interface clock (mcck) is master clock (mck) divided by (2*(clkdiv+1)). pwsdiv: power saving divider multimedia card interface clock is divided by 2 (pwsdiv) + 1 when entering power saving mode. warning: this value must be different from 0 before enabling the power save mode in the mci_cr (mci_pwsen bit). pdcpadv: pdc padding value 0 = 0x00 value is used when padding data in write transfer (not only pdc transfer). 1 = 0xff value is used when padding data in write transfer (not only pdc transfer). pdcmode: pdc-oriented mode 0 = disables pdc transfer 1 = enables pdc transfer. in this case, unre and ovre flags in the mci mode register (mci_sr) are deactivated after the pdc transfer has been completed. blklen: data block length this field determines the size of the data block. bits 16 and 17 must be 0. 31 30 29 28 27 26 25 24 ? ? blklen 23 22 21 20 19 18 17 16 blklen 0 0 15 14 13 12 11 10 9 8 pdcmode pdcpadv ? ? ? pwsdiv 76543210 clkdiv 509 6062b?atarm?15-nov-05 at91sam9261 34.9.3 mci data timeout register name: mci_dtor access type: read/write dtocyc: data timeout cycle number dtomul: data timeout multiplier these fields determine the maximum number of master clock cycles that the mci waits between two data block transfers. it equals (dtocyc x multiplier). multiplier is defined by dtomul as shown in the following table: if the data time-out set by dtocyc and dtomul has been exceeded, the data time-out error flag (dtoe) in the mci status register (mci_sr) raises. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? dtomul dtocyc dtomul multiplier 0001 00116 010128 011256 1001024 1014096 1 1 0 65536 1 1 1 1048576 510 6062b?atarm?15-nov-05 at91sam9261 34.9.4 mci sd card register name: mci_sdcr access type: read/write sdcsel: sd card selector 0 = sdcard slot a selected. sdcbus: sd card bus width 0 = 1-bit data bus 1 = 4-bit data bus 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 sdcbus ? ? ? sdcsel 511 6062b?atarm?15-nov-05 at91sam9261 34.9.5 mci argument register name: mci_argr access type: read/write arg: command argument 31 30 29 28 27 26 25 24 arg 23 22 21 20 19 18 17 16 arg 15 14 13 12 11 10 9 8 arg 76543210 arg 512 6062b?atarm?15-nov-05 at91sam9261 34.9.6 mci command register name: mci_cmdr access type: write-only this register is write-protecte d while cmdrdy is 0 in mci_sr. if an interrupt command is sen t, this register is only write- able by an interrupt response (field spcmd). this means that the current command execution cannot be interrupted or modified. cmdnb: command number rsptyp: response type spcmd: special command opdcmd: open drain command 0 = push pull command 1 = open drain command 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? trtyp trdir trcmd 15 14 13 12 11 10 9 8 ? ? ? maxlat opdcmd spcmd 76543210 rsptyp cmdnb rsp response type 0 0 no response. 0 1 48-bit response. 1 0 136-bit response. 1 1 reserved. spcmd command 0 0 0 not a special cmd. 001 initialization cmd: 74 clock cycles for in itialization sequence. 010 synchronized cmd: wait for the end of the current data block transfer before sending the pending command. 011reserved. 100 interrupt command: corresponds to the interrupt mode (cmd40). 101 interrupt response: corresponds to the interrupt mode (cmd40). 513 6062b?atarm?15-nov-05 at91sam9261 maxlat: max latency for command to response 0 = 5-cycle max latency 1 = 64-cycle max latency trcmd: transfer command trdir: transfer direction 0 = write 1 = read trtyp: transfer type trcmd transfer type 0 0 no data transfer 0 1 start data transfer 1 0 stop data transfer 11reserved trtyp transfer type 00block 0 1 multiple block 10stream 11reserved 514 6062b?atarm?15-nov-05 at91sam9261 34.9.7 mci sd response register name: mci_rspr access type: read-only rsp: response note: 1. the response register can be read by n accesses at th e same mci_rspr or at consecutive addresses (0x20 to 0x2c). n depends on the size of the response. 31 30 29 28 27 26 25 24 rsp 23 22 21 20 19 18 17 16 rsp 15 14 13 12 11 10 9 8 rsp 76543210 rsp 515 6062b?atarm?15-nov-05 at91sam9261 34.9.8 mci sd receive data register name: mci_rdr access type: read-only data: data to read 34.9.9 mci sd transmit data register name: mci_tdr access type: write-only data: data to write 31 30 29 28 27 26 25 24 data 23 22 21 20 19 18 17 16 data 15 14 13 12 11 10 9 8 data 76543210 data 31 30 29 28 27 26 25 24 data 23 22 21 20 19 18 17 16 data 15 14 13 12 11 10 9 8 data 76543210 data 516 6062b?atarm?15-nov-05 at91sam9261 34.9.10 mci status register name: mci_sr access type: read-only cmdrdy: command ready 0 = a command is in progress. 1 = the last command has been sent. cleared when writing in the mci_cmdr. rxrdy: receiver ready 0 = data has not yet been received since the last read of mci_rdr. 1 = data has been received since the last read of mci_rdr. txrdy: transmit ready 0= the last data written in mci_tdr has not yet been transferred in the shift register. 1= the last data written in mci_tdr has been transferred in the shift register. blke: data block ended 0 = a data block transfer is not yet finished. 1 = a data block transfer has ended. set at the end of the last block in pdcmode (when rxbuff or txbufe is set), oth- erwise at the end of the first block. cleared when reading the mci_sr. dtip: data transfer in progress 0 = no data transfer in progress. 1 = the current data tran sfer is still in progress, including crc16 calculatio n. cleared at the end of the crc16 calculation. notbusy: data not busy 0 = the card is not ready for new data transfer. 1 = the card is ready for new data transfer (data line dat0 high corresponding to a free data receive buffer in the card). endrx: end of rx buffer 0 = the receive counter register has not reached 0 since the last write in mci_rcr or mci_rncr. 1 = the receive counter register has reached 0 since the last write in mci_rcr or mci_rncr. endtx: end of tx buffer 0 = the transmit counter register has not reached 0 since the last write in mci_tcr or mci_tncr. 1 = the transmit counter register has reached 0 since the last write in mci_tcr or mci_tncr. rxbuff: rx buffer full 31 30 29 28 27 26 25 24 unreovre?????? 23 22 21 20 19 18 17 16 ? dtoe dcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 txbuferxbuff?????? 76543210 endtx endrx notbusy dtip blke txrdy rxrdy cmdrdy 517 6062b?atarm?15-nov-05 at91sam9261 0 = mci_rcr or mci_rncr has a value other than 0. 1 = both mci_rcr and mci_rncr have a value of 0. txbufe: tx buffer empty 0 = mci_tcr or mci_tncr has a value other than 0. 1 = both mci_tcr and mci_tncr have a value of 0. rinde: response index error 0 = no error. 1 = a mismatch is detected between the command index sent and the response index received. cleared when writing in the mci_cmdr. rdire: response direction error 0 = no error. 1 = the direction bit from card to host in the response has not been detected. rcrce: response crc error 0 = no error. 1 = a crc7 error has been detected in the response. cleared when writing in the mci_cmdr. rende: response end bit error 0 = no error. 1 = the end bit of the response has not been detected. cleared when writing in the mci_cmdr. rtoe: response time-out error 0 = no error. 1 = the response time-out set by maxlat in the mci_cmdr has been exceeded. cleared when writing in the mci_cmdr. dcrce: data crc error 0 = no error. 1 = a crc16 error has been detected in the last data block. cleared when sending a new data transfer command. dtoe: data time-out error 0 = no error. 1 = the data time-out set by dtocyc and dtomul in mci_dtor has been exceeded. cleared when writing in the mci_cmdr. ovre: overrun 0 = no error. 1 = at least one 8-bit received data has been lost (not read). cleared when sending a new data transfer command. unre: underrun 0 = no error. 1 = at least one 8-bit data has been sent without valid inform ation (not written). cleared when sending a new data transfer command. 518 6062b?atarm?15-nov-05 at91sam9261 34.9.11 mci interrupt enable register name: mci_ier access type: write-only cmdrdy: command ready interrupt enable rxrdy: receiver ready interrupt enable txrdy: transmit ready interrupt enable blke: data block ended interrupt enable dtip: data transfer in progress interrupt enable notbusy: data not busy interrupt enable endrx: end of receive buffer interrupt enable endtx: end of transmit buffer interrupt enable rxbuff: receive buffer full interrupt enable txbufe: transmit buffer empty interrupt enable rinde: response index error interrupt enable rdire: response direction error interrupt enable rcrce: response crc error interrupt enable rende: response end bit error interrupt enable rtoe: response time-out error interrupt enable dcrce: data crc error interrupt enable dtoe: data time-out error interrupt enable ovre: overrun interrupt enable unre: underrun interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 unreovre?????? 23 22 21 20 19 18 17 16 ? dtoe dcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 txbuferxbuff?????? 76543210 endtx endrx notbusy dtip blke txrdy rxrdy cmdrdy 519 6062b?atarm?15-nov-05 at91sam9261 34.9.12 mci interrupt disable register name: mci_idr access type: write-only cmdrdy: command ready interrupt disable rxrdy: receiver ready interrupt disable txrdy: transmit ready interrupt disable blke: data block ended interrupt disable dtip: data transfer in progress interrupt disable notbusy: data not busy interrupt disable endrx: end of receive buffer interrupt disable endtx: end of transmit buffer interrupt disable rxbuff: receive buffer full interrupt disable txbufe: transmit buffer empty interrupt disable rinde: response index error interrupt disable rdire: response direction error interrupt disable rcrce: response crc error interrupt disable rende: response end bit error interrupt disable rtoe: response time-out error interrupt disable dcrce: data crc error interrupt disable dtoe: data time-out error interrupt disable ovre: overrun interrupt disable unre: underrun interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 unreovre?????? 23 22 21 20 19 18 17 16 ? dtoe dcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 txbuferxbuff?????? 76543210 endtx endrx notbusy dtip blke txrdy rxrdy cmdrdy 520 6062b?atarm?15-nov-05 at91sam9261 34.9.13 mci interrupt mask register name: mci_imr access type: read-only cmdrdy: command ready interrupt mask rxrdy: receiver ready interrupt mask txrdy: transmit ready interrupt mask blke: data block ended interrupt mask dtip: data transfer in progress interrupt mask notbusy: data not busy interrupt mask endrx: end of receive buffer interrupt mask endtx: end of transmit buffer interrupt mask rxbuff: receive buffer full interrupt mask txbufe: transmit buffer empty interrupt mask rinde: response index error interrupt mask rdire: response direction error interrupt mask rcrce: response crc error interrupt mask rende: response end bit error interrupt mask rtoe: response time-out error interrupt mask dcrce: data crc error interrupt mask dtoe: data time-out error interrupt mask ovre: overrun interrupt mask unre: underrun interrupt mask 0 = the corresponding interrupt is not enabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 unreovre?????? 23 22 21 20 19 18 17 16 ? dtoe dcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 txbuferxbuff?????? 76543210 endtx endrx notbusy dtip blke txrdy rxrdy cmdrdy 521 6062b?atarm?15-nov-05 at91sam9261 35. usb host port (uhp) 35.1 description the usb host port (uhp) interfaces the usb with the host application. it handles open hci protocol (open host controller interface) as well as usb v2.0 full-speed and low-speed protocols. the usb host port integrates a root hub and transceivers on downstream ports. it provides several high-speed half-duplex serial communication ports at a baud rate of 12 mbit/s. up to 127 usb devices (printer, camera, mouse, keyboard, disk, etc.) and the usb hub can be con- nected to the usb host in the usb ?tiered star? topology. the usb host port controller is fully compliant with the open hci specification. the standard ohci usb stack driver can be easily ported to atmel?s architecture in the same way all exist- ing class drivers run without hardware specialization. this means that all standard class devices are automatically detected and available to the user application. as an example, integratin g an hid (human interface device) class driver provides a plug & play feature for all usb keyboards and mouses. 35.2 block diagram figure 35-1. block diagram access to the usb host operational registers is achieved through the ahb bus slave interface. the open hci host controller initializes master dma transf ers through the asb bus master interface as follows: fetches endpoint descriptors and transfer descriptors access to endpoint data from system memory access to the hc communication area write status and retire transfer descriptor port s/m port s/m usb transceiver usb transceiver dp dm dp dm embedded usb v2.0 full-speed transceiver root hub and host sie list processor block fifo 64 x 8 hci slave block ohci registers ohci root hub registers asb ed & td regsisters control hci master block data uhp_int mck udpck ahb slave master 522 6062b?atarm?15-nov-05 at91sam9261 memory access errors (abort, misalignment) lead to an ?unrecoverableerror? indicated by the corresponding flag in the host controller operational registers. the usb root hub is integrated in the usb host. several usb downstream ports are available. the number of downstream ports can be determined by the software driver reading the root hub?s operational registers. device connection is automatically detected by the usb host port logic. warning: a pull-down must be connected to dp on the board. otherwise the usb host will permanently detect a device connection on this port. usb physical transceivers are integrated in the product and driven by the root hub?s ports. over current protection on ports can be activated by the usb host controller. atmel?s standard product does not dedicate pads to external over current protection. 35.3 product dependencies 35.3.1 i/o lines dps and dms are not controlled by any pio controllers. the embedded usb physical trans- ceivers are controlled by the usb host controller. 35.3.2 power management the usb host controller requires a 48 mhz clock. this clock must be generated by a pll with a correct accuracy of 0.25%. thus the usb device peripheral receives two clocks from the power management controller (pmc): the master clock mck used to drive the peripheral user interface (mck domain) and the uhpclk 48 mhz clock used to interface with the bus usb signals (recovered 12 mhz domain). 35.3.3 interrupt the usb host interface has an interrupt line connected to the advanced interrupt controller (aic). handling usb host interrupts requires programming the aic before configuring the uhp. 35.4 functional description please refer to the open host controller interface specification for usb release 1.0.a. 35.4.1 host controller interface there are two communication channels between the host controller and the host controller driver. the first channel uses a set of operational registers located on the usb host control- ler. the host controller is the target for all communications on this channel. the operational registers contain control, status and list pointer registers. they are mapped in the memory mapped area. within the operational register set there is a pointer to a location in the proces- sor address space named the host controller communication area (h cca). the hcca is the second communication channel. the host controlle r is the master for all communication on this channel. the hcca contains the head pointers to the interrupt endpoint descriptor lists, the head pointer to the done queue and status information associated with start-of-frame processing. 523 6062b?atarm?15-nov-05 at91sam9261 the basic building blocks for communication across the interface are endpoint descriptors (ed, 4 double words) and transfer descriptors (td, 4 or 8 double words). the host controller assigns an endpoint descriptor to each endpoint in the system. a queue of transfer descrip- tors is linked to the endpoint descriptor for the specific endpoint. figure 35-2. usb host communication channels 35.4.2 host controller driver figure 35-3. usb host drivers operational registers mode hcca status event frame int ratio control bulk host controller communications area interrupt 0 interrupt 1 interrupt 2 interrupt 31 done . . . . . . open hci shared ram device register in memory space device enumeration = transfer descriptor = endpoint descriptor . . . host controller hardware hub driver host controller driver usb driver mini driver class driver class driver user application kernel drivers user space hardware 524 6062b?atarm?15-nov-05 at91sam9261 usb handling is done through several layers as follows: host controller hardware and serial engine: transmit and receive usb data on the bus. host controller driver: drives the host controller hardware and handle the usb protocol usb bus driver and hub driver: handles usb commands and enumeration. offers a hardware independent interface. mini driver: handles device specific commands. class driver: handles standard devices. this acts as a generic driver for a class of devices, for example the hid driver. 35.5 typical connection figure 35-4. board schematic to interface uhp device controller as device connection is automatically detected by the usb host port logic, a pull-down must be connected on dp and dm on the board. otherwis e the usb host will permanently detect a device connection on this port. 47pf 47pf 27 ? hdma or hdmb hdpa or hdpb 27 ? 15k ? 15k ? 10nf 100nf 10 f 5v 0.20a type a connector 525 6062b?atarm?15-nov-05 at91sam9261 36. usb device port (udp) 36.1 description the usb device port (udp) is compliant with th e universal serial bus (usb) v2.0 full-speed device specification. each endpoint can be configured in one of seve ral usb transfer types. it can be associated with one or two banks of a dual-port ram used to store the current data payload. if two banks are used, one dpr bank is read or written by the processor, while the other is read or written by the usb device peripheral. this feature is mandatory for isochronous endpoints. thus the device maintains the maximum bandwidth (1m by tes/s) by working with endpoints with two banks of dpr. suspend and resume are automatically detected by the usb device, which notifies the pro- cessor by raising an interrupt. depending on the product, an external signal can be used to send a wake-up to the usb host controller. table 36-1. usb endpoint description endpoint number mnemonic dual- bank max. endpoint size endpoint type 0 ep0 no 8 control/bulk/interrupt 1 ep1 yes 64 bulk/iso/interrupt 3 ep2 yes 64 bulk/iso/interrupt 3 ep3 no 64 control/bulk/interrupt 4 ep4 yes 256 bulk/iso/interrupt 5 ep5 yes 256 bulk/iso/interrupt 526 6062b?atarm?15-nov-05 at91sam9261 36.2 block diagram figure 36-1. block diagram access to the udp is via the apb bus interface. read and write to the data fifo are done by reading and writing 8-bit values to apb registers. the udp peripheral requires two clocks: one pe ripheral clock used by the mck domain and a 48 mhz clock used by the 12 mhz domain. a usb 2.0 full-speed pad is embedded and controlled by the serial interface engine (sie). the signal external_resume is optional. it allo ws the udp peripheral to wake-up once in sys- tem mode. the host is then notified that the device asks for a resume. this optional feature must be also negotiated with the host during the enumeration. 36.3 product dependencies for further details on the usb device hardware implementation, see the specific product properties document. the usb physical transceiver is integrated into the product. the bidirectional differential sig- nals dp and dm are available from the product boundary. two i/o lines may be used by the application: one to check that vbus is still available from the host. self -powered devices may use this entry to be notified that the host has been powered off. in this case, the board pull-up on dp must be disabled in order to prevent feeding current to the host. one to control the board pull-up on dp. thus, when the device is ready to communicate with the host, it activates its dp pull-up through th is control line. atmel bridge 12 mhz suspend/resume logic w r a p p e r w r a p p e r u s e r i n t e r f a c e serial interface engine sie mck master clock domain dual port ram fifo udpck recovered 12 mhz domain udp_int usb device embedded usb transceiver dp dm external_resume apb to mcu bus txoen eopn txd rxdm rxd rxdp 527 6062b?atarm?15-nov-05 at91sam9261 36.3.1 i/o lines dp and dm are not controlled by any pio controllers. the embedded usb physical trans- ceiver is controlled by the usb device peripheral. to reserve an i/o line to check vbus, the programmer must first program the pio controller to assign this i/o in input pio mode. to reserve an i/o line to control the board pull-up, the programmer must first program the pio controller to assign this i/o in output pio mode. 36.3.2 power management the usb device peripheral requires a 48 mhz cl ock. this clock must be generated by a pll with an accuracy of 0.25%. thus, the usb device receives two clocks from the power management controller (pmc): the master clock, mck, used to drive the peripheral user interface, and the udpck, used to inter- face with the bus usb signals (recovered 12 mhz domain). 36.3.3 interrupt the usb device interface has an interrupt line connected to the advanced interrupt controller (aic). handling the usb device interrupt requires programming the aic before configuring the udp. 36.4 typical connection figure 36-2. board schematic to interface usb device peripheral udp_ cnx is an input signal used to check if the host is connected udp_ pup is an output signal used to disable pull-up on dp by driving it to 0. figure 36-2 shows automatic activation of pull-up after reset. 3v3 15 pf 15 pf 27 ? 33 pf 1.5 k ? 47 k ? 100 nf dm dp pan pam system reset 15 k ? 22 k ? 27 ? type b connector 1 2 34 udp_cnx udp_pup 528 6062b?atarm?15-nov-05 at91sam9261 36.5 functional description 36.5.1 usb v2.0 full-speed introduction the usb v2.0 full-speed provides communication services between host and attached usb devices. each device is offered with a collec tion of communication flows (pipes) associated with each endpoint. software on the host communicates with an usb device through a set of communication flows. figure 36-3. example of usb v2.0 full-speed communication control 36.5.1.1 usb v2.0 full-speed transfer types a communication flow is carried over one of f our transfer types defined by the usb device. 36.5.1.2 usb bus transactions each transfer results in one or more transactions over the usb bus. there are five kinds of transactions flowing acro ss the bus in packets: 1. setup transaction 2. data in transaction 3. data out transaction 4. status in transaction 5. status out transaction ep0 usb host v2.0 software client 1 software client 2 data flow: bulk out transfer data flow: bulk in transfer data flow: control transfer data flow: control transfer ep1 ep2 usb device 2.0 block 1 usb device 2.0 block 2 ep5 ep4 ep0 data flow: isochronous in transfer data flow: isochronous out transfer table 36-2. usb communication flow transfer direction bandw idth endpoint size error detection retrying control bidirectional not guaranteed 8, 16, 32, 64 yes automatic isochronous unidirectional guaranteed 1 - 1023 yes no interrupt unidirectional not guaranteed 64 yes yes bulk unidirectional not guaranteed 8, 16, 32, 64 yes yes 529 6062b?atarm?15-nov-05 at91sam9261 36.5.1.3 usb transfer event definitions as indicated below, transfers are sequential events carried out on the usb bus. notes: 1. control transfer must use endpoints with no ping-pong attributes. 2. isochronous transfers must use endpoints with ping-pong attributes. 3. control transfers can be aborted using a stall handshake. 36.5.2 handling transactions with usb v2.0 device peripheral 36.5.2.1 setup transaction setup is a special type of host-to-device transaction used during control transfers. control transfers must be performed using endpoints with no ping-pong attributes. a setup transaction needs to be handled as soon as possible by the firmware. it is used to transmit requests from the host to the device. these requests are then handled by the usb device and may require more arguments. the arguments are sent to the device by a data out transaction which fol- lows the setup transaction. these requests may also return data. the data is carried out to the host by the next data in transaction which fo llows the setup transaction . a status transaction ends the control transfer. when a setup transfer is received by the usb endpoint: the usb device automatically acknowledges the setup packet rxsetup is set in the udp_ csrx register an endpoint interrupt is generated while the rxsetup is not cleared. this interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint. thus, firmware must detect the rxsetup polling the udp_ csrx or catching an interrupt, read the setup packet in th e fifo, then clear the rxsetu p. rxsetup cannot be cleared before the setup packet has been read in the fifo. otherwise, the usb device would accept the next data out transfer and overwrite the setup packet in the fifo. table 36-3. usb transfer events control transfers (1) (3) setup transaction > data in transactions > status out transaction setup transaction > data out transactions > status in transaction setup transaction > status in transaction interrupt in transfer (device toward host) data in transaction > data in transaction interrupt out transfer (host toward device) data out transaction > data out transaction isochronous in transfer (2) (device toward host) data in transaction > data in transaction isochronous out transfer (2) (host toward device) data out transaction > data out transaction bulk in transfer (device toward host) data in transaction > data in transaction bulk out transfer (host toward device) data out transaction > data out transaction 530 6062b?atarm?15-nov-05 at91sam9261 figure 36-4. setup transaction followed by a data out transaction 36.5.2.2 data in transaction data in transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the device to the host. data in transactions in isochronous transfer must be done using endpoints with ping-pong attributes. using endpoints without ping-pong attributes to perform a data in transaction using a non ping-pong endpoint: 1. the microcontroller checks if it is possible to write in the fifo by polling txpktrdy in the endpoint?s udp_ csrx r egister (txpktrdy must be cleared). 2. the microcontroller writes data to be sent in the endpoint?s fifo, writing zero or more byte values in the endpoint?s udp_ fdrx register, 3. the microcontroller notifi es the usb peripheral it has finished by setting the txpk- trdy in the endpoint?s udp_ csrx register. 4. the microcontroller is notified that the endpoint?s fifo has been released by the usb device when txcomp in the endpoint?s udp_ csrx register has been set. then an interrupt for the corresponding endpoint is pending while txcomp is set. txcomp is set by the usb device when it has received an ack pid signal for the data in packet. an interrupt is pending while txcomp is set. note: refer to chapter 8 of the universal serial bus specification, rev 2.0, for more information on the data in protocol layer. rx_data_bko (udp_csrx) ack pid data out data out pid nak pid ack pid data setup setup pid usb bus packets rxsetup flag set by usb device cleared by firmware set by usb device peripheral fifo (dpr) content data setup data xx xx out interrupt pending setup received setup handled by firmware data out received data out data out pid 531 6062b?atarm?15-nov-05 at91sam9261 figure 36-5. data in transfer for non ping-pong endpoint using endpoints with ping-pong attribute the use of an endpoint with ping-pong attributes is necessary during isochronous transfer. to be able to guarantee a constant bandwidth, the microcontroller must prepare the next data payload to be sent while the current one is bei ng sent by the usb device. thus two banks of memory are used. while one is available for the microcontroller, the other one is locked by the usb device. figure 36-6. bank swapping data in transfer for ping-pong endpoints when using a ping-pong endpoint, the following procedures are required to perform data in transactions: usb bus packets data in 2 data in nak ack data in 1 fifo (dpr) content load in data in 2 load in progress data in 1 cleared by firmware start to write data payload in fifo set by the firmware data payload written in fifo txcomp flag (udp_csrx) txpktrdy flag (udp_csrx) cleared by usb device pid data in data in pid pid pid pid ack pid progress prevous data in tx microcontroller load data in fifo data is sent on usb bus interrupt pending interrupt pending usb device usb bus read write read and write at the same time 1 st data payload 2 nd data payload 3 rd data payload 3 rd data payload 2 nd data payload 1 st data payload data in packet data in packet data in packet microcontroller endpoint 1 bank 0 endpoint 1 bank 1 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 1 532 6062b?atarm?15-nov-05 at91sam9261 1. the microcontroller checks if it is possible to write in the fifo by polling txpktrdy to be cleared in the endpoint?s udp_ csrx register. 2. the microcontroller writes the first data payload to be sent in the fifo (bank 0), writ- ing zero or more byte values in the endpoint?s udp_ fdrx register. 3. the microcontroller notifies the usb peripheral it has finished writing in bank 0 of the fifo by setting the txpktrdy in the endpoint?s udp_ csrx register. 4. without waiting for txpktrdy to be cleared, the microcon troller writes the second data payload to be sent in the fifo (bank 1), writing zero or more byte values in the endpoint?s udp_ fdrx register. 5. the microcontroller is notified that the first bank has been released by the usb device when txcomp in the endpoint?s udp_ csrx register is set. an interrupt is pending while txcomp is being set. 6. once the microcontroller has received txco mp for the first bank, it notifies the usb device that it has prepared the second bank to be sent rising txpktrdy in the end- point?s udp_ csrx register. 7. at this step, bank 0 is available and the microcontroller can prepare a third data pay- load to be sent . figure 36-7. data in transfer for ping-pong endpoint warning: there is software critical pat h due to the fact th at once the second bank is filled, the driver has to wait for tx_comp to set tx_pktrdy. if the delay between receiving tx_comp is set and tx_pktrdy is set is too long, some data in packets may be nacked, reducing the bandwidth. data in data in read by usb device read by usb device bank 1 bank 0 fifo (dpr) txcomp flag (udp_csrx) interrupt cleared by firmware set by usb device txpktrdy flag (udp_mcsrx) ack pid data in pid ack pid set by firmware, data payload written in fifo bank 1 cleared by usb device, data payload fully transmitted data in pid usb bus packets set by usb device set by firmware, data payload written in fifo bank 0 written by fifo (dpr) microcontroller written by microcontroller written by microcontroller microcontroller load data in bank 0 microcontroller load data in bank 1 usb device send bank 0 microcontroller load data in bank 0 usb device send bank 1 interrupt pending 533 6062b?atarm?15-nov-05 at91sam9261 36.5.2.3 data out transaction data out transactions are used in control, isochronous, bulk and interrupt transfers and con- duct the transfer of data from the host to the device. data out transactions in isochronous transfers must be done using endpoints with ping-pong attributes. data out transaction without ping-pong attributes to perform a data out transaction, using a non ping-pong endpoint: 1. the host generates a data out packet. 2. this packet is received by the usb device endpoint. while the fifo associated to this endpoint is being used by the microcontr oller, a nak pid is returned to the host. once the fifo is available, data are written to the fifo by the usb device and an ack is automatically carried out to the host. 3. the microcontroller is notified that the usb device has received a data payload poll- ing rx_data_bk0 in the endpoint?s udp_ csrx register. an interrupt is pending for this endpoint while rx_data_bk0 is set. 4. the number of bytes available in the fifo is made available by reading rxbytecnt in the endpoint?s udp_ csrx register. 5. the microcontroller carries out data received from the endpoint?s memory to its mem- ory. data received is available by reading the endpoint?s udp_ fdrx register. 6. the microcontroller notifies the usb device that it has finished the transfer by clear- ing rx_data_bk0 in the endpoint?s udp_ csrx register. 7. a new data out packet can be accepted by the usb device. figure 36-8. data out transfer for non ping-pong endpoints an interrupt is pending while the flag rx_data_bk0 is set. memory transfer between the usb device, the fifo and microcontroller memory can not be done after rx_data_bk0 has been cleared. otherwise, the usb device would accept the next data out transfer and over- write the current data out packet in the fifo. using endpoints with ping-pong attributes during isochronous transfer, using an endpoint with ping-pong attributes is obligatory. to be able to guarantee a constant bandwidth, the microcontroller must read the previous data pay- ack pid data out nak pid pid pid pid pid data out2 ack data out data out 1 usb bus packets rx_data_bk0 set by usb device cleared by firmware, data payload written in fifo fifo (dpr) content written by usb device microcontroller read data out 1 data out 1 data out 2 host resends the next data payload microcontroller transfers data host sends data payload data out2 data out2 host sends the next data payload written by usb device (udp_csrx) interrupt pending 534 6062b?atarm?15-nov-05 at91sam9261 load sent by the host, while the current data payload is received by the usb device. thus two banks of memory are used. while one is available for the microcontroller, the other one is locked by the usb device. figure 36-9. bank swapping in data out transfers for ping-pong endpoints when using a ping-pong endpoint, the following procedures are required to perform data out transactions: 1. the host generates a data out packet. 2. this packet is received by the usb device endpoint. it is written in the endpoint?s fifo bank 0. 3. the usb device sends an ack pid packet to the host. the host can immediately send a second data out packet. it is accepted by the device and copied to fifo bank 1. 4. the microcontroller is notified that the usb device has received a data payload, poll- ing rx_data_bk0 in the endpoint?s udp_ csrx register. an interrupt is pending for this endpoint while rx_data_bk0 is set. 5. the number of bytes available in the fifo is made available by reading rxbytecnt in the endpoint?s udp_ csrx register. 6. the microcontroller transfers out data received from the endpoint?s memory to the microcontroller?s memory. data received is made available by reading the endpoint?s udp_ fdrx register. 7. the microcontroller notifies the usb peripheral device that it has finished the transfer by clearing rx_data_bk0 in the endpoint?s udp_ csrx register. 8. a third data out packet can be accepted by the usb peripheral device and copied in the fifo bank 0. 9. if a second data out packet has been received, the microcontroller is notified by the flag rx_data_bk1 set in the endpoint?s udp_ csrx register. an interrupt is pending for this endpoint while rx_data_bk1 is set. 10. the microcontroller transfers out data received from the endpoint?s memory to the microcontroller?s memory. data received is available by reading the endpoint?s udp_ fdrx register. usb device usb bus read write write and read at the same time 1 st data payload 2 nd data payload 3 rd data payload 3 rd data payload 2 nd data payload 1 st data payload data in packet data in packet data in packet microcontroller endpoint 1 bank 0 endpoint 1 bank 1 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 0 endpoint 1 bank 1 535 6062b?atarm?15-nov-05 at91sam9261 11. the microcontroller notifies the usb device it has finished the transfer by clearing rx_data_bk1 in the endpoint?s udp_ csrx register. 12. a fourth data out packet can be accepted by the usb device and copied in the fifo bank 0. figure 36-10. data out transfer for ping-pong endpoint note: an interrupt is pending while the rx_data_bk0 or rx_data_bk1 flag is set. warning : when rx_data_bk0 and rx_data_bk1 are both set, there is no way to deter- mine which one to clear first. thus the software must keep an internal counter to be sure to clear alternatively rx_data_bk0 then rx_dat a_bk1. this situation may occur when the software application is busy elsewhere and the two banks are filled by the usb host. once the application comes back to the usb driver, the two flags are set. 36.5.2.4 status transaction a status transaction is a special type of host- to-device transaction used only in a control trans- fer. the control transfer must be performed using endpoints with no ping-pong attributes. according to the control sequence (read or write), the usb device sends or receives a status transaction. a p data out pid ack data out 3 data out data out 2 data out data out 1 pid data out 3 data out 1 data out1 data out 2 data out 2 pid pid pid ack cleared by firmware usb bus packets rx_data_bk0 flag rx_data_bk1 flag set by usb device, data payload written in fifo endpoint bank 1 fifo (dpr) bank 0 bank 1 write by usb device write in progress read by microcontroller read by microcontroller set by usb device, data payload written in fifo endpoint bank 0 host sends first data payload microcontroller reads data 1 in bank 0, host sends second data payload microcontroller reads data2 in bank 1, host sends third data payload cleared by firmware write by usb device fifo (dpr) (udp_csrx) (udp_csrx) interrupt pending interrupt pending 536 6062b?atarm?15-nov-05 at91sam9261 figure 36-11. control read and write sequences notes: 1. during the status in stage, the host waits for a zero le ngth packet (data in transaction with no data) from the device using data1 pid. refer to chapter 8 of the universal serial bus specification, rev. 2.0, for more information on the protocol layer. 2. during the status out stage, the host emits a zero lengt h packet to the device (data out transaction with no data). 36.5.2.5 status in transfer once a control request has been processed, the device returns a status to the host. this is a zero length data in transaction. 1. the microcontroller waits for txpktrdy in the udp_ csrx endpoint?s register to be cleared. (at this step, txpktrdy must be cleared because the pr evious transaction was a setup transaction or a data out transaction.) 2. without writing anything to the udp_ fdrx endpoint?s register, the microcontroller sets txpktrdy. the usb device genera tes a data in packet using data1 pid. 3. this packet is acknowledge d by the host and txpktrdy is set in the udp_ csrx endpoint?s register. control read setup tx data out tx data out tx data stage control write setup stage setup stage setup tx setup tx no data control data in tx data in tx status stage status stage status in tx status out tx status in tx data stage setup stage status stage 537 6062b?atarm?15-nov-05 at91sam9261 figure 36-12. data out followed by status in transfer. 36.5.2.6 status out transfer once a control request has been processed and the requested data returned, the host acknowledges by sending a zero length packet. this is a zero length data out transaction. 1. the usb device receives a zero length packet. it sets rx_data_bk0 flag in the udp_ csrx register and acknowledges the zero length packet. 2. the microcontroller is notified that the usb device has received a zero length packet sent by the host polling rx_data_bk0 in t he udp_ csrx register. an interrupt is pending while rx_data_bk0 is set. the number of bytes received in the endpoint?s udp_ bcr register is equal to zero. 3. the microcontroller must clear rx_data_bk0. figure 36-13. data in followed by status out transfer 36.5.2.7 stall handshake a stall handshake can be used in one of two dist inct occasions. (for more information on the stall handshake, refer to chapter 8 of the universal serial bus specification, rev 2.0. ) data in nak data out data out ack pid pid pid pid usb bus packets rx_data_bko (udp_csrx) cleared by firmware set by usb device cleared by usb device txpktrdy (udp_csrx) set by firmware host sends the last data payload to the device device sends a status in to the host interrupt pending data out data in data in ack pid pid pid ack pid rx_data_bko (udp_csrx) txcomp (udp_csrx) set by usb device usb bus packets cleared by firmware cleared by firmware set by usb device device sends a status out to host device sends the last data payload to host interrupt pending 538 6062b?atarm?15-nov-05 at91sam9261 a functional stall is used when the halt feature associated with the endpoint is set. (refer to chapter 9 of the universal serial bus sp ecification, rev 2.0, for more information on the halt feature.) to abort the current request, a protocol stall is used, but uniquely with control transfer. the following procedure generates a stall packet: 1. the microcontroller sets the forcestall flag in the udp_ csrx endpoint?s register. 2. the host receives the stall packet. 3. the microcontroller is notif ied that the device has se nt the stall by polling the stallsent to be set. an endpoint interrupt is pending while stallsent is set. the microcontroller must clear stallsent to clear the interrupt. when a setup transaction is received after a stall handshake, stallsent must be cleared in order to prevent interrupts due to stallsent being set. figure 36-14. stall handshake (data in transfer) figure 36-15. stall handshake (data out transfer) data in stall pid pid usb bus packets cleared by firmware set by firmware forcestall stallsent set by usb device cleared by firmware interrupt pending data out pid stall pid data out usb bus packets cleared by firmware set by firmware forcestall stallsent set by usb device interrupt pending 539 6062b?atarm?15-nov-05 at91sam9261 36.5.3 controlling device states a usb device has several possible states. refer to chapter 9 of the universal serial bus specification, rev 2.0 . figure 36-16. usb device state diagram movement from one state to another depends on the usb bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). after a period of bus inactivity, the us b device enters suspend mode. accepting sus- pend/resume requests from the usb host is mandatory. constraints in suspend mode are very strict for bus-powered applications; devices may not consume more than 500 ua on the usb bus. while in suspend mode, the host may wake up a device by sending a resume signal (bus activity) or a usb device may send a wake-up request to the host, e.g., waking up a pc by moving a usb mouse. the wake-up feature is not mandatory for all devices and must be negotiated with the host. attached suspended suspended suspended suspended hub reset or deconfigured hub configured bus inactive bus activity bus inactive bus activity bus inactive bus activity bus inactive bus activity reset reset address assigned device deconfigured device configured powered default address configured power interruption 540 6062b?atarm?15-nov-05 at91sam9261 36.5.3.1 from powered state to default state after its connection to a usb host, the usb device waits for an end-of-bus reset. the usb host stops driving a reset state once it has detected the device?s pull-up on dp. the unmasked flag endburses is set in the register udp_isr an d an interrupt is trig gered. the udp soft- ware enables the default endpoint, setting the epeds flag in the udp_csr[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 to the udp_ier register. the enu- meration then begins by a control transfer. 36.5.3.2 from default state to address state after a set address standard device request, the usb host peripheral enters the address state. before this, it achieves the status in transaction of the control transfer, i.e., the udp device sets its new address once the txcomp flag in the udp_csr[0] register has been received and cleared. to move to address state, the driver software sets the fadden flag in the udp_glb_state, sets its new address, and sets the fen bit in the udp_faddr register. 36.5.3.3 from address state to configured state once a valid set configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. this is done by setting the epeds and eptype fields in the udp_csrx registers and, optiona lly, enabling corre- sponding interrupts in the udp_ier register. 36.5.3.4 enabling suspend when a suspend (no bus activity on the usb bus ) is detected, the rxsusp signal in the udp_isr register is set. this triggers an interrupt if the corresponding bit is set in the udp_imr register. this flag is cleared by writing to the ud p_icr register. then the device enters suspend mode. as an example, the microcontroller switc hes to slow clock, disables the pll and main oscillator, and goes into idle mode. it may also switch o ff other devices on the board. the usb device peripheral clocks may be switched off. however, the transceiver and the usb peripheral must not be switched off, otherwise the resume is not detected. 36.5.3.5 receiving a host resume in suspend mode, the usb transceiver and the usb peripheral must be powered to detect the resume. however, the usb device peripheral may not be clocked as the wakeup signal is asynchronous. once the resume is detected on the bus, the signal wakeup in the udp_isr is set. it may generate an interrupt if the corresponding bit in the udp_imr register is set. this interrupt may be used to wake-up the co re, enable pll and main oscilla tors and configure clocks. the wakeup bit must be cleared as soon as possib le by setting wakeup in the udp_icr register. 36.5.3.6 sending an external resume the external resume is negotiated with the host and enabled by setting the esr bit in the udp_ glb_state. an asynchronous event on the ext_resume_pin of the peripheral gener- ates a wakeup interrupt. on early versions of the usp peripheral, the k-state on the usb line is generated immediately. this means that the usb device must be able to answer to the host very quickly. on recent versions, th e software sets the rmwupe bit in the 541 6062b?atarm?15-nov-05 at91sam9261 udp_glb_state register once it is ready to communicate with the host. the k-state on the bus is then generated. the wakeup bit must be cleare d as soon as possible by setting wakeup in the udp_icr register. 542 6062b?atarm?15-nov-05 at91sam9261 36.6 usb device port (udp) user interface notes: 1. the addresses of the udp_ csrx registers ar e calculated as: 0x030 + 4(endpoint number - 1). 2. the addresses of the udp_ fdrx registers are calculated as: 0x050 + 4(endpoint number - 1). table 36-4. udp memory map offset register name access reset state 0x000 frame number register udp_ frm_num read 0x0000_0000 0x004 global state register udp_ glb_stat read/write 0x0000_0010 0x008 function address register udp_ faddr read/write 0x0000_0100 0x00c reserved ? ? ? 0x010 interrupt enable register udp_ ier write 0x014 interrupt disable register udp_ idr write 0x018 interrupt mask register udp_ imr read 0x0000_1200 0x01c interrupt status register udp_ isr read 0x0000_xx00 0x020 interrupt clear register udp_ icr write 0x024 reserved ? ? ? 0x028 reset endpoint register udp_ rst_ep read/write 0x02c reserved ? ? ? 0x030 endpoint 0 control and status register udp_csr0 read/write 0x0000_0000 . . . . . . see note: (1) endpoint 5 control and status register udp_csr5 read/write 0x0000_0000 0x050 endpoint 0 fifo data register udp_ fdr0 read/write 0x0000_0000 . . . . . . see note: (2) endpoint 5 fifo data register udp_ fdr5 read/write 0x0000_0000 0x070 reserved ? ? ? 0x074 transceiver control register udp_ txvc read/write 0x0000_0000 0x078 - 0xfc reserved ? ? ? 543 6062b?atarm?15-nov-05 at91sam9261 36.6.1 udp frame number register register name: udp_ frm_num access type: read-only frm_num[10:0]: frame number as defined in the packet field formats this 11-bit value is incremented by the host on a per fr ame basis. this value is updated at each start of frame. value updated at the sof_eop (start of frame end of packet). frm_err: frame error this bit is set at sof_eop when the sof packet is received containing an error. this bit is reset upon receipt of sof_pid. frm_ok: frame ok this bit is set at sof_eop when the sof packet is received without any error. this bit is reset upon receipt of sof_pid (packet identification). in the interrupt status register, the sof interrupt is updated upon receiving sof_pid. this bit is set without waiting for eop. note: in the 8-bit register interfac e, frm_ok is bit 4 of frm_num_h and frm_err is bit 3 of frm_num_l. 31 30 29 28 27 26 25 24 --- --- --- --- --- --- --- --- 23 22 21 20 19 18 17 16 ??????frm_okfrm_err 15 14 13 12 11 10 9 8 ????? frm_num 76543210 frm_num 544 6062b?atarm?15-nov-05 at91sam9261 36.6.2 udp global state register register name: udp_ glb_stat access type: read/write this register is used to get and set the device state as specified in chapter 9 of the usb serial bus specification, rev.2.0 . fadden: function address enable read: 0 = device is not in address state. 1 = device is in address state. write: 0 = no effect, only a reset can bring back a device to the default state. 1 = sets device in address state. this occurs after a succe ssful set address request. beforehand, the udp_ faddr regis- ter must have been initialized with set address parameters. set address must complete the status stage before setting fadden. refer to chapter 9 of the universal serial bus specification, rev. 2.0 for more details. confg: configured read: 0 = device is not in configured state. 1 = device is in configured state. write: 0 = sets device in a non configured state 1 = sets device in configured state. the device is set in configured state when it is in address st ate and receives a successful set configuration request. refer to chapter 9 of the universal serial bus specification, rev. 2.0 for more details. esr: enable send resume 0 = disables the remote wake up sequence. 1 = remote wake up can be processed and the pin send_resume is enabled. rsminpr: a resume has been sent to the host read: 0 = no effect. 1 = a resume has been received from the host during remote wake up feature. rmwupe: remote wake up enable 0 = must be cleared after receiving any host packet or sof interrupt. 1 = enables the k-state on the usb cable if esr is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ?? 76543210 ? ? ? rmwupe rsminpr esr confg fadden 545 6062b?atarm?15-nov-05 at91sam9261 36.6.3 udp function address register register name: udp_ faddr access type: read/write fadd[6:0]: function address value the function address value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence. refer to the universal serial bus specification, rev. 2.0 for more information. after power up or reset, the function address value is set to 0. fen: function enable read: 0 = function endpoint disabled. 1 = function endpoint enabled. write: 0 = disables function endpoint. 1 = default value. the function enable bit (fen) allows the microcontroller to enable or disable the function endpoints. the microcontroller sets this bit after receipt of a reset from the host. once this bit is set, the usb device is able to accept and transfer data packets from and to the host. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ?fen 76543210 ?fadd 546 6062b?atarm?15-nov-05 at91sam9261 36.6.4 udp interrupt enable register register name: udp_ ier access type: write-only ep0int: enable endpoint 0 interrupt ep1int: enable endpoint 1 interrupt ep2int: enable endpoint 2interrupt ep3int: enable endpoint 3 interrupt ep4int: enable endpoint 4 interrupt ep5int: enable endpoint 5 interrupt 0 = no effect. 1 = enables corresponding endpoint interrupt. rxsusp: enable udp suspend interrupt 0 = no effect. 1 = enables udp suspend interrupt. rxrsm: enable udp resume interrupt 0 = no effect. 1 = enables udp resume interrupt. extrsm: enable external resume interrupt 0 = no effect. 1 = enables external resume interrupt. sofint: enable start of frame interrupt 0 = no effect. 1 = enables start of frame interrupt. wakeup: enable udp bus wakeup interrupt 0 = no effect. 1 = enables usb bus interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup ? sofint extrsm rxrsm rxsusp 76543210 ? ? ep5int ep4int ep3int ep2int ep1int ep0int 547 6062b?atarm?15-nov-05 at91sam9261 36.6.5 udp interrupt disable register register name: udp_ idr access type: write-only ep0int: disable endpoint 0 interrupt ep1int: disable endpoint 1 interrupt ep2int: disable endpoint 2 interrupt ep3int: disable endpoint 3 interrupt ep4int: disable endpoint 4 interrupt ep5int: disable endpoint 5 interrupt 0 = no effect. 1 = disables corresponding endpoint interrupt. rxsusp: disable udp suspend interrupt 0 = no effect. 1 = disables udp suspend interrupt. rxrsm: disable udp resume interrupt 0 = no effect. 1 = disables udp resume interrupt. extrsm: disable external resume interrupt 0 = no effect. 1 = disables external resume interrupt. sofint: disable start of frame interrupt 0 = no effect. 1 = disables start of frame interrupt wakeup: disable usb bus interrupt 0 = no effect. 1 = disables usb bus wakeup interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup ? sofint extrsm rxrsm rxsusp 76543210 ? ? ep5int ep4int ep3int ep2int ep1int ep0int 548 6062b?atarm?15-nov-05 at91sam9261 36.6.6 udp interrupt mask register register name: udp_ imr access type: read-only ep0int: mask endpoint 0 interrupt ep1int: mask endpoint 1 interrupt ep2int: mask endpoint 2 interrupt ep3int: mask endpoint 3 interrupt ep4int: mask endpoint 4 interrupt ep5int: mask endpoint 5 interrupt 0 = corresponding endpoint interrupt is disabled. 1 = corresponding endpoint interrupt is enabled. rxsusp: mask udp suspend interrupt 0 = udp suspend interrupt is disabled. 1 = udp suspend interrupt is enabled. rxrsm: mask udp resume interrupt. 0 = udp resume interrupt is disabled. 1 = udp resume interrupt is enabled. extrsm: mask external resume interrupt 0 = external resume interrupt is disabled. 1 = external resume interrupt is enabled. sofint: mask start of frame interrupt 0 = start of frame interrupt is disabled. 1 = start of frame interrupt is enabled. wakeup: usb bus wakeup interrupt 0 = usb bus wakeup interrupt is disabled. 1 = usb bus wakeup interrupt is enabled. note: when the usb block is in suspend mode, the application may po wer down the usb logic. in this case, any usb host resume request that is made must be taken into account and, thus, the reset value of th e rxrsm bit of the register udp_ imr is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup ? sofint extrsm rxrsm rxsusp 76543210 ? ? ep5int ep4int ep3int ep2int ep1int ep0int 549 6062b?atarm?15-nov-05 at91sam9261 36.6.7 udp interrupt status register register name: udp_ isr access type: read-only ep0int: endpoint 0 interrupt status 0 = no endpoint0 interrupt pending. 1 = endpoint0 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading udp_ csr0: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 ep0int is a sticky bit. interrupt remains valid until ep0int is cleared by writing in the corresponding udp_ csr0 bit. ep1int: endpoint 1 interrupt status 0 = no endpoint1 interrupt pending. 1 = endpoint1 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading udp_ csr1: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 ep1int is a sticky bit. interrupt remains valid until ep1int is cleared by writing in the corresponding udp_ csr1 bit. ep2int: endpoint 2 interrupt status 0 = no endpoint2 interrupt pending. 1 = endpoint2 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading udp_ csr2: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup endbusres sofint extrsm rxrsm rxsusp 76543210 ? ? ep5int ep4int ep3int ep2int ep1int ep0int 550 6062b?atarm?15-nov-05 at91sam9261 txcomp set to 1 stallsent set to 1 ep2int is a sticky bit. interrupt remains valid until ep2int is cleared by writing in the corresponding udp_ csr2 bit. ep3int: endpoint 3 interrupt status 0 = no endpoint3 interrupt pending. 1 = endpoint3 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading udp_ csr3: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 ep3int is a sticky bit. interrupt remains valid until ep3int is cleared by writing in the corresponding udp_ csr3 bit. ep4int: endpoint 4 interrupt status 0 = no endpoint4 interrupt pending. 1 = endpoint4 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading udp_ csr4: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 ep4int is a sticky bit. interrupt remains valid until ep4int is cleared by writing in the corresponding udp_ csr4 bit. ep5int: endpoint 5 interrupt status 0 = no endpoint5 interrupt pending. 1 = endpoint5 interrupt has been raised. several signals can generate this interrupt. the reason can be found by reading udp_ csr5: rxsetup set to 1 rx_data_bk0 set to 1 rx_data_bk1 set to 1 txcomp set to 1 stallsent set to 1 ep5int is a sticky bit. interrupt remains valid until ep5int is cleared by writing in the corresponding udp_ csr5 bit. rxsusp: udp suspend interrupt status 0 = no udp suspend interrupt pending. 1 = udp suspend interrupt has been raised. the usb device sets this bit when it detects no ac tivity for 3ms. the usb device enters suspend mode. rxrsm: udp resume interrupt status 0 = no udp resume interrupt pending. 551 6062b?atarm?15-nov-05 at91sam9261 1 =udp resume interrupt has been raised. the usb device sets this bit when a udp resume signal is detected at its port. after reset, the state of this bit is undefined, the application must clear this bit by setting the rxrsm flag in the udp_ icr register. extrsm: external resume interrupt status 0 = no external resume interrupt pending. 1 = external resume interrupt has been raised. this interrupt is raised when, in suspend mode, an asynchronous rising edge on the send_resume is detected. if rmwupe = 1, a resume state is sent in the usb bus. sofint: start of frame interrupt status 0 = no start of frame interrupt pending. 1 = start of frame interrupt has been raised. this interrupt is raised each time a sof token has been detected. it can be used as a synchronization signal by using isochronous endpoints. endbusres: end of bus reset interrupt status 0 = no end of bus reset interrupt pending. 1 = end of bus reset interrupt has been raised. this interrupt is raised at the end of a udp reset sequence. the usb device must prepare to receive requests on the end- point 0. the host starts the enumeration, then performs the configuration. wakeup: udp resume interrupt status 0 = no wakeup interrupt pending. 1 = a wakeup interrupt (usb host sent a resume or reset) occurred since the last clear. after reset the state of this bit is undefined, the applic ation must clear this bit by sett ing the wakeup flag in the udp_ icr register. 552 6062b?atarm?15-nov-05 at91sam9261 36.6.8 udp interrupt clear register register name: udp_ icr access type: write-only rxsusp: clear udp suspend interrupt 0 = no effect. 1 = clears udp suspend interrupt. rxrsm: clear udp resume interrupt 0 = no effect. 1 = clears udp resume interrupt. extrsm: clear external resume interrupt 0 = no effect. 1 = clears external resume interrupt. sofint: clear start of frame interrupt 0 = no effect. 1 = clears start of frame interrupt. endburses: clear end of bus reset interrupt 0 = no effect. 1 = clears end of bus reset interrupt. wakeup: clear wakeup interrupt 0 = no effect. 1 = clears wakeup interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? wakeup endburses sofint extrsm rxrsm rxsusp 76543210 ???????? 553 6062b?atarm?15-nov-05 at91sam9261 36.6.9 udp reset en dpoint register register name: udp_ rst_ep access type: read/write ep0: reset endpoint 0 ep1: reset endpoint 1 ep2: reset endpoint 2 ep3: reset endpoint 3 ep4: reset endpoint 4 ep5: reset endpoint 5 this flag is used to reset the fifo associated with the endpoint and the bit rxbytecount in the register udp_csrx.it also resets the data toggle to data0. it is useful after removing a halt cond ition on a bulk endpoint. refer to chapter 5.8.5 in the usb serial bus specification, rev.2.0 . warning: this flag must be cleared at the end of the reset. it does not clear udp_ csrx flags. 0 = no reset. 1 = forces the corresponding end point fif0 pointers to 0, ther efore rxbytecnt field is read at 0 in udp_ csrx register. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ?? 76543210 ? ? ep5 ep4 ep3 ep2 ep1 ep0 554 6062b?atarm?15-nov-05 at91sam9261 36.6.10 udp endpoint control and status register register name: udp_ csrx [x = 0.. 5 ] access type: read/write txcomp: generates an in packet with data previously written in the dpr this flag generates an interr upt while it is set to one. write (cleared by the firmware): 0 = clear the flag, clear the interrupt. 1 = no effect. read (set by the usb peripheral): 0 = data in transaction has not been acknowledged by the host. 1 = data in transaction is achieved, acknowledged by the host. after having issued a data in transaction setting txpktrdy, the device firmware waits for txcomp to be sure that the host has acknowledged the transaction. rx_data_bk0: receive data bank 0 this flag generates an interr upt while it is set to one. write (cleared by the firmware): 0 = notify usb peripheral device that data have been read in the fifo's bank 0. 1 = no effect. read (set by the usb peripheral): 0 = no data packet has been received in the fifo's bank 0 1 = a data packet has been received, it has been stored in the fifo's bank 0. when the device firmware has polled this bit or has been interr upted by this signal, it must transfer data from the fifo to the microcontroller memory. the nu mber of bytes received is ava ilable in rxbytcent field. ba nk 0 fifo values are read through the udp_ fdrx register. once a transfer is done, the device firmware must release bank 0 to the usb peripheral device by clearing rx_data_bk0. rxsetup: sends stall to the host (control endpoints) this flag generates an interr upt while it is set to one. read: 0 = no setup packet available. 1 = a setup data packet has been sent by the host and is available in the fifo. write: 0 = device firmware notifies the usb peripheral device that it has read the setup data in the fifo. 1 = no effect. 31 30 29 28 27 26 25 24 ????? r xbytecnt 23 22 21 20 19 18 17 16 rxbytecnt 15 14 13 12 11 10 9 8 epeds ? ? ? dtgle eptype 76543210 dir rx_data_ bk1 force stall txpktrdy stallsent isoerror rxsetup rx_data_ bk0 txcomp 555 6062b?atarm?15-nov-05 at91sam9261 this flag is used to notify the usb device firmware that a valid setup data packet has been sent by the host and success- fully received by the usb device. the usb device firmware ma y transfer setup data from the fifo by reading the udp_ fdrx register to the mi crocontroller memory. once a tr ansfer has been done, rxsetup mu st be cleared by the device firmware. ensuing data out transaction is not accepted while rxsetup is set. stallsent: stall sent (control, bulk interrupt endpoints) / isoerror (isochronous endpoints) this flag generates an interr upt while it is set to one. stallsent: this ends a stall handshake. read: 0 = the host has not acknowledged a stall. 1 = host has acknowledged the stall. write: 0 = resets the stallsent flag, clears the interrupt. 1 = no effect. this is mandatory for the device firmware to clear this flag. otherwise the interrupt remains. refer to chapters 8.4.5 and 9.4.5 of the universal serial bus s pecification, rev. 2.0 for more information on the stall handshake. isoerror: a crc error has been detected in an isochronous transfer. read: 0 = no error in the prev ious isochronous transfer. 1 = crc error has been detected, data available in the fifo are corrupted. write: 0 = resets the isoerror flag, clears the interrupt. 1 = no effect. txpktrdy: transmit packet ready this flag is cleared by the usb device. this flag is set by the usb device firmware. read: 0 = data values can be written in the fifo. 1 = data values can not be written in the fifo. write: 0 = no effect. 1 = a new data payload is has been written in the fifo by the firmware and is ready to be sent. this flag is used to generate a data in transaction (device to host). device firmware checks that it can write a data payload in the fifo, checking that txpktrdy is clear ed. transfer to the fifo is done by writing in the udp_ fdrx register. once the data payload has been transferred to the fifo, the firmwar e notifies the usb device setting txpktrdy to one. usb bus transactions can start. txcomp is set once the data payload has been received by the host. forcestall: force stall (used by control, bulk and isochronous endpoints) write-only 0 = no effect. 1 = sends stall to the host. refer to chapters 8.4.5 and 9.4.5 of the universal serial bus s pecification, rev. 2.0 for more information on the stall handshake. control endpoints: during the data stage and status stage, this indicates that the microcontroller cannot complete the request. 556 6062b?atarm?15-nov-05 at91sam9261 bulk and interrupt endpoints: notifies the host that the endpoint is halted. the host acknowledges the stall, device fi rmware is notified by the stallsent flag. rx_data_bk1: receive data bank 1 (only used by endpoints with ping-pong attributes) this flag generates an interr upt while it is set to one. write (cleared by the firmware): 0 = notifies usb device that data have been read in the fifo?s bank 1. 1 = no effect. read (set by the usb peripheral): 0 = no data packet has been received in the fifo's bank 1. 1 = a data packet has been received, it has been stored in fifo's bank 1. when the device firmware has polled this bit or has been interr upted by this signal, it must transfer data from the fifo to microcontroller memory. the number of bytes received is available in rxbytecnt field. bank 1 fifo values are read through udp_ fdrx register. once a transfer is done, the de vice firmware must release bank 1 to the usb device by clearing rx_data_bk1. dir: transfer direction (only available for control endpoints) read/write 0 = allows data out transactio ns in the control data stage. 1 = enables data in transactions in the control data stage. refer to chapter 8.5.3 of the universal serial bus specification, rev. 2.0 for more information on the control data stage. this bit must be set before udp_ csrx/r xsetup is cleared at the end of the setu p stage. according to the request sent in the setup data packet, the data stage is either a device to host (dir = 1) or host to device (dir = 0) data transfer. it is not necessary to check this bit to reve rse direction for the status stage. eptype[2:0]: endpoint type dtgle: data toggle read-only 0 = identifies data0 packet. 1 = identifies data1 packet. refer to chapter 8 of the universal serial bus specification, rev. 2.0 for more information on data0, data1 packet definitions. epeds: endpoint enable disable read: 0 = endpoint disabled. 1 = endpoint enabled. write: read/write 000 control 001 isochronous out 101 isochronous in 010 bulk out 110 bulk in 011 interrupt out 111 interrupt in 557 6062b?atarm?15-nov-05 at91sam9261 0 = disables endpoint. 1 = enables endpoint. rxbytecnt[10:0]: number of bytes available in the fifo read-only when the host sends a data packet to the device, the usb device stores the data in the fifo and notifies the microcontrol- ler. the microcontroller can lo ad the data from t he fifo by reading rxbytecent byte s in the udp_ fdrx register. 558 6062b?atarm?15-nov-05 at91sam9261 36.6.11 udp fifo data register register name: udp_ fdrx [x = 0..5] access type: read/write fifo_data[7:0]: fifo data value the microcontroller can push or pop values in the fifo through this register. rxbytecnt in the corresponding udp_ csrx register is the num ber of bytes to be read from the fifo (sent by the host). the maximum number of bytes to write is fixed by the max packet size in the standard endpoint descriptor. it can not be more than the physical memory size associated to the endpoint. refer to the universal serial bus specification, rev. 2.0 for more information. 36.6.12 udp transceiver control register register name: udp_ txvc access type: read/write txvdis: transceiver disable when udp is disabled, power consumption can be reduced significantly by disab ling the embedded transceiver. this can be done by setting txvdis field. to enable the transceiver, txvdis must be cleared. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ?? 76543210 fifo_data 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??????? txvdis 76543210 ?????? ?? 559 6062b?atarm?15-nov-05 at91sam9261 37. lcd controller (lcdc) 37.1 description the lcd controller consists of logic for transferring lcd image data from an external display buffer to an lcd module with integrated common and segment drivers. the lcd controller supports single and double scan monochrome and color passive stn lcd modules and single scan active tft lcd modules. on monochrome stn displays, up to 16 gray shades are supported using a time-based dithering algorithm and frame rate control (frc) method. this method is also used in colo r stn displays to generate up to 4096 colors. the lcd controller has a display input buffer (fifo) to allow a flexible connection of the exter- nal ahb master interface, and a lookup table to allow palletized display configurations. the lcd controller is programmable in order to support many different requirements such as resolutions up to 2048 x 2048; pixel depth (1, 2, 4, 8, 16, 24 bits per pixel); data line width (4, 8, 16 or 24 bits) and interface timing. the lcd controller is connected to the arm advanced high performance bus (ahb) as a master for reading pixel data. however, the lcd controller interfaces with the ahb as a slave in order to configure its registers. 560 6062b?atarm?15-nov-05 at91sam9261 37.2 block diagram figure 37-1. lcd macrocell block diagram timegen pwm display cfg ch-l ahb if ch-u ctrl cfg ahb slave display if ahb master split lut mem fifo mem dma controller lcd controller core configuration if control interface lower push fifo serializer palette dithering output shifter ahb slave ahb slave input interface upper push dma data lcdd display if control signals dvalid dvalid ahb clock domain lcdc core clock domain lut mem interface fifo mem interface lut mem interface data pat h 561 6062b?atarm?15-nov-05 at91sam9261 37.3 i/o lines description 37.4 product dependencies 37.4.1 i/o lines the pins used for interfacing the lcd controll er may be multiplexed with pio lines. the pro- grammer must first program the pio controller to assign the pins to their peripheral function. if i/o lines of the lcd controller are not used by the application, they can be used for other pur- poses by the pio controller. 37.4.2 power management the lcd controller is not continuously clocked. the user must first enable the lcd controller clock in the power management controller before using it. as the lcd controller is on the ahb bus, the clock is enabled by setting the hclk bit in the pmc_scer register. 37.4.3 interrupt sources the lcd controller interrupt line is connected to one of the internal sources of the advanced interrupt controller. using the lcd controller interrupt requires prior programming of the aic. 37.5 functional description the lcd controller consists of two main blocks ( figure 37-1 on page 560 ), the dma controller and the lcd controller core (lcdc core). the dma controller reads the display data from an external memory through a ahb master interface. the lcd controller core formats the display data. the lcd controller core continuously pumps the pixel data into the lcd module via the lcd data bus (lcdd[23:0]); this bus is time d by the lcd_pclk, lcd_dval, lcd_hsync, and lcd_vsync signals. 37.5.1 dma controller 37.5.1.1 configuration block the configuration block is a set of programmable registers that are used to configure the dma controller operation. these registers are written via the ahb slave interface. only word access is allowed. for details on the configuration registers, see ?lcd controller (lcdc) us er interface? on page 585 . table 37-1. i/o lines description name description type lcd_cc contrast control signal output lcd_hsync line synchronous signal (stn) or horizontal synchronous signal (tft) output lcd_pclk lcd clock signal (stn/tft) output lcd_vsync frame synchronous signal (stn) or ve rtical synchronization signal (tft) output lcd_dval stn ac bias signal for the driver or data enable signal (tft) output lcd_mod lcd modulation signal output lcd_pwr lcd panel power enable control signal output lcdd[23:0] lcd data bus output output 562 6062b?atarm?15-nov-05 at91sam9261 37.5.1.2 ahb interface this block generates the ahb transactions. it generates undefined-length incrementing bursts as well as 4- ,8- or 16-beat incrementing bursts. the size of the transfer can be configured in the brstln field of the dmafrmcfg register. for details on this register, see ?dma frame configuration register? on page 590 . 37.5.1.3 channel-u this block stores the base address and the number of words transferred for this channel (frame in single scan mode and upper panel in dual scan mode) since the beginning of the frame. it also generates the end of frame signal. it has two pointers, the base address and the num ber of words to transfer. when the module receives a new_frame signal, it reloads the number of words to transfer pointer with the size of the frame/panel. when the module receives the new_frame signal, it also reloads the base address with the base address programmed by the host. the size of the frame/panel can be programme d in the frmsize field of the dmafrmcfg register. this size is calculated as follows: in tft mode: in stn monochrome mode: in stn color mode: where: lineval is the value of the lineval field of the lcdfrmcfg register of lcd controller hozval is the value of the hozval field of the lcdfrmcfg register of the lcd controller e_ifwidth is the number of data bits in the lcd interface for each panel bpp is the bits per pixel configuration 37.5.1.4 channel-l this block has the same functionality as c hannel-u, but for the lower panel in dual scan mode only. 37.5.1.5 control this block receives the request signals from the lcdc core and generates the requests for the channels. frame_size display_size bpp 32 --------------------------------------------------- = frame_size lineval 1 + () hozval 1 + () e_ifwidth bpp 32 ------------------------------------------------------------------------------------------------------------------------------- ------- = frame_size lineval 1 + () hozval 1 + () e_ifwidth 3 --------------------------------------------------------------------- - ?? ?? bpp 32 ------------------------------------------------------------------------------------------------------------------------------ = 563 6062b?atarm?15-nov-05 at91sam9261 37.5.2 lcd controller core 37.5.2.1 configuration block the configuration block is a set of programmable registers that are used to configure the lcdc core operation. these regi sters are written via the ahb slave interface. only word access is allowed. the description of the configuration registers can be found in ?lcd controller (lcdc) user interface? on page 585 . 37.5.2.2 datapath the datapath block contains five submodules: fifo, serializer, palette, dithering and shifter. the structure of the datapath is shown in figure 37-2 . figure 37-2. datapath structure this module transforms the data read from the memory into a format according to the lcd module used. it has four different interfaces: the input interface, the output interface, the con- figuration interface and the control interface. the input interface connects the datapath with the dma controller. it is a dual fifo interface with a data bus and two push lines that are used by the dma controller to fill the fifos. fifo serializer palette dithering output shifter input interface output interface configuration if control interface 564 6062b?atarm?15-nov-05 at91sam9261 the output interface is a 24-bit data bus. the configuration of this interface depends on the type of lcd used (tft or stn, single or dual scan, 4-bit, 8-bit, 16-bit or 24-bit interface). the configuration interface connects the datapath with the configuration block. it is used to select between the different datapath configurations. the control interface connects the datapath with the timing generation block. the main control signal is the data-request signal, used by the timing generation module to request new data from the datapath. the datapath can be characterized by two parameters: initial_latency and cycles_per_data. the parameter initial_latency is defined as the number of lcdc core clock cycles until the first data is available at the output of the da tapath. the parameter cycles_per_data is the min- imum number of lcdc core cl ock cycles between two consec utive data at the output interface. these parameters are different for the different configurations of the lcd controller and are shown in table 37-2 . fifo the fifo block buffers the input data read by the dma module. it contains two input fifos to be used in dual scan configuration that are c onfigured as a single fifo when used in single scan configuration. the size of the fifos allows a wide range of architectures to be supported. the upper threshold of the fifos can be configured in the fifoth field of the lcdfifo reg- ister. the lcdc core will request a dma transfe r when the number of words in each fifo is less than fifoth words. to avoid overwriting in the fifo and to maximize the fifo utiliza- tion, the fifoth should be programmed with: fifoth = 512 words - (2 x dma_burst_length + 3) where: 512 words is the effective size of the fifo. it is the total fifo memory size in single scan mode and half that size in dual scan mode. dma_burst_length is the burst length of the transfers made by the dma table 37-2. datapath parameters configuration initial_latency cycles_per_data distype scan ifwidth tft 9 1 stn mono single 4 13 4 stn mono single 8 17 8 stn mono dual 8 17 8 stn mono dual 16 25 16 stn color single 4 11 2 stn color single 8 12 3 stn color dual 8 14 4 stn color dual 16 15 6 565 6062b?atarm?15-nov-05 at91sam9261 serializer this block serializes the data read from memory. it reads words from the fifo and outputs pixels (1 bit, 2 bits, 4 bits, 8 bits, 16 bits or 24 bits wide) depending on the format specified in the pixelsize field of the lcdcon2 register. it also adapts the memory-ordering format. both big-endian and little-endian formats are supported. they are configured in the memor field of the lcdcon2 register. the organization of the pixel data in the memory depends on the configuration and is shown in table 37-3 and table 37-4 . table 37-3. little endian memory organization mem addr 0x3 0x2 0x1 0x0 bit313029282726252423222120191817161514131211109876543210 pixel 1bpp 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 pixel 2bpp 15 14 13 12 11 10 9 8 7 6 543210 pixel 4bpp 7 6 5 4 3 2 1 0 pixel 8bpp 3 2 1 0 pixel 16bpp 10 pixel 24bpp 10 pixel 24bpp 21 pixel 24bpp 32 pixel 24bpp 54 table 37-4. big endian memory organization mem addr 0x3 0x2 0x1 0x0 bit313029282726252423222120191817161514131211109876543210 pixel 1bpp 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210 pixel 2bpp 0123456789101112131415 pixel 4bpp 0 1 2 3 4 5 6 7 pixel 8bpp 0 1 2 3 pixel 16bpp 01 pixel 24bpp 01 pixel 24bpp 12 pixel 24bpp 23 pixel 24bpp 45 566 6062b?atarm?15-nov-05 at91sam9261 palette this block is used to generate the pixel gray or color information in palletized configurations. the different modes with the palletized/non-palletized configuration can be found in table 37- 5 . in these modes, 1, 2, 4 or 8 input bits index an entry in the lookup table. the corresponding entry in the lookup table contains the color or gray shade information for the pixel. the lookup table can be accessed by the host in r/w mode to allow the host to program and check the values stored in the palette. it is mapped in the lcd controller configuration memory map. the lut is mapped as 16-bit half-words aligned at word boundaries, only word write access is allowed (the 16 msb of the bus are not used). for the detailed memory map, see table 37-12 on page 585 . the lookup table contains 256 16-bit wide entries. the 256 entries are chosen by the program- mer from the 2 16 possible combinations. for the structure of each lut entry, see table 37-6 . in stn monochrome, only the four most significant bits of the red value are used (16 gray shades). in stn color, only the four most significant bits of the blue, green and red value are used (4096 colors). in tft mode, all the bits in the blue, green and red values are used (32768 colors). in this mode, there is also a common intensity bit that c an be used to double the possible colors. this bit is the least significant bit of each co lor component in the lcdd interface (lcdd[18], lcdd[10], lcdd[2]). the lcdd un used bits are tied to 0 when tft palletized configurations are used (lcdd[17:16], lcdd[9:8], lcdd[1:0]). table 37-5. palette configurations configuration palette distype pixelsize tft 1, 2, 4, 8 palletized tft 16, 24 non-palletized stn mono 1, 2 palletized stn mono 4 non-palletized stn color 1, 2, 4, 8 palletized stn color 16 non-palletized table 37-6. lookup table structure in the memory address data output [15:0] 00 intensity_bit_0 blue_value_0[4:0] green_value_0[4:0] red_value_0[4:0] 01 intensity_bit_1 blue_value_1[4:0] green_value_1[4:0] red_value_1[4:0] ... fe intensity_bit_254 blue_value_254[4: 0] green_value_254[4:0] red_value_254[4:0] ff intensity_bit_255 blue_value_255[4: 0] green_value_255[4:0] red_value_255[4:0] 567 6062b?atarm?15-nov-05 at91sam9261 dithering the dithering block is used to generate the shades of gray or color when the lcd controller is used with an stn lcd module. it uses a time-based dithering algorithm and frame rate con- trol method. the frame rate control varies the duty cycle for which a given pi xel is turned on, giving the display an appearance of multiple shades. in order to reduce the flicker noise caused by turn- ing on and off adjacent pixels at the same time , a time-based dithering algorithm is used to vary the pattern of adjacent pixels every frame. this algorithm is expressed in terms of dither- ing pattern registers (dp_i) and considers not only the pixel gray level number, but also its horizontal coordinate. table 37-7 shows the correspondences between the gray levels and the duty cycle. the duty cycles for gray levels 0 and 15 are 0 and 1, respectively. the same dp_i register can be used for the pairs for which the sum of duty cycles is 1 (e.g., 1/7 and 6/7). the dithering pattern for the first pair member is the inversion of the one for the second. the dp_i registers contain a series of 4-bit patterns. the (3-m) th bit of the pattern determines if a pixel with horizontal coordinate x = 4n + m (n is an integer and m ranges from 0 to 3) should be turned on or off in the current frame. the operation is shown by the examples below. consider the pixels a, b, c and d with the horizontal coordinates 4*n+0, 4*n+1, 4*n+2 and 4*n+3, respectively. the four pixels should be displayed in gray level 9 (duty cycle 3/5) so the register used is dp3_5 =?1010 0101 1010 0101 1111?. table 37-7. dithering duty cycle gray level duty cycle pattern register 15 1 - 14 6/7 dp6_7 13 4/5 dp4_5 12 3/4 dp3_4 11 5/7 dp5_7 10 2/3 dp2_3 93/5dp3_5 84/7dp4_7 71/2~dp1_2 63/7~dp4_7 52/5~dp3_5 41/3~dp2_3 31/4~dp3_4 21/5~dp4_5 11/7~dp6_7 00 - 568 6062b?atarm?15-nov-05 at91sam9261 the output sequence obtained in the data output for monochrome mode is shown in table 37- 8 . consider now color display mode and two pixels p0 and p1 with the horizontal coordinates 4*n+0, and 4*n+1. a color pixel is composed of three components: {r, g, b}. pixel p0 will be displayed sending the color comp onents {r0, g0, b0} to the disp lay. pixel p1 will be displayed sending the color components {r1, g1, b1}. suppose that the data read from memory and mapped to the lookup tables corresponds to shade level 10 for the three color components of both pixels, with the dithering pattern to apply to all of them being dp2_3 = ?1101 1011 0110?. table 37-9 shows the output sequence in the data output bus for single scan configurations. (in dual scan configuration, each panel data bus acts like in the equivalent single scan configuration.) table 37-8. dithering algorithm for monochrome mode frame number pattern pixel a pixel b pixel c pixel d n1010onoffonoff n+1 0101 off on off on n+2 1010 on off on off n+3 0101 off on off on n+41111onononon n+5 1010 on off on off n+6 0101 off on off on n+7 1010 on off on off ... ... ... ... ... ... table 37-9. dithering algorithm for color mode frame signal shadow level bit used dithering pattern 4-bit lcdd 8-bit lcdd output n red_data_0 1010 3 1101 lcdd[3] lcdd[7] r0 n green_data_0 1010 2 1101 lcdd[2] lcdd[6] g0 n blue_data_0 1010 1 1101 lcdd[1] lcdd[5] b0 n red_data_1 1010 0 1101 lcdd[0] lcdd[4] r1 n green_data_1 1010 3 1101 lcdd[3] lcdd[3] g1 n blue_data_1 1010 2 1101 lcdd[2] lcdd[2] b1 ?? ? ? ? ? ?? n+1 red_data_0 1010 3 1011 lcdd[3] lcdd[7] r0 n+1 green_data_0 1010 2 1011 lcdd[2] lcdd[6] g0 n+1 blue_data_0 1010 1 1011 lcdd[1] lcdd[5] b0 n+1 red_data_1 1010 0 1011 lcdd[0] lcdd[4] r1 n+1 green_data_1 1010 3 1011 lcdd[3] lcdd[3] g1 n+1 blue_data_1 1010 2 1011 lcdd[2] lcdd[2] b1 ?? ? ? ? ? ?? 569 6062b?atarm?15-nov-05 at91sam9261 note: ri = red pixel component on. gi = green pixel component on. bi = blue pixel component on. ri = red pixel component off. gi = green pixel component off. bi = blue pixel component off. shifter the fifo, serializer, palette and dithering m odules process one pixel at a time in mono- chrome mode and three sub-pixels at a time in color mode (r,g,b components). this module packs the data according to the output interfac e. this interface can be programmed in the distype, scanmod, and ifwidth fields of the ldccon3 register. the distype field selects between tft, stn monochrome and stn color display. the scanmode field selects between single and dual scan modes; in tft mode, only single scan is supported. the ifwidth field configures the width of the interface in stn mode: 4-bit (in single scan mode only), 8-bit and 16-bit (in dual scan mode only). for a more detailed description of the fields, see ?lcd controller (lcdc) user interface? on page 585 . for a more detailed description of the lcd interface, see ?lcd interface? on page 575 . 37.5.2.3 timegen the time generator block generates the control signals lcd_pclk, lcd_hsync, lcd_vsync, lcd_dval, and lcd_ mode, used by the lcd modu le. this blo ck is program- mable in order to support different types of lcd modules and obtain the output clock signals, which are derived from the lcdc core clock. the lcd_mode signal provides an ac signal fo r the display. it is used by the lcd to alter- nate the polarity of the row and column voltages used to turn the pixels on and off. this prevents the liquid crystal from degradation. it can be configured to toggle every frame (bit mmode = 0 in lcdmval register) or to toggle every programmable number of lcd_hsync pulses (bit mmode = 1, number of pulses defined in mval field of lcdmval register). figure 37-3 and figure 37-4 on page 570 show the timing of lcd_mode in both configurations. n+2 red_data_0 1010 3 0110 lcdd[3] lcdd[7] r0 n+2 green_data_0 1010 2 0110 lcdd[2] lcdd[6] g0 n+2 blue_data_0 1010 1 0110 lcdd[1] lcdd[5] b0 n+2 red_data_1 1010 0 0110 lcdd[0] lcdd[4] r1 n+2 green_data_1 1010 3 0110 lcdd[3] lcdd[3] g1 n+2 blue_data_1 1010 2 0110 lcdd[2] lcdd[2] b1 ?? ? ? ? ? ?? table 37-9. dithering algorithm for color mode (continued) frame signal shadow level bit used dithering pattern 4-bit lcdd 8-bit lcdd output f lcd_mode f lcd_hsync 2 mval 1 + () 570 6062b?atarm?15-nov-05 at91sam9261 figure 37-3. full frame timing, mmode=1, mval=1 figure 37-4. full frame timing, mmode=0 the lcd_pclk signal is used to clock the data into the lcd drivers' shift register. the data is sent through lcdd[23:0] synchronized by default with lcd_pc lk falling edge (rising edge can be selected). the clkval field of lcdcon1 register controls the rate of this signal. the divi- sor can also be bypass ed with the bypass bit in the lcdcon1 register. in this case, the rate of lcd_pclk is equal to the frequency of the lcdc core clock. the minimum period of the lcd_pclk signal depends on the configuration. this information can be found in table 37- 10 . the lcd_pclk signal has two different timings that are selected with the clkmod field of the lcdcon2 register: always active (used with tft lcd modules) active only when data is ava ilable (used with stn lcd modules) lcd_vsync lcd_mode lcd_pclk line1 line2 line3 line4 line5 lcd_vsync lcd_mode lcd_pclk line1 line2 line3 line4 line5 table 37-10. minimum lcd_pclk period in lcdc core clock cycles configuration lcd_pclk period distype scan ifwidth tft 1 stn mono single 4 4 stn mono single 8 8 stn mono dual 8 8 stn mono dual 16 16 stn color single 4 2 f lcd_pclk f lcdc_clock 2 clkval 571 6062b?atarm?15-nov-05 at91sam9261 the lcd_dval signal indicates valid data in the lcd interface. after each horizontal line of data has been shifted into the lcd, the lcd_hsync is asserted to cause the line to be displayed on the panel. the following timing parameters can be configured: vertical to horizontal delay (vhdly): the delay between begin_of_line and the generation of lcd_hsync is configurable in the vhdly field of the lcdtim1 register. the delay is equal to (vhdly+1) lcd_pclk cycles. horizontal pulse width (hpw): the lcd_hsync pulse width is configurable in hpw field of lcdtim2 register. the width is eq ual to (hpw + 1) lcd_pclk cycles. horizontal back porch (hbp): the delay between the lcd_hsync falling edge and the first lcd_pclk rising edge with valid data at the lcd interface is configurable in the hbp field of the lcdtim2 register. the dela y is equal to (hbp+1) lcd_pclk cycles. horizontal front porch (hfp): the delay between end of valid data and the end of the line is configurable in the hfp field of the lcdt im2 register. the delay is equal to (hfp+1) lcd_pclk cycles. there is a limitation in the minimum values of vhdly, hpw and hbp parameters imposed by the initial latency of th e datapath. the total del ay in lcdc clock cycles must be hig her than or equal to the latency column in table 37-2 on page 564 . this limitation is given by the following formula: equation 1 where: vhdly, hpw, hbp are the value of the fields of lcdtim1 and lcdtim2 registers pclk_period is the period of lcd_pclk signal measured in lcdc clock cycles dpath_latency is the datapath latency of the configuration, given in table 37-2 on page 564 the lcd_vsync is asserted once pe r frame. this signal is asse rted to cause the lcd's line pointer to start over at the top of the display. the timing of this signal depends on the type of lcd: stn or tft lcd. in stn mode, the high phase corresponds to the complete first line of the frame. in stn mode, this signal is synchronized with the first active lcd_pclk rising edge in a line. in tft mode, the high phase of this signal starts at the beginning of the first line. the following timing parameters can be selected: vertical pulse width (vpw): lcd_vsync pulse width is config urable in vpw field of the lcdtim1 register. the pulse width is equal to (vpw+1) lines. stn color single 8 2 stn color dual 8 4 stn color dual 16 6 table 37-10. minimum lcd_pclk period in lcdc core clock cycles configuration lcd_pclk period distype scan ifwidth vhdly hpw hbp 3 +++ () pclk_period dpath_latency 572 6062b?atarm?15-nov-05 at91sam9261 vertical back porch: number of inactive lines at the beginning of the frame is configurable in vbp field of lcdtim1 register. the number of inacti ve lines is equal to vbp. this field should be programmed with 0 in stn mode. vertical front porch: number of inactive lines at the end of the frame is configurable in vfp field of lcdtim2 register. the number of inactive lines is equal to vfp. this field should be programmed with 0 in stn mode. there are two other parameters to configure in this module, the hozval and the lineval fields of the lcdfrmcfg: hozval configures the number of active lcd_pclk cycles in each line. the number of active cycles in each line is equal to (hozval+1) cycles. the minimum value of this parameter is 1. lineval configures the number of active lines per frame. this number is equal to (lineval+1) lines. the minimum value of this parameter is 1. figure 37-5 , figure 37-6 and figure 37-7 show the timing of lcd_mode, lcd_pclk, lcd_dval, lcd_hsync and lcd_vsync signals: figure 37-5. stn panel timing, clkmod 0 lcd_hsync lcd_vsync lcd_mode lcd_dval lcd_pclk lcdd frame period vhdly+ hbp+1 hpw+1 hfp+1 hozval+1 lcd_pclk lcdd 1 pclk 1/2 pclk 1/2 pclk line period lcd_vsync lcd_mode lcd_hsync lcd_dval 573 6062b?atarm?15-nov-05 at91sam9261 figure 37-6. tft panel timing, clkmod = 0, vpw = 2, vbp = 2, vfp = 1 figure 37-7. tft panel timing (line expanded view), clkmod=1 usually the lcd_frm rate is ab out 70 hz to 75 hz. it is given by the following equation: where: hozval determines de number of lcd_pclk cycles per line lineval determines the number of lcd_hsync cycles per frame, according to the expressions shown below: in stn mode: vhdly+1 hbp+1 hpw+1 hfp+1 hozval+1 lcd_pclk lcdd 1 pclk 1/2 pclk 1/2 pclk line period lcd_vsync lcd_hsync lcd_dval (vpw+1) lines lcd_vsync lcd_pclk lcdd lcd_dval vhdly+1 lcd_hsync vertical fron t porch = vfp lines vertical back porch = vbp lines frame period vhly+1 vbp+1 hpw+1 vfp+1 hozval+1 lcd_pclk lcdd 1 pclk 1/2 pclk 1/2 pclk line period lcd_vsync lcd_hsync lcd_dval 1 f lcd_vsync ---------------------- vhdly hpw hbp hozval hfp 5 +++ ++ f lcd_pclk --------------------------------------------------------------------------------------------------------------------- ?? ?? vbp lineval vfp 1 +++ () hozval horizontal_display_size number_data_lines -------------------------------------------------------------- - 1 ? = 574 6062b?atarm?15-nov-05 at91sam9261 in monochrome mode, horizontal_display_size is equal to the number of horizontal pixels. the number_data_lines is equal to the number of bits of the interface in single scan mode; number_data_lines is equal to half the bits of the interface in dual scan mode. in color mode, horizontal_display_size equals three times the number of horizontal pixels. in tft mode: the frame rate equation is used first without c onsidering the clock periods added at the end beginning or at the end of each line to determine, approximately, the lcd_pclk rate: with this value, the clkval is fixed, as well as the corresponding lcd_pclk rate. then select vhdly, hpw and hbp according to the type of lcd used and ?equation 1? on page 571 . finally, the frame rate is adjusted to 70 hz - 75 hz with the hfp value: the line counting is controlled by the read-onl y field linecnt of lcdcon1 register. the linecnt field decreases by one unit at each falling edge of lcd_hsync. 37.5.2.4 display this block is used to configure the polarity of the data and control signals. the polarity of all clock signals can be configured by lcdcon2[12:8] register setting. the block also generates the lcd_pwr output that can be used to turn the lcd module on and off by software. this signal is controlled by the pwrcon register and respects the num- ber of frames configured in the guard_time field of pwrcon register (pwrcon[7:1]) between the write access to lcd_pwr field (pwrcon[0]) and the activation/deactivation of lcd_pwr output signal. the minimum value for the guard_time field is one frame. this gives the dma controller enough time to fill the fifos before the start of data transfer to the lcd. 37.5.2.5 pwm this block generates the lcd contrast control signal (lcd_cc) to make possible the control of the display's contrast by software. this is an 8-bit pwm (pulse width modulation) signal that can be converted to an analog voltage with a simple passive filter. the pwm module has a free-running counter whose value is compared against a compare register (constrast_val register). if the value in the counter is less than that in the regis- ter, the output brings the value of the polarity (pol) bit in the pwm control register: contrast_ctr. otherwise, the opposite value is output. thus, a periodic waveform with a pulse width proportional to the value in the compare register is generated. lineval vertical_display_size 1 ? = hozval horizontal_display_size 1 ? = lineval vertical_display_size 1 ? = f lcd_pclk hozval 5 + () f lcd_vsync lineval 1 + () () hfp f pclk 1 f lcd_vsync lineval vbp vfp 1 +++ () vhdly vpw vbp hozval 5 +++ + () 575 6062b?atarm?15-nov-05 at91sam9261 due to the comparison mechanism, the output pulse has a width between zero and 255 pwm counter cycles. thus by adding a simple passive filter outside the chip, an analog voltage between 0 and (255/256) vdd can be obtained (for the positive polarity case, or between (1/256) vdd and vdd for the negative polarity case). other voltage values can be obtained by adding active external circuitry. for pwm mode, the frequency of the counter can be adjusted to four different values using field ps of contrast_ctr register. 37.5.3 lcd interface the lcd controller interfaces with the lcd module through the lcd interface ( table 37-11 on page 580 ). the controller supports the following in terface configurations: 24-bit tft single scan, 16-bit stn dual scan mono (color), 8- bit stn dual (single) scan mono (color), 4-bit single scan mono (color). a 4-bit single scan stn display uses 4 parallel data lines to shift data to successive single hor- izontal lines one at a time until the entire frame has been shifted and transferred. the 4 lsb pins of lcd data bus (lcdd [3:0]) can be di rectly connected to the lcd driver; the 20 msb pins (lcdd [23:4]) are not used. an 8-bit single scan stn display uses 8 parallel data lines to shift data to successive single horizontal lines one at a time until the entire frame has been shifted and transferred. the 8 lsb pins of lcd data bus (lcdd [7:0]) can be directly connected to the lcd driver; the 16 msb pins (lcdd [23:8]) are not used. an 8-bit dual scan stn display uses two sets of 4 parallel data lines to shift data to succes- sive upper and lower panel horizontal lines one at a time until the entire frame has been shifted and transferred. the bus lcdd[3:0] is connected to the upper panel data lines and the bus lcdd[7:4] is connected to the lower panel data lines. the rest of the lcd data bus lines (lcdd[23:8]) are not used. a 16-bit dual scan stn display uses two sets of 8 parallel data lines to shift data to succes- sive upper and lower panel horizontal lines one at a time until the entire frame has been shifted and transferred. the bus lcdd[7:0] is connected to the upper panel data lines and the bus lcdd[15:8] is connected to the lower panel data lines. the rest of the lcd data bus lines (lcdd[23:16]) are not used. stn mono displays require one bit of image data per pixel. stn color displays require three bits (red, green and blue) of image data per pixel, resulting in a horizontal shift register of length three times the number of pixels per horizontal line. this rgb or monochrome data is shifted to the lcd driver as consecutive bits via the parallel data lines. a tft single scan display uses up to 24 parallel data lines to shift data to successive horizon- tal lines one at a time until the entire frame has been shifted and transferred. the 24 data lines are divided in three bytes that define the color shade of each color component of each pixel. the lcdd bus is split as lcdd[23:16] for the blue component, lcdd[15:8] for the green com- ponent and lcdd[7:0] for the red component. if the lcd module has lower color resolution (fewer bits per color component), only the most significant bits of each component are used. all these interfaces are shown in figure 37-8 to figure 37-12 . figure 37-8 on page 576 shows the 24-bit single scan tft display timing; figure 37-9 on page 576 shows the 4-bit single scan stn display timing for monochrome and color modes; figure 37-10 on page 577 shows the 8- bit single scan stn display timing for monochrome and color modes; figure 37-11 on page 578 shows the 8-bit dual scan stn display timing for monochrome and color modes; figure 576 6062b?atarm?15-nov-05 at91sam9261 37-12 on page 579 shows the 16-bit dual scan stn display timing for monochrome and color modes. figure 37-8. tft timing (first line expanded view) figure 37-9. single scan monochrome and color 4-bit panel timing (first line expanded view) lcd_vsync lcd_dval lcd_hsync lcd_pclk lcdd [24:16] lcdd [15:8] lcdd [7:0] g0 b0 r0 g1 b1 r1 lcd_vsync lcd_dval lcd_hsync lcd_pclk lcdd [3] lcdd [2] lcdd [1] lcdd [0] p1 p0 p2 p3 p5 p4 p6 p7 lcd_vsync lcd_dval lcd_h sync lcd_pclk lcdd [3] lcdd [2] lcdd [1] lcdd [0] g0 r0 b0 r1 b1 g1 r2 g2 577 6062b?atarm?15-nov-05 at91sam9261 figure 37-10. single scan monochrome and color 8-bit panel timing (first line expanded view) lcdd [7] lcdd [6] lcdd [5] lcdd [4] p1 p0 p2 p3 p9 p8 p10 p11 lcdd [7] lcdd [6] lcdd [5] lcdd [4] g0 r0 b0 r1 r3 b2 g3 b3 lcdd [3] lcdd [2] lcdd [1] lcdd [0] p5 p4 p6 p7 p13 p12 p14 p15 lcdd [3] lcdd [2] lcdd [1] lcdd [0] b1 g1 r2 g2 g4 r4 b4 r5 lcd_vsync lcd_dval lcd_hsync lcd_pclk lcd_vsync lcd_dval lcd_hsync lcd_pclk 578 6062b?atarm?15-nov-05 at91sam9261 figure 37-11. dual scan monochrome and color 8-bit panel timing (first line expanded view) lcdd [7] lcdd [6] lcdd [5] lcdd [4] lp1 lp0 l2 l3 lp5 lp4 lp6 lp7 lcdd [7] lcdd [6] lcdd [5] lcdd [4] lg0 lr0 lb0 lr1 lb1 lg1 lr2 lg2 lcdd [3] lcdd [2] lcdd [1] lcdd [0] up1 up0 up2 up3 up5 up4 up6 up7 lcdd [3] lcdd [2] lcdd [1] lcdd [0] ug0 ur0 ub0 ur1 ub1 ug1 ur2 ug2 lower pane upper pane lower pane upper pane lcd_vsync lcd_dval lcd_hsync lcd_pclk lcd_vsync lcd_dval lcd_hsync lcd_pclk 579 6062b?atarm?15-nov-05 at91sam9261 figure 37-12. dual scan monochrome and color 16-bit pa nel timing (first line expanded view) lcd_vsync lcd_dval lcd_hsync lcd_pclk lcdd [15] lcdd [ 14 ] lcdd [13] lcdd [12] lp1 lp0 lp2 lp3 lp9 lp8 lp10 lp11 lcdd [15] lcdd [ 14 ] lcdd [13] lcdd [12] lg0 lr0 lb0 lr1 lr3 lb2 lg3 lb3 lcdd [11] lcdd [ 10 ] lcdd [9] lcdd [8] lp5 lp4 lp6 lp7 lp13 lp12 lp14 lp15 lcdd [11] lcdd [ 10 ] lcdd [9] lcdd [8] lb1 lg1 lr2 lg2 lg4 lr4 lb4 lr5 lcdd [7] lcdd [ 6 ] lcdd [5] lcdd [4] ug0 ur0 ub0 ur1 ur3 ub2 ug3 ub3 lcdd [3] lcdd [ 2 ] lcdd [1] lcdd [0] ub1 ug1 ur2 ug2 ug4 ur4 ub4 ur5 lower panel upper panel lc dd [7] lcdd [ 6 ] lcdd [5] lcdd [4] up1 up0 up2 up3 up9 up8 up10 up11 lcdd [3] lcdd [ 2 ] lcdd [1] lcdd [0] up5 up4 up6 up7 up13 up12 up14 up15 lower panel upper panel lcd_vsync lcd_dval lc d_hsync lcd_pclk 580 6062b?atarm?15-nov-05 at91sam9261 table 37-11. lcd signal multiplexing lcd data bus 4-bit stn single scan (mono, color) 8-bit stn single scan (mono, color) 8-bit stn dual scan (mono, color) 16-bit stn dual scan (mono, color) 24-bit tft 16-bit tft lcdd[23] lcd_blue7 lcd_blue4 lcdd[22] lcd_blue6 lcd_blue3 lcdd[21] lcd_blue5 lcd_blue2 lcdd[20] lcd_blue4 lcd_blue1 lcdd[19] lcd_blue3 lcd_blue0 lcdd[18] lcd_blue2 intensity bit lcdd[17] lcd_blue1 lcdd[16] lcd_blue0 lcdd[15] lcdlp7 lcd_green7 lcd_green4 lcdd[14] lcdlp6 lcd_green6 lcd_green3 lcdd[13] lcdlp5 lcd_green5 lcd_green2 lcdd[12] lcdlp4 lcd_green4 lcd_green1 lcdd[11] lcdlp3 lcd_green3 lcd_green0 lcdd[10] lcdlp2 lcd_green2 intensity bit lcdd[9] lcdlp1 lcd_green1 lcdd[8] lcdlp0 lcd_green0 lcdd[7] lcd7 lcdlp3 lcdup7 lcd_red7 lcd_red4 lcdd[6] lcd6 lcdlp2 lcdup6 lcd_red6 lcd_red3 lcdd[5] lcd5 lcdlp1 lcdup5 lcd_red5 lcd_red2 lcdd[4] lcd4 lcdlp0 lcdup4 lcd_red4 lcd_red1 lcdd[3] lcd3 lcd3 lcdup3 lcdup3 lcd_red3 lcd_red0 lcdd[2] lcd2 lcd2 lcdup2 lcdup2 lcd_red2 intensity bit lcdd[1] lcd1 lcd1 lcdup1 lcdup1 lcd_red1 lcdd[0] lcd0 lcd0 lcdup0 lcdup0 lcd_red0 581 6062b?atarm?15-nov-05 at91sam9261 37.6 interrupts the lcd controller generates six different irqs. all the irqs are synchronized with the inter- nal lcd core clock. the irqs are: dma memory error irq. generated when the dma receives an error response from an ahb slave while it is doing a data transfer. fifo underflow irq. generated when the serializer tries to read a word from the fifo when the fifo is empty. fifo overwrite irq. generated when the dma co ntroller tries to write a word in the fifo while the fifo is full. dma end of frame irq. generated when the dma controller updates the frame base address pointers. this irq can be used to implement a double-buffer technique. for more information, see ?double-buffer technique? on page 583 . end of line irq. this irq is generated when the lineblank period of each line is reached and the dma controller is in inactive state. end of last line irq. this irq is generated when the lineblank period of the last line of the current frame is reached and the dma controller is in inactive state. each irq can be individually enabled, disabled or cleared, in the lcd_ier (interrupt enable register), lcd_idr (interrupt disable register) and lcd_icr (interrupt clear register) reg- isters. the lcd_imr register contains the mask value for each irq source and the ldc_isr contains the status of each irq source. a more detailed description of these registers can be found in ?lcd controller (lcdc) user interface? on page 585 . 37.7 configuration sequence the dma controller starts to tr ansfer image data when the lcdc core is activated (write to lcd_pwr field of pwrcon register). thus, the user should configure the lcdc core and configure and enable the dma controller prior to activation of the lcd controller. in addition, the image data to be shows should be available when the lcdc core is activated, regardless of the value programmed in the guard_time field of the pwrcon register. to disable the lcd controller, the user should disable the lcdc core and then disable the dma controller. the user should not enable lip again until the lcdc co re is in idle state. this is checked by reading the lcd_busy bit in the pwrcon register. the initialization sequence that the user should follow to make the lcdc work is: create or copy the first image to show in the display buffer memory. if a palletized mode is used, create and store a palette in the internal lcd palette memory( see ?palette? on page 566. configure the lcd controller core without enabling it: ? lcdcon1 register: program the c lkval and bypass fields: these fields control the pixel clock divisor that is used to generate the pixel clock lcd_pclk. the value to program depends on the lcd core clock and on the type and size of the lcd module used. there is a minimum value of the lcd_pclk clock period that depends on the lcd controller configuration, this minimum value can be found in table 37-10 on page 570 . the equations that are used to calculate the value of the pixel clock divisor can be found at the end of the section ?timegen? on page 569 ? lcdcon2 register: program its fields fo llowing their descriptions in the lcd controller user interface se ction below and considering the type of lcd module 582 6062b?atarm?15-nov-05 at91sam9261 used and the desired working mode. consider that not all combinations are possible. ? lcdtim1 and lcdtim2 registers: program their fields according to the datasheet of the lcd module used and with the help of the timegen section in page 10. note that some fields are not applicable to stn modules and must be programmed with 0 values. note also that there is a limitation on the minimum value of vhdly, hpw, hbp that depends on the configuration of the lcdc. ? lcdfrmcfg register: program the dimensions of the lcd module used. ? lcdfifo register: to program it, use the formula in section ?fifo? on page 564 ? lcdmval register: its configuration depends on the lcd module used and should be tuned to improve the image quality in the display ( see ?timegen? on page 569. ) ? dp1_2 to dp6_7 registers: they are only used for stn displays. they contain the dithering patterns used to generate gray shades or colors in these modules. they are loaded with recommended patterns at reset, so it is not necessary to write anything on them. they can be used to improve the image quality in the display by tuning the patterns in each application. ? pwrcon register: this register controls the power-up sequence of the lcd, so take care to use it properly. do not enable the lcd (writing a 1 in lcd_pwr field) until the previous steps and the configuration of the dma have been finished. ? contrast_ctr and contrast_val: use this registers to adjust the contrast of the display, when the lcd_cc line is used. configure the dma controller. the user should configure the base address of the display buffer memory, the size of the ahb transaction and the size of the display image in memory. when the dma is configured the user should enable the dma. to do so the user should configure the following registers: ? dmabaddr1 and dmabaddr2 register s: in single scan mode only dmabaddr1 register must be configured with the base address of the display buffer in memory. in dual scan mode dmabaddr1 should be configured with the base address of th e upper panel display buffer and dmabaddr2 should be configured with the base address of the lower panel display buffer. ? dmafrmcfg register: program the frmsize field. note that in dual scan mode the vertical size to use in the calculatio n is that of each panel. respect to the brstln field, a recommended value is a 4-word burst. ? dmacon register: once both the lcd controller core and the dma controller have been configured, enable the dma controller by writing a ?1? to the dmaen field of this register. finally, enable the lcd controller core by writing a ?1? in the lcd_pwr field of the pwrcon register and do any other action that may be required to turn the lcd module on. 583 6062b?atarm?15-nov-05 at91sam9261 37.8 double-buffer technique the double-buffer technique is used to avoid flic kering while the frame being displayed is updated. instead of using a single buffer, there are two different buffers, the backbuffer (back- ground buffer) and the primary buffer (the buffer being displayed). the host updates the backbuffer while the lcd controller is displaying the primary buffer. when the backbuffer has been updated the host updates the dma base address registers. when using a dual panel lcd module, both base address pointers should be updated in the same frame. there are two possibilities: check the dmafrmptx register to ensure that there is enough time to update the dma base address registers before the end of frame. update the frame base address registers when the end of frame irq is generated. once the host has updated the frame base address registers and the next dma end of frame irq arrives, the backbuffer and the prim ary buffer are swapped and the host can work with the new backbuffer. 584 6062b?atarm?15-nov-05 at91sam9261 37.9 register configuration guide 37.9.1 stn mode example stn color(r,g,b) 320*240, 8-bit single scan, 70 frames/sec, lcd_core clock = 60 mhz data rate : 320*240*70*3/8 = 2.016mhz hozval= ((3*320)/8 ) -1 lineval= 240 -1 clkval = 60mhz/ (2*2.016mhz) = 15 lcdcon1= clkval << 12 lcdcon2 = littleendian | singlescan | stncolor | disp8bit| ps8bpp; lcdtim1 = 0; lcdtim2 = 10 | (10 << 21); lcdfrmcfg = (hozval << 21) | lineval; lcdmval = 0x80000004; dmafrmcfg = (7 << 24) + (320 * 240 * 8) / 32; 37.9.2 tft mode example this example is based on the nec tft color lcd module nl6448bc20-08 . tft 640*480, 16-bit single scan, 60 frames/s ec, pixel clock frequency = [21mhz..29mhz] with a typical value = 25,175mhz. the lcd_core clock must be (2*n)*pixel clock frequency [42mhz..100mhz] hozval = 640 -1 lineval = 240 -1 if lcd_core clock is 50 mhz clkval = 50mhz/ (2*25,175mhz) = 1 vfp = (12 -1), vbp = (31-1), vpw = (2-1), vhdly= (2-1) hfp = (16-1), hbp = (48 -1), hpw= (96-1) lcdcon1= clkval << 12 lcdcon2 = littleendian | clkmod | in vert_clk | invert_line | invert_frm | ps16bpp | singlescan | tft lcdtim1 = vfp | (vbp << 8) | (vpw << 16) | (vhdly << 24) lcdtim2 = hbp | (hpw << 8) | (hfp << 21) lcdfrmcfg = (hozval << 21) | lineval lcdmval = 0 dmafrmcfg = (7 << 24) + (640 * 480* 16) / 32; 585 6062b?atarm?15-nov-05 at91sam9261 37.10 lcd controller (lcdc) user interface table 37-12. lcd controller (lcdc) user interface offset register register name access reset value 0x0 dma base address register 1 dmabaddr1 r/w 0x00000000 0x4 dma base address register 2 dmabaddr2 r/w 0x00000000 0x8 dma frame pointer register 1 dmafrmpt1 read-only 0x00000000 0xc dma frame pointer register 2 dmafrmpt2 read-only 0x00000000 0x10 dma frame address register 1 dmafrmadd1 read-only 0x00000000 0x14 dma frame address register 2 dmafrmadd2 read-only 0x00000000 0x18 dma frame configuration register dmafrmcfg r/w 0x00000000 0x1c dma control register dmacon r/w 0x00000000 0x800 lcd control register 1 lcdcon1 r/w 0x00002000 0x804 lcd control register 2 lcdcon2 r/w 0x00000000 0x808 lcd timing register 1 lcdtim1 r/w 0x00000000 0x80c lcd timing register 2 lcdtim2 r/w 0x00000000 0x810 lcd frame configuration register lcdfrmcfg r/w 0x00000000 0x814 lcd fifo register lcdfifo r/w 0x00000000 0x818 lcd_mode toggle rate value register lcdmval r/w 0x00000000 0x81c dithering pattern dp1_2 dp1_2 r/w 0xa5 0x820 dithering pattern dp4_7 dp4_7 r/w 0x5af0fa5 0x824 dithering pattern dp3_5 dp3_5 r/w 0xa5a5f 0x828 dithering pattern dp2_3 dp2_3 r/w 0xa5f 0x82c dithering pattern dp5_7 dp5_7 r/w 0xfaf5fa5 0x830 dithering pattern dp3_4 dp3_4 r/w 0xfaf5 0x834 dithering pattern dp4_5 dp4_5 r/w 0xfaf5f 0x838 dithering pattern dp6_7 dp6_7 r/w 0xf5ffaff 0x83c power control register pwrcon r/w 0x0000000e 0x840 contrast control register contrast_ctr r/w 0x00000000 0x844 contrast value register contrast_val r/w 0x00000000 0x848 lcd interrupt enable register lcd_ier write-only 0x0 0x84c lcd interrupt disable register lcd_idr write-only 0x0 0x850 lcd interrupt mask register lcd_imr read-only 0x0 0x854 lcd interrupt status register lcd_isr read-only 0x0 0x858 lcd interrupt clear register lcd_icr write-only 0x0 0xc00 palette entry 0 lut entry 0 r/w 0xc04 palette entry 1 lut entry 1 r/w 0xc08 palette entry 2 lut entry 2 r/w 586 6062b?atarm?15-nov-05 at91sam9261 0xc0c palette entry 3 lut entry 3 r/w ?? 0xffc palette entry 255 lut entry 255 r/w table 37-12. lcd controller (lcdc) user interface (continued) offset register register name access reset value 587 6062b?atarm?15-nov-05 at91sam9261 37.10.1 dma base address register 1 name: dmabaddr1 access: read/write reset value: 0x00000000 baddr-u base address for the upper panel in dual scan mode. base address for the complete frame in single scan mode. 37.10.2 dma base address register 2 name: dmabaddr2 access: read/write reset value: 0x00000000 baddr-l base address for the lower panel in dual scan mode only. 31 30 29 28 27 26 25 24 baddr-u 23 22 21 20 19 18 17 16 baddr-u 15 14 13 12 11 10 9 8 baddr-u 76543210 baddr-u 31 30 29 28 27 26 25 24 baddr-l 23 22 21 20 19 18 17 16 baddr-l 15 14 13 12 11 10 9 8 baddr-l 76543210 baddr-l 588 6062b?atarm?15-nov-05 at91sam9261 37.10.3 dma frame pointer register 1 name: dmafrmpt1 access: read-only reset value: 0x00000000 frmpt-u current value of frame pointer for the upper panel in dual scan mode. current value of frame pointer for the complete frame in single scan mode. down count from frmsize to 0. note: this register is read-only and contains the current value of the frame pointer (number of wo rds to the end of the frame). it can be used as an estimation of the number of words transferred from memory for the current frame. 37.10.4 dma frame pointer register 2 name: dmafrmpt2 access: read-only reset value : 0x00000000 frmpt-l current value of frame pointer for the lower panel in dual scan mode only. down count from frmsize to 0. note: this register is read-only and contains the current value of the frame pointer (number of wo rds to the end of the frame). it can be used as an estimation of the number of words transferred from memory for the current frame. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?frmpt-u 15 14 13 12 11 10 9 8 frmpt-u 76543210 frmpt-u 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?frmpt-l 15 14 13 12 11 10 9 8 frmpt-l 76543210 frmpt-l 589 6062b?atarm?15-nov-05 at91sam9261 37.10.5 dma frame address register 1 name: dmafrmadd1 access: read-only reset value: 0x00000000 frmadd-u current value of frame address for the upper panel in dual scan mode. current value of frame address for the complete frame in single scan. note: this register is read-only and contains the current val ue of the last dma transaction in the bus for the panel/frame. 37.10.6 dma frame address register 2 name: dmafrmadd2 access: read-only reset value: 0x00000000 frmadd-l current value of frame address for the lower panel in single scan mode only. note: this register is read-only and contains the current va lue of the last dma transaction in the bus for the panel. 31 30 29 28 27 26 25 24 frmadd-u 23 22 21 20 19 18 17 16 frmadd-u 15 14 13 12 11 10 9 8 frmadd-u 76543210 frmadd-u 31 30 29 28 27 26 25 24 frmadd-l 23 22 21 20 19 18 17 16 frmadd-l 15 14 13 12 11 10 9 8 frmadd-l 76543210 frmadd-l 590 6062b?atarm?15-nov-05 at91sam9261 37.10.7 dma frame c onfiguration register name: dmafrmcfg access: read/write reset value: 0x00000000 frmsize: frame size in single scan mode, this is the frame size in words. in dual scan mode, this is the size of each panel. brstln: burst length program with the desired burst length - 1 31 30 29 28 27 26 25 24 ?brstln 23 22 21 20 19 18 17 16 -frmsize 15 14 13 12 11 10 9 8 frmsize 76543210 frmsize 591 6062b?atarm?15-nov-05 at91sam9261 37.10.8 dma control register name: dmacon access: read/write reset value: 0x00000000 dmaen: dma enable 0: dma is disabled. 1: dma is enabled. dmarst: dma reset (write-only) 0: no effect. 1: reset dma module. dma module should be reset only when disabled and in idle state. dmabusy: dma busy 0: dma module is idle. 1: dma module is busy (doing a transaction on the ahb bus). 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????dmabusydmarstdmaen 592 6062b?atarm?15-nov-05 at91sam9261 37.10.9 lcd control register 1 name: lcdcon1 access: read/write, except linecnt: read-only reset value: 0x00002000 bypass: bypass lcd_pclk divider 0: the divider is not bypa ssed. lcd_pclk frequency def ined by the clkval field. 1: the lcd_pclk divider is bypassed. lcd_pclk frequency is equal to the lcdc clock frequency. clkval: clock divider 9-bit divider for pixel clock (lcd_pclk) frequency. linecnt: line counter (read-only) current value of 11-bit line counter. down count from lineval to 0. 31 30 29 28 27 26 25 24 linecnt 23 22 21 20 19 18 17 16 linecnt clkval 15 14 13 12 11 10 9 8 clkval ???? 76543210 ???????bypass pixel_clock system_clock clkval ( 1 ) 2 ? 593 6062b?atarm?15-nov-05 at91sam9261 37.10.10 lcd control register 2 name: lcdcon2 access: read/write reset value: 0x0000000 distype: display type scanmod: scan mode 0: single scan 1: dual scan ifwidth: interface width (stn) 31 30 29 28 27 26 25 24 memor ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 clkmod ? ? invdval invclk invline invframe invvd 76543210 pixelsize ifwidth scanmod distype distype 0 0 stn monochrome 0 1 stn color 10tft 11reserved ifwidth 0 0 4-bit (only valid in single scan stn mono or color) 0 1 8-bit (only valid in stn mono or color) 1 0 16-bit (only valid in dual scan stn mono or color) 11reserved 594 6062b?atarm?15-nov-05 at91sam9261 pixelsize: bits per pixel invvd: lcdd polarity 0: normal 1: inverted invframe: lcd_vsync polarity 0: normal (active high) 1: inverted (active low) invline: lcd_hsync polarity 0: normal (active high) 1: inverted (active low) invclk: lcd_pclk polarity 0: normal (lcdd fetched at lcd_pclk falling edge) 1: inverted (lcdd fetched at lcd_pclk rising edge) invdval: lcd_dval polarity 0: normal (active high) 1: inverted (active low) clkmod: lcd_pclk mode 0: lcd_pclk only active during active display period 1: lcd_pclk always active memor: memory ordering format 00: big endian 10: little endian pixelsize 0 0 0 1 bit per pixel 0 0 1 2 bits per pixel 0 1 0 4 bits per pixel 0 1 1 8 bits per pixel 1 0 0 16 bits per pixel 1 0 1 24 bits per pixel (only valid in tft mode) 1 1 0 reserved 1 1 1 reserved 595 6062b?atarm?15-nov-05 at91sam9261 37.10.11 lcd timing configuration register 1 name: lcdtim1 access: read/write reset value: 0x0000000 vfp: vertical front porch in tft mode, these bits equal the number of idle lines at the end of the frame. in stn mode, these bits should be set to 0. vbp: vertical back porch in tft mode, these bits equal the number of idle lines at the beginning of the frame. in stn mode, these bits should be set to 0. vpw: vertical synchronization pulse width in tft mode, these bits equa l the vertical synchronizatio n pulse width, given in number of lines. lcd_vsync width is equal to (vpw+1) lines. in stn mode, these bits should be set to 0. vhdly: vertical to horizontal delay in tft mode, this is the delay between lcd_vsync rising or falling edge and lcd_h sync rising edge. delay is (vhdly+1) lcd_pclk cycles. in stn mode, these bits should be set to 0. 31 30 29 28 27 26 25 24 ???? vhdly 23 22 21 20 19 18 17 16 ?? vpw 15 14 13 12 11 10 9 8 vbp 76543210 vfp 596 6062b?atarm?15-nov-05 at91sam9261 37.10.12 lcd timing configuration register 2 name: lcdtim2 access: read/write reset value: 0x0000000 hbp: horizontal back porch number of idle lcd_pclk cycles at the beginning of the line. idle period is (hbp+1) lcd_pclk cycles. hpw: horizontal synch ronization pulse width width of the lcd_hsync pulse, given in lcd_ pclk cycles. width is (hpw+1) lcd_pclk cycles. hfp: horizontal front porch number of idle lcd_pclk cycles at the end of the line. idle period is (hfp+1) lcd_pclk cycles. 31 30 29 28 27 26 25 24 hfp 23 22 21 20 19 18 17 16 hfp ????? 15 14 13 12 11 10 9 8 ?? hpw 76543210 hbp 597 6062b?atarm?15-nov-05 at91sam9261 37.10.13 lcd frame configuration register name: lcdfrmcfg access: read/write reset value: 0x0000000 lineval: vertical size of lcd module lineval = (vertical display size) - 1 in dual scan mode, vertical display size refers to the size of each panel. hozval: horizontal size of lcd module in stn mode: ? hozval = (horizontal display size / nu mber of valid lcdd data line) - 1 ? in stn monochrome mode, horizontal display size = number of horizontal pixels ? in stn color mode, horizontal display size = 3*number of horizontal pixels ? in 4-bit single scan or 8-bit dual scan stn display mode, number of valid lcdd data lines = 4 ? in 8-bit single scan or 16-bit dual scan stn display mode, number of valid lcdd data lines = 8 ? if the value calculated for hozval with the above formula is not an integer, it must be rounded up to the next integer value. in tft mode: ? hozval = horizontal display size 31 30 29 28 27 26 25 24 hozval 23 22 21 20 19 18 17 16 hozval ????? 15 14 13 12 11 10 9 8 ????? lineval 76543210 lineval 598 6062b?atarm?15-nov-05 at91sam9261 37.10.14 lcd fifo register name: lcdfifo access: read/write reset value: 0x0000000 fifoth: fifo threshold must be programmed with: fifoth = 512 words - (2 x dma_burst_length + 3) where: 512 words is the effective size of the fifo. it is the total fifo memory size in single scan mode and half that size in dual scan mode. dma_burst_length is the burst length of the transfers made by the dma. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 fifoth 76543210 fifoth 599 6062b?atarm?15-nov-05 at91sam9261 37.10.15 lcd_mode toggle rate value register name: lcdmval access: read/write reset value: 0x00000000 mval: lcd_mode toggle rate value lcd_mode toggle ra te if mmode = 1. toggle rate is mval + 1 line periods. mmode: lcd_mode toggle rate select 0: each frame 1: rate defined by mval 31 30 29 28 27 26 25 24 mmode??????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 mval 600 6062b?atarm?15-nov-05 at91sam9261 37.10.16 dithering pattern dp1_2 register name: dp1_2 access: read/write reset value: 0xa5 dp1_2: pattern value for ? duty cycle 37.10.17 dithering pattern dp4_7 register name: dp4_7 access: read/write reset value: 0x5af0fa5 dp4_7: pattern value for 4/7 duty cycle 37.10.18 dithering pattern dp3_5 register name: dp3_5 access: read/write reset value: 0xa5a5f dp3_5: pattern value for 3/5 duty cycle 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 dp1_2 31 30 29 28 27 26 25 24 ???? dp4_7 23 22 21 20 19 18 17 16 dp4_7 15 14 13 12 11 10 9 8 dp4_7 76543210 dp4_7 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???? dp3_5 15 14 13 12 11 10 9 8 dp3_5 76543210 dp3_5 601 6062b?atarm?15-nov-05 at91sam9261 37.10.19 dithering pattern dp2_3 register name: dp2_3: dithering pattern dp2_3 register access: read/write reset value: 0xa5f dp2_3: pattern value for 2/3 duty cycle 37.10.20 dithering pattern dp5_7 register name: dp5_7: access: read/write reset value: 0xfaf5fa5 dp5_7: pattern value for 5/7 duty cycle 37.10.21 dithering pattern dp3_4 register name: dp3_4 access: read/write reset value: 0xfaf5 dp3_4: pattern value for 3/4 duty cycle 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???? dp2_3 76543210 dp2_3 31 30 29 28 27 26 25 24 ???? dp5_7 23 22 21 20 19 18 17 16 dp5_7 15 14 13 12 11 10 9 8 dp5_7 76543210 dp5_7 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 dp3_4 76543210 dp3_4 602 6062b?atarm?15-nov-05 at91sam9261 37.10.22 dithering pattern dp4_5 register name: dp4_5 access: read/write reset value: 0xfaf5f dp4_5: pattern value for 4/5 duty cycle 37.10.23 dithering pattern dp6_7 register name: dp6_7 access: read/write reset value: 0xf5ffaff dp6_7: pattern value for 6/7 duty cycle 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???? dp4_5 15 14 13 12 11 10 9 8 dp4_5 76543210 dp4_5 31 30 29 28 27 26 25 24 ???? dp6_7 23 22 21 20 19 18 17 16 dp6_7 15 14 13 12 11 10 9 8 dp6_7 76543210 dp6_7 603 6062b?atarm?15-nov-05 at91sam9261 37.10.24 power control register name: pwrcon access: read/write reset value: 0x0000000e lcd_pwr: lcd module power control 0 = lcd_pwr pin is low, other lcd_* pins are low. 0->1 = lcd_* pins activated, lcd_pwr are set hi gh with the delay of guard_time frame periods. 1 = lcd_pwr pin is high, other lcd_* pins are active 1->0 = lcd_pwr pin is low, other lcd_* pins are ac tive, but are set low after guard_time frame periods. guard_time delay in frame periods between applying control signals to the lcd module and setting lcd_pwr high, and between set- ting lcd_pwr low and removing control signals from lcd module lcd_busy read-only field. if 1, it indicates that the lcd is busy (a ctive and displaying data, in power_on sequence or in power off sequence). 31 30 29 28 27 26 25 24 lcd_busy??????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 guard_time lcd_pwr 604 6062b?atarm?15-nov-05 at91sam9261 37.10.25 contrast control register name: contrast_ctr access: read/write reset value: 0x00000000 ps this 2-bit value selects the configuration of a counter prescaler. the meaning of each combination is as follows: pol this bit defines the polarity of the output. if 1, the ou tput pulses are high level (the out put will be high whenever the value in the counter is less than the value in the compare register constrast_val). if 0, the output pulses are low level. ena when 1, this bit enables the operation of the pwm generator. when 0, the pwm counter is stopped. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????enapol ps ps 0 0 the counter advances at a rate of fcounter = flcdc_clock. 0 1 the counter advances at a rate of fcounter = flcdc_cloc /2. 1 0 the counter advances at a rate of fcounter = flcdc_clock/4. 1 1 the counter advances at a rate of fcounter = flcdc_clock/8. 605 6062b?atarm?15-nov-05 at91sam9261 37.10.26 contrast value register name: constrast_val access: read/write reset value: 0x00000000 cval pwm compare value. used to adjust the analog value obtained after an external filter to control the contrast of the display. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 cval 606 6062b?atarm?15-nov-05 at91sam9261 37.10.27 lcd interrupt enable register name: lcd_ier access: write-only reset value: 0x0 lnie: line interrupt enable 0: no effect 1: enable each line interrupt lstlnie: last line interrupt enable 0: no effect 1: enable last line interrupt eofie: dma end of frame interrupt enable 0: no effect 1: enable end of frame interrupt uflwie: fifo underflow interrupt enable 0: no effect 1: enable fifo u nderflow interrupt owrie: fifo overwrite interrupt enable 0: no effect 1: enable fifo overwrite interrupt merie: dma memory error interrupt enable 0: no effect 1: enable dma memory error interrupt 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? merie owrie uflwie - eofie lstlnie lnie 607 6062b?atarm?15-nov-05 at91sam9261 37.10.28 lcd interrupt disable register name: lcd_idr access: write-only reset value: 0x0 lnid: line interrupt disable 0: no effect 1: disable each line interrupt lstlnid: last line interrupt disable 0: no effect 1: disable last line interrupt eofid: dma end of frame interrupt disable 0: no effect 1: disable end of frame interrupt uflwid: fifo underflow interrupt disable 0: no effect 1: disable fifo un derflow interrupt owrid: fifo overwrite interrupt disable 0: no effect 1: disable fifo overwrite interrupt merid: dma memory error interrupt disable 0: no effect 1: disable dma memo ry error interrupt 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? merid owrid uflwid ? eofid lstlnid lnid 608 6062b?atarm?15-nov-05 at91sam9261 37.10.29 lcd interrupt mask register name: lcd_imr access: read-only reset value: 0x0 lnim: line interrupt mask 0: line interrupt disabled 1: line interrupt enabled lstlnim: last line interrupt mask 0: last line interrupt disabled 1: last line interrupt enabled eofim: dma end of frame interrupt mask 0: end of frame interrupt disabled 1: end of frame interrupt enabled uflwim: fifo underflow interrupt mask 0: fifo underflow interrupt disabled 1: fifo underflow interrupt enabled owrim: fifo overwrite interrupt mask 0: fifo overwrite interrupt disabled 1: fifo overwrite interrupt enabled merim: dma memory error interrupt mask 0: dma memory error interrupt disabled 1: dma memory error interrupt enabled 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?merimowrimuflwim? eofim lstlnim lnim 609 6062b?atarm?15-nov-05 at91sam9261 37.10.30 lcd interrupt status register name: lcd_isr access: read-only reset value: 0x0 lnis: line interrupt status 0: line interrupt not active 1: line interrupt active lstlnis: last line interrupt status 0: last line interrupt not active 1: last line interrupt active eofis: dma end of frame interrupt status 0: end of frame interrupt not active 1: end of frame interrupt active uflwis: fifo underflow interrupt status 0: fifo underflow interrupt not active 1: fifo underflow interrupt active owris: fifo overwrite interrupt status 0: fifo overwrite interrupt not active 1: fifo overwrite interrupt active meris: dma memory error interrupt status 0: dma memory error interrupt not active 1: dma memory error interrupt active 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? meris owris uflwis ? eofis lstlnis lnis 610 6062b?atarm?15-nov-05 at91sam9261 37.10.31 lcd interrupt clear register name: lcd_icr access: write-only reset value: 0x0 lnic: line interrupt clear 0: no effect 1: clear each line interrupt lstlnic: last line interrupt clear 0: no effect 1: clear last line interrupt eofic: dma end of frame interrupt clear 0: no effect 1: clear end of frame interrupt uflwic: fifo underflow interrupt clear 0: no effect 1: clear fifo underflow interrupt owric: fifo overwrite interrupt clear 0: no effect 1: clear fifo overwrite interrupt meric: dma memory error interrupt clear 0: no effect 1: clear dma memory error interrupt 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? meric owric uflwic ? eofic lstlnic lnic 611 6062b?atarm?15-nov-05 at91sam9261 38. at91sam9261 electrical characteristics 38.1 absolute maximum ratings 38.2 dc characteristics the following characteristics are applicable to the operating temperature range: t a = -40c to 85c, unless otherwise spec- ified and are certified for a junction temperature up to t j = 100c. table 38-1. absolute maximum ratings* operating temperature (industrial)........... -40 c to +85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational se ctions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reli- ability. storage temperature ............................... -60c to +150c voltage on input pins with respect to ground ........... ................... -0.3v to +5.5v maximum operating voltage (vddcore and vddbu)........... .............. ........... ..... 1.32v maximum operating voltage (vddosc, vddpll, vddiom and vddiop) ............ 3.6v total dc output current on al l i/o lines ................. 350ma table 38-2. dc characteristics symbol parameter conditions min typ max units v vddcore dc supply core 1.08 1.32 v v vddbu dc supply backup 1.08 1.32 v vddosc dc supply oscillator 2.7 3.6 v v vddpll dc supply pll 2.7 3.6 v v vddiom dc supply memory i/os 2.7 3.6 v v vddiop dc supply peripheral i/os 2.7 3.6 v v il input low-level voltage -0.3 0.8 v v ih input high-level voltage v vddio = v vddiom or v vddiop 2v vddio +0.3 v v ol output low-level voltage 0.4 v v oh output high-level voltage v vddio = v vddiom or v vddiop v vddio -0.4 v i leak input leakage current pullup resistors disabled 1 a c in input capacitance 217-ball lfbga package 5.0 pf r pullup pull-up resistance pa0-pa31, pb0-pb31, pc0-pc31 70 10 175 kohm i o output current pa0-pa31, pb0-pb31, pc0-pc31 8 ma 612 6062b?atarm?15-nov-05 at91sam9261 38.3 power consumption typical power consumption of plls , slow clock and main oscillator. power consumption of power supply in four different modes: active, idle, ultra low-power and backup. power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock. 38.3.1 power consumption versus modes the values in table 38-3 and table 38-4 on page 613 are measured values of power con- sumption with operating conditions as follows: v ddiom = v ddiop = 3.3v v ddpll = v ddosc = 3.3v v ddcore = v ddbu = 1.2v t a = 25 c there is no consumption on the i/os of the device figure 38-1. measures schematics i sc static current on v vddcore = 1.2v, mck = 0 hz, excluding por t a =25c 345 a all inputs driven tms, tdi, tck, nrst = 1 t a =85c 3000 on v vddbu = 1.2v, logic cells consumption, excluding por t a =25c 1.13 a all inputs driven wkup = 0 t a =85c 9.8 table 38-2. dc characteristics (continued) vddcore vddbu amp2 amp1 613 6062b?atarm?15-nov-05 at91sam9261 these figures represent the power consum ption measured on the power supplies. table 38-3. power consumption for different modes (1) mode conditions consumption unit active arm core clock is 200 mhz. mck is 100 mhz. all peripheral clocks activated, including hclk0. cache de-activated. onto amp2 64.1 ma idle arm core in idle state, waiting an interrupt. all peripheral clocks de-activated, including hclk0. cache de-activated. onto amp2 11.2 ma ultra low power arm core clock is 500 hz. all peripheral clocks de-activated, including hclk0. plla and pllb de-activated. onto amp2 400 a backup device only v ddbu powered onto amp1 2.5 a table 38-4. power consumption by peripheral in active mode peripheral consumption unit pio controller 0.5 ma usart 1.5 uhp 2.8 udp 1.3 lcdc 1.3 twi 0.3 spi 0.9 mci 1.3 ssc 1.6 timer counter channels 0.3 614 6062b?atarm?15-nov-05 at91sam9261 38.4 clock characteristics these parameters are given in the following conditions: v ddcore = 1.2v ambient temperature = 25c the temperature derating factor described in ?applicable conditions and derating data? on page 618 , section ?tempera- ture derating factor? on page 619 and v ddcore voltage derating factor described in ?applicable conditions and derating data? on page 618 , section ?vddcore voltage derating factor? on page 619 are both applicable to these characteristics. 38.4.1 processor clock characteristics 38.4.2 master clock characteristics 38.4.3 xin clock characteristics note: 1. these characteristics apply only wh en the main oscillator is in bypass mo de (i.e., when moscen = 0 and oscbypass = 1 in the ckgr_mor register.) table 38-5. processor clock waveform parameters symbol parameter conditions min max units 1/(t cppck ) processor clock frequency 238 mhz t cppck processor clock period 4.19 ns table 38-6. master clock waveform parameters symbol parameter conditions min max units 1/(t cpmck ) master clock frequency 119 mhz t cpmck master clock period 8.38 ns table 38-7. xin clock electrical characteristics symbol parameter conditions min max units 1/(t cpxin ) xin clock frequency 50.0 mhz t cpxin xin clock period 20.0 ns t chxin xin clock high half-period 0.4 x t cpxin 0.6 x t cpxin t clxin xin clock low half-period 0.4 x t cpxin 0.6 x t cpxin c in xin input capacitance (1) 25 pf r in xin pulldown resistor (1) 500 k ? 615 6062b?atarm?15-nov-05 at91sam9261 38.5 crystal oscillat or characteristics the following characteristics are applicabl e to the operating temperature range: t a = -40c to 85c and worst case of power supply, unless otherwise specified. 38.5.1 32 khz oscillator characteristics note: 1. r s is the equivalent series resistance, c l is the equivalent load capacitance. 38.5.2 main oscillators characteristics notes: 1. c s is the shunt capacitance 38.5.3 pll characteristics note: 1. startup time depends on pll rc filter. a calculation tool is provided by atmel. table 38-8. 32 khz oscillator characteristics symbol parameter conditions min typ max unit 1/(t cp32khz ) crystal oscillator frequency 32 768 khz duty cycle 40 60 % t st startup time v ddosc = 3.3v r s = 50 k ? , c l = 12.5 pf (1) 900 ms table 38-9. main oscillator characteristics symbol parameter conditions min typ max unit 1/(t cpmain ) crystal oscillator frequency 3 16 20 mhz c l1 , c l2 internal load capacitance (c l1 = c l2 ) 25 pf c l equivalent load capacitance 12.5 pf duty cycle 40 50 60 % t st startup time v ddpll = 3 to 3.6v c s = 3 pf (1) 1/(t cpmain ) = 3 mhz c s = 7 pf (1) 1/(t cpmain ) = 8mhz c s = 7 pf (1) 1/(t cpmain ) = 16 mhz c s = 7 pf (1) 1/(t cpmain ) = 20 mhz 14.5 4 1.4 1 ms i osc current consumption active mode @20mhz 450 650 a standby mode @3.6v 1 a table 38-10. phase lock loop characteristics symbol parameter conditions min typ max unit f out output frequency field out of ckgr_pll is 00 80 200 mhz field out of ckgr_pll is 10 190 240 mhz f in input frequency 1 32 mhz i pll current consumption active mode 3 ma standby mode 1 a 616 6062b?atarm?15-nov-05 at91sam9261 38.6 usb transceiver characteristics 38.6.1 electrical characteristics 38.6.2 switching characteristics table 38-11. electrical parameters symbol parameter conditions min typ max unit input levels v il low level 0.8 v v ih high level 2.0 v v di differential input sensivity |(d+) - (d-)| 0.2 v v cm differential input common mode range 0.8 2.5 v c in transceiver capacitance capacitance to ground on each line 9.18 pf i hi-z state data line leakage 0v < v in < 3.3v - 10 + 10 a r ext recommended external usb series resistor in series with each usb pin with 5% 27 ? output levels v ol low level output measured with r l of 1.425 k ? tied to 3.6v 0.0 0.3 v v oh high level output measured with r l of 14.25 k ? tied to gnd 2.8 3.6 v v crs output signal crossover voltage measure conditions described in figure 38-2 1.3 2.0 v table 38-12. in low speed symbol parameter conditions min typ max unit t fr transition rise time c load = 400 pf 75 300 ns t fe transition fall time c load = 400 pf 75 300 ns t frfm rise/fall time matching c load = 400 pf 80 125 % table 38-13. in full speed symbol parameter conditions min typ max unit t fr transition rise time c load = 50 pf 4 20 ns t fe transition fall time c load = 50 pf 4 20 ns t frfm rise/fall time matching 90 111.11 % 617 6062b?atarm?15-nov-05 at91sam9261 figure 38-2. usb data signal rise and fall times 10% 10% 90% v crs t r t f differential data lines rise time fall time fosc = 6 mhz/750khz r ext = 39 ohms c load buffer (b) (a) 618 6062b?atarm?15-nov-05 at91sam9261 39. at91sam9261 ac characteristics 39.1 applicable conditi ons and derating data these conditions and derating process apply to the following paragraphs: clock characteris- tics and jtag/ice timings. 39.1.1 conditions and timings computation the delays are given as typical values under the following conditions: v ddiom = 3.3v v ddcore = 1.2v ambient temperature = 25c load capacitance = 0 pf the output level change detection is (0.5 x v ddiom ). the input level is 0.8v for a low-level dete ction and is 2.0v for a high-level detection. the minimum and maximum values given in the ac characteristics tables of this datasheet take into account process variation and design. in order to obtain the timingfor other condi- tions, the following equation should be used: where: t is the derating factor in temperature given in figure 39-1 on page 619 . vddcore is the derating factor for the core power supply given in figure 39-2 on page 619 . t datasheet is the minimum or maximum timing val ue given in this datasheet for a load capacitance of 0 pf. vddiom is the derating factor for the iom power supply given in figure 39-3 on page 620 . c signa l is the capacitance load on the considered output pin (1) . csignal is the load derating factor depending on the capacitance load on the related output pins given in min and max in this datasheet. the input delays are given as typical values. note: 1. the user must take into account the package capacitance load contribution (c in ) described in ?dc characteristics? on page 611 , table 38-2 on page 611 . t t vddcore t datasheet () vddio m c signal csignal () ?? ?? ?? ?? 619 6062b?atarm?15-nov-05 at91sam9261 39.1.2 temperature derating factor figure 39-1. derating curve for different operating temperatures 39.1.3 v ddcore voltage derating factor figure 39-2. derating curve for different core supply voltages 0.8 0.9 1 1.1 1.2 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 operating temperature (c) derating factor 0.85 1 1.15 1.08 1.1 1.12 1.14 1.16 1.18 1.2 1.22 1.24 1.26 1.28 1.3 1.32 core supply voltage (v) derating factor 620 6062b?atarm?15-nov-05 at91sam9261 39.1.4 v ddiom and v ddiop voltage derating factor figure 39-3. derating curve for differe nt io supply voltages) note: the derating factor in this example is applicable only to timings related to output pins. 0.9 0.95 1 1.05 1.1 1.15 3 3.1 3.2 3.3 3.4 3.5 3.6 vddiom supply voltage (v) derating factor 621 6062b?atarm?15-nov-05 at91sam9261 39.2 ebi timings 39.2.1 smc signals relative to mck the following tables show timings relative to oper ating condition limits defined in the section ?conditions and timings computation? on page 618 . table 39-1. access type independent smc signals symbol parameter conditions min max units smc 1 mck rising to a2-a25 valid c add = 0 pf 7.78 ns c add derating 0.0336 ns/pf smc 2 mck rising to nbs0/a0 valid c nbs0 = 0 pf 5.21 ns c nbs0 derating 0.0336 ns/pf smc 3 mck rising to nbs1 valid c nbs1 = 0 pf 5.36 ns c nbs1 derating 0.0336 ns/pf smc 4 mck rising to a1/nbs2 valid c nbs2 = 0 pf 5.31 ns c nbs2 derating 0.0336 ns/pf smc 5 mck rising to nbs3 valid c nbs3 = 0 pf 5.2 ns c nbs3 derating 0.0336 ns/pf smc 6 mck rising to ncs falling c ncs = 0 pf 4.95 ns c ncs derating 0.0336 ns/pf smc 7 mck rising to ncs rising c ncs = 0 pf 5.32 ns c ncs derating 0.0336 ns/pf smc 8 mck rising to nrd falling c nrd = 0 pf 4.90 ns c nrd derating 0.0336 ns/pf smc 9 mck rising to nrd rising c nrd = 0 pf 4.98 ns c nrd derating 0.0336 ns/pf smc 10 mck rising to nwr falling c nwr = 0 pf 5.31 ns c nwr derating 0.0336 ns/pf smc 11 mck rising to nwr rising c nwr = 0 pf 5.37 ns c nwr derating 0.0336 ns/pf smc 12 nwait minimum pulse width 2 x t cpmck ns 622 6062b?atarm?15-nov-05 at91sam9261 table 39-2. smc read signals with hold settings symbol parameter conditions min max units nrd controlled (read_mode = 1) smc 13 data setup before mck rising (2) 1.12 ns smc 14 data hold after mck rising (3) -0.14 ns smc 15 data setup before nrd high (2) c nrd = 0 pf 6.1 ns c nrd derating 0.0336 ns/pf smc 16 data hold after nrd high (3) c nrd = 0 pf 5.12 ns c nrd derating 0.0336 ns/pf smc 17 nrd high to nbs0/a0 change (1) c nbs0 = 0 pf nrd hold length * t cpmck + 0.2 ns c nbs0 derating 0.0336 ns/pf smc 18 nrd high to nbs1 change (1) c nbs1 = 0 pf nrd hold length * t cpmck + 0.4 ns c nbs1 derating 0.0336 ns/pf smc 19 nrd high to nbs2/a1 change (1) c nbs2 = 0 pf nrd hold length * t cpmck + 0.4 ns c nbs2 derating 0.0336 ns/pf smc 20 nrd high to nbs3 change (1) c nbs3 = 0 pf nrd hold length * t cpmck + 0.2 ns c nbs3 derating 0.0336 ns/pf smc 21 nrd high to a2 - a25 change (1) c add = 0 pf nrd hold length * t cpmck + 2.8 ns c add derating 0.0336 ns/pf smc 22 nrd high to ncs inactive (1) c ncs = 0 pf (nrd hold length - ncs rd hold length) * t cpmck + 0.4 ns c ncs derating 0.0336 ns/pf smc 23 nrd pulse width c nrd = 0 pf nrd pulse length * t cpmck + 0.1 ns c nrd derating 0.0336 ns/pf ncs controlled (read_mode = 0) smc 24 data setup before mck rising (4) 1.12 ns smc 25 data hold after mck rising (5) -0.143 ns smc 26 data setup before ncs high (4) c ncs = 0 pf 6.44 ns c ncs derating 0.0336 ns/pf smc 27 data hold after ncs high (5) c ncs = 0 pf 5.5 ns c ncs derating 0.0336 ns/pf 623 6062b?atarm?15-nov-05 at91sam9261 note: 1. hold length = total cycle duration - setup durati on - pulse duration. ?hold length? is for ?ncs rd hold length? or ?nrd hold length?. 2. only one of these two timings needs to be met. 3. only one of these two timings needs to be met. 4. only one of these two timings needs to be met. 5. only one of these two timings needs to be met. smc 28 ncs high to nbs0/a0 change (1) c nbs0 = 0 pf ncs rd hold length * t cpmck - 0.1 ns c nbs0 derating 0.0336 ns/pf smc 29 ncs high to nbs1 change (1) c nbs1 = 0 pf ncs rd hold length * t cpmck + 0.1 ns c nbs1 derating 0.0336 ns/pf smc 30 ncs high to nbs2/a1 change (1) c nbs2 = 0 pf ncs rd hold length * t cpmck + 0.1 ns c nbs2 derating 0.0336 ns/pf smc 31 ncs high to nbs3 change (1) c nbs3 = 0 pf ncs rd hold length * t cpmck - 0.1 ns c nbs3 derating 0.0336 ns/pf smc 32 ncs high to a2 - a25 change (1) c add = 0 pf ncs rd hold length * t cpmck + 2.5 ns c add derating 0.0336 ns/pf smc 33 ncs high to nrd inactive (1) c ncs = 0 pf (ncs rd hold length - nrd hold length)* t cpmck - 0.3 ns c ncs derating 0.0336 ns/pf smc 34 ncs pulse width c ncs = 0 pf ncs rd pulse length * t cpmck + 0.4 ns c ncs derating 0.0336 ns/pf table 39-2. smc read signals with hold settings symbol parameter conditions min max units 624 6062b?atarm?15-nov-05 at91sam9261 notes: 1. only one of these two timings needs to be met. 2. only one of these two timings needs to be met. 3. only one of these two timings needs to be met. 4. only one of these two timings needs to be met. table 39-3. smc read signals with no hold settings symbol parameter conditions min max units nrd controlled (read_mode = 1) smc 35 data setup before mck rising (1) 2.94 ns smc 36 data hold after mck rising (2) -1.66 ns smc 37 data setup before nrd high (1) c nrd = 0 pf 7.92 ns c nrd derating 0.0336 ns/pf smc 38 data hold after nrd high (2) c nrd = 0 pf 7.92 ns c nrd derating 0.0336 ns/pf ncs controlled (read_mode = 0) smc 39 data setup before mck rising (3) 1.12 ns smc 40 data hold after mck rising (4) -0.143 ns smc 41 data setup before ncs high (3) c ncs = 0 pf 6.5 ns c ncs derating 0.0336 ns/pf smc 42 data hold after ncs high (4) c ncs = 0 pf 5.5 ns c ncs derating 0.0336 ns/pf 625 6062b?atarm?15-nov-05 at91sam9261 table 39-4. smc write signals with hold settings symbol parameter conditions min max units smc 43 mck rising to data out valid c data = 0 pf 5.38 ns c data derating 0.0336 ns/pf nwr controlled (write_mode = 1) smc 44 data out valid before nwr high c = 0 pf (nwr pulse length - 1) * t cpmck ns c data derating 0.0336 ns/pf c nwr derating 0.0336 ns/pf smc 45 data out valid after nwr high (1) c = 0 pf nwr hold length * t cpmck ns c data derating 0.0336 ns/pf c nwr derating 0.0336 ns/pf smc 46 nwr high to nbs0/a0 change (1) c nbs0 = 0 pf nwr hold length * t cpmck - 0.2 ns c nbs0 derating 0.0336 ns/pf smc 47 nwr high to nbs1 change (1) c nbs1 = 0 pf nwr hold length * t cpmck ns c nbs1 derating 0.0336 ns/pf smc 48 nwr high to nbs2/a1 change (1) c nbs2 = 0 pf nwr hold length * t cpmck ns c nbs2 derating 0.0336 ns/pf smc 49 nwr high to nbs3 change (1) c nbs3 = 0 pf nwr hold length * t cpmck - 0.2 ns c nbs3 derating 0.0336 ns/pf smc 50 nwr high to a2 - a25 change (1) c add = 0 pf nwr hold length * t cpmck + 2.4 ns c add derating 0.0336 ns/pf smc 51 nwr high to ncs inactive (1) c ncs = 0 pf (nwr hold length - ncs wr hold length)* t cpmck - 0.1 ns c ncs derating 0.0336 ns/pf smc 52 nwr pulse width c nwr = 0 pf nwr pulse length * t cpmck - 0.1 ns c nwr derating 0.0336 ns/pf ncs controlled (write_mode = 0) smc 53 data out valid before ncs high c = 0 pf (ncs wr pulse length - 1)* t cpmck - 0.1 ns c data derating 0.0336 ns/pf c ncs derating 0.0336 ns/pf 626 6062b?atarm?15-nov-05 at91sam9261 note: 1. hold length = total cycle dura tion - setup duration - pulse durati on. ?hold length? is for ?ncs wr hold length? or ?nwr hold length?. smc 54 data out valid after ncs high (1) c = 0 pf ncs wr hold length * t cpmck + 0.1 ns c data derating 0.0336 ns/pf c ncs derating 0.0336 ns/pf smc 55 ncs high to nwr inactive (1) c ncs = 0 pf (ncs wr hold length - nwr hold length)* t cpmck + 0.1 ns c ncs derating 0.0336 ns/pf table 39-4. smc write signals with hold settings symbol parameter conditions min max units table 39-5. smc write signals with no hold se ttings (nwr controlled only) symbol parameter conditions min max units smc 56 nwr rising to a2-a25 valid c add = 0 pf 8.18 ns c add derating 0.0336 ns/pf smc 57 nwr rising to nbs0/a0 valid c nbs0 = 0 pf 4.87 ns c nbs0 derating 0.0336 ns/pf smc 58 nwr rising to nbs1 change c nbs1 = 0 pf 4.66 ns c nbs1 derating 0.0336 ns/pf smc 59 nwr rising to a1/nbs2 change c nbs2 = 0 pf 5.01 ns c nbs2 derating 0.0336 ns/pf smc 60 nwr rising to nbs3 change c nbs3 = 0 pf 4.74 ns c nbs3 derating 0.0336 ns/pf smc 61 nwr rising to ncs rising c ncs = 0 pf 5.7 ns c ncs derating 0.0336 ns/pf smc 62 data out valid before nwr rising c = 0 pf (nwr pulse length - 1) * t cpmck ns c data derating 0.0336 ns/pf c nwr derating 0.0336 ns/pf smc 63 data out valid after nwr rising c = 0 pf 6.59 ns c data derating 0.0336 ns/pf c nwr derating 0.0336 ns/pf smc 64 nwr pulse width c nwr = 0 pf nwr pulse length * t cpmck + 0.1 ns c nwr derating 0.0336 ns/pf 627 6062b?atarm?15-nov-05 at91sam9261 table 39-6. smc read signals in page mode symbol parameter conditions min max units smc 65 data setup before mck rising 1.12 ns smc 66 data hold after mck rising -0.143 ns 628 6062b?atarm?15-nov-05 at91sam9261 figure 39-4. smc signals for ncs controlled accesses mck internal signal nrd ncs d0 - d31 nwr a2-a25 a0/a1/nbs[3:0] smc 8 smc 9 smc 6 smc 7 smc 6 smc 7 smc 10 smc 11 smc 53 smc 54 smc 43 smc 26 smc 27 smc 1 smc 32 smc 31 smc 6 smc 8 smc 9 smc 42 smc 41 smc 33 smc 40 smc 39 smc 34 smc 7 smc 30 smc 29 smc 28 smc 34 smc 25 smc 24 smc 33 smc 32 smc 31 smc 30 smc 29 smc 28 smc 34 smc 55 smc 32 smc 31 smc 30 smc 29 smc 28 smc 5 smc 4 smc 3 smc 2 read cycle with no hold read cycle with hold write cycle with hold 629 6062b?atarm?15-nov-05 at91sam9261 figure 39-5. smc signals for nrd and nwr controlled accesses mck internal signal nrd ncs d0 - d31 nwr a2-a25 a0/a1/nbs[3:0] smc 1 smc 21 smc 8 smc 9 smc 6 smc 7 smc 6 smc 10 smc 11 smc 37 smc 38 smc 62 smc 56 smc 43 smc 61 smc 22 smc 6 smc 9 smc 8 smc 6 smc 15 smc 16 smc 10 smc 44 smc 45 smc 11 smc 51 smc 21 smc 5 smc 4 smc 3 smc 2 smc 22 smc 35 smc 36 smc 20 smc 19 smc 18 smc 17 smc 23 smc 60 smc 59 smc 58 smc 57 smc 64 smc 23 smc 13 smc 14 smc 20 smc 19 smc 18 smc 17 smc 52 smc 49 smc 48 smc 47 smc 46 smc 50 smc 43 smc 63 read cycle with no hold write cycle with no hold read cycle with hold write cycle with hold 630 6062b?atarm?15-nov-05 at91sam9261 figure 39-6. smc signals for read ac cesses in page mode (1) note: 1. 2 i 5 and depends on page size. see smc description for more information. 39.2.2 sdramc signals relative to sdck table 39-7 and table 39-8 below show timings relative to operating condition limits defined in the section ?conditions and timings computation? on page 618 . mck internal signal nrd ncs d0 - d31 a i -a25 a0/a1/nbs[3:0] smc 7 smc 1 smc 1 smc 6 smc 8 smc 9 smc 66 smc 65 smc 5 smc 4 smc 3 smc 2 smc 66 smc 65 smc 66 smc 65 smc 5 smc 4 smc 3 smc 2 smc 5 smc 4 smc 3 smc 2 smc 5 smc 4 smc 3 smc 2 a2 - a i-1 smc 1 smc 1 smc 1 smc 1 i > 2 table 39-7. sdramc clock signal symbol parameter conditions min max units 1/(t cpsdck ) sdram controller clock frequency 119 mhz t cpsdck sdram controller clock period 8.38 ns table 39-8. sdramc signals symbol parameter conditions min max units sdramc 1 sdcke high before sdck rising edge (1) c sdcke = 0 pf t clmck + 4.62 ns c sdcke derating 0.0187 ns/pf sdramc 2 sdcke low after sdck rising edge (1) c sdcke = 0 pf t chmck - 5.04 ns c sdcke derating 0.0167 ns/pf 631 6062b?atarm?15-nov-05 at91sam9261 sdramc 3 sdcke low before sdck rising edge (1) c sdcke = 0 pf t clmck + 4.62 ns c sdcke derating 0.0187 ns/pf sdramc 4 sdcke high after sdck rising edge (1) c sdcke = 0 pf t chmck - 5.04 ns c sdcke derating 0.0167 ns/pf sdramc 5 sdcs low before sdck rising edge (1) c sdcs = 0 pf t clmck + 4.57 ns c sdcs derating 0.0336 ns/pf sdramc 6 sdcs high after sdck rising edge (1) c sdcs = 0 pf t chmck - 4.83 ns c sdcs derating 0.0336 ns/pf sdramc 7 ras low before sdck rising edge (1) c ras = 0 pf t clmck + 4.57 ns c ras derating 0.0336 ns/pf sdramc 8 ras high after sdck rising edge (1) c ras = 0 pf t chmck - 4.56 ns c ras derating 0.0167 ns/pf sdramc 9 sda10 change before sdck rising edge (1) c sda10 = 0 pf t clmck + 4.48 ns c sda10 derating 0.0187 ns/pf sdramc 10 sda10 change after sdck rising edge (1) c sda10 = 0 pf t chmck - 4.67 ns c sda10 derating 0.0167 ns/pf sdramc 11 address change before sdck rising edge (1) c add = 0 pf t clmck + 4.91 ns c add derating 0.0336 ns/pf sdramc 12 address change after sdck rising edge (1) c add = 0 pf t chmck - 4.21 ns c add derating 0.0336 ns/pf sdramc 13 bank change before sdck rising edge (1) c ba = 0 pf t clmck + 4.79 ns c ba derating 0.0336 ns/pf sdramc 14 bank change after sdck rising edge (1) c ba = 0 pf t chmck - 4.32 ns c ba derating 0.0336 ns/pf sdramc 15 cas low before sdck rising edge (1) c cas = 0 pf t clmck + 4.68 ns c cas derating 0.0190 ns/pf sdramc 16 cas high after sdck rising edge (1) c cas = 0 pf t chmck - 5.08 ns c cas derating 0.0167 ns/pf sdramc 17 dqm change before sdck rising edge (1) c dqm = 0 pf t clmck + 4.67 ns c dqm derating 0.0336 ns/pf table 39-8. sdramc signals symbol parameter conditions min max units 632 6062b?atarm?15-nov-05 at91sam9261 note: 1. the derating factor is not to be applied to t clmck or t chmck . sdramc 18 dqm change after sdck rising edge (1) c dqm = 0 pf t chmck - 4.38 ns c dqm derating 0.0336 ns/pf sdramc 19 d0-d15 in setup before sdck rising edge 1.95 ns sdramc 20 d0-d15 in hold after sdck rising edge -0.12 ns sdramc 21 d16-d31 in setup before sdck rising edge 1.12 ns sdramc 22 d16-d31 in hold after sdck rising edge -0.19 ns sdramc 23 sdwe low before sdck rising edge c sdwe = 0 pf t clmck + 4.47 ns c sdwe derating 0.0187 ns/pf sdramc 24 sdwe high after sdck rising edge c sdwe = 0 pf t chmck - 4.61 ns c sdwe derating 0.0167 ns/pf sdramc 25 d0-d15 out valid before sdck rising edge c = 0 pf t clmck - 7.65 ns c data derating 0.0336 ns/pf sdramc 26 d0-d15 out valid after sdck rising edge c = 0 pf t chmck - 4.24 ns c data derating 0.0336 ns/pf sdramc 27 d16-d31 out valid before sdck rising edge c = 0 pf t clmck - 6.98 ns c data derating 0.0336 ns/pf sdramc 28 d16-d31 out valid after sdck rising edge c = 0 pf t chmck - 4.41 ns c data derating 0.0336 ns/pf table 39-8. sdramc signals symbol parameter conditions min max units 633 6062b?atarm?15-nov-05 at91sam9261 figure 39-7. sdramc signals relative to sdck ras a0 - a9, a11 - a13 d0 - d15 read sdck sda10 d0 - d15 to write sdramc 1 sdcke sdramc 2 sdramc 3 sdramc 4 sdcs sdramc 5 sdramc 6 sdramc 5 sdramc 6 sdramc 5 sdramc 6 sdramc 7 sdramc 8 cas sdramc 15 sdramc 16 sdramc 15 sdramc 16 sdwe sdramc 23 sdramc 24 sdramc 9 sdramc 10 sdramc 9 sdramc 10 sdramc 9 sdramc 10 sdramc 11 sdramc 12 sdramc 11 sdramc 12 sdramc 11 sdramc 12 ba0/ba1 sdramc 13 sdramc 14 sdramc 13 sdramc 14 sdramc 13 sdramc 14 sdramc 17 sdramc 18 sdramc 17 sdramc 18 dqm0 - dqm3 sdramc 19 sdramc 20 d16 - d31 read sdramc 21 sdramc 22 sdramc 25 sdramc 26 d16 - d31 to write sdramc 27 sdramc 28 634 6062b?atarm?15-nov-05 at91sam9261 40. at91sam9261 mechanic al characteristics 40.1 thermal considerations 40.1.1 thermal data table 40-1 summarizes the thermal resistance data depending on the package. 40.1.2 junction temperature the average chip-junction temperature, t j , in c can be obtained from the following: 1. 2. where: ja = package thermal resistance, junction-to-ambient (c/w), provided in table 40-4 on page 635 . jc = package thermal resistance, junction-to-case thermal resistance (c/w), provided in table 40-4 on page 635 . heat sink = cooling device thermal resistance (c/w), provided in the device datasheet. p d = device power consumption (w) estimated from data provided in the section ?power consumption? on page 612 . t a = ambient temperature (c). from the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. if a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature t j in c. table 40-1. thermal resistance data symbol parameter condition package typ unit ja junction-to-ambient thermal resistance still air lfbga217 39.1 c/w jc junction-to-case thermal resistance lfbga217 7.1 t j t a p d ja () t j t a p ( d ( heatsink jc )) 635 6062b?atarm?15-nov-05 at91sam9261 40.2 package drawings figure 40-1. 217-balls lfbga package drawing table 40-2. soldering information ball land 0.43 mm 0.05 solder mask opening 0.30 mm 0.05 table 40-3. device and 217-ball lfbg a package maximum weight 450 mg table 40-4. 217-ball lfbga package characteristics moisture sensitivity level 3 table 40-5. package reference jedec drawing reference mo-205 jesd97 classification e1 636 6062b?atarm?15-nov-05 at91sam9261 40.3 soldering profile table 40-6 gives the recommended soldering profile from j-std-20. note: it is recommended to apply a soldering temperature higher than 250c. a maximum of three reflow passes is allowed per component. table 40-6. soldering profile profile feature green package average ramp-up rate (217c to peak) 3 c/sec. max. preheat temperature 175c 25c 180 sec. max. temperature maintained above 217c 60 sec. to 150 sec. time within 5 c of actual peak temperature 20 sec. to 40 sec. peak temperature range 260 +0 c ramp-down rate 6 c/sec. max. time 25 c to peak temperature 8 min. max. 637 6062b?atarm?15-nov-05 at91sam9261 41. at91sam9261 ordering information table 41-1. at91sam9261 ordering information ordering code package package type temperature operating range AT91SAM9261-CJ bga217 rohs-compliant industrial -40c to 85c 638 6062b?atarm?15-nov-05 at91sam9261 42. at91sam9261 errata these errata refer to at91sam9261 devices packaged in 217-ball bga with the marking AT91SAM9261-CJ. 42.1 boot rom 42.1.1 watchdog disable when at91sam9261 boots on internal rom (bms =1) the watchdog timer is disabled by soft- ware. because the watchdog mode register is a ?write once?, the system, designed to boot on an spi dataflash, cannot reuse the watchdog functionality. problem fix/workaround if the watchdog feature is mandatory for the application, the system must boot on external memory connected on cs0 (bms = 0). 42.2 sdram controller 42.2.1 sdclk clock active after reset after a reset the sdram clock is always active leading in over consumption in the pad. problem fix/workaround the following sequence allows to stop the sdram clock. 1. set the bit lpcb in the sdramc low power register. 2. write 0 in the sdramc mode register and perform a dummy write in sdram to complete. 42.3 serial peripheral interface (spi) 42.3.1 pulse generation on spck in master mode, there is an additional pulse generated on spck when the spi is configured as follows: ? the baudrate is odd and different from 1. ? the polarity is set to 1. ? the phase is set to 0 . problem fix/workaround none. 42.3.2 bad tx_ready behavior when csaat=1 and scbr = 1 if the spi2 is programmed with csaat = 1, scbr(baudrate) = 1 and two transfers are per- formed consecutively on the same slave with an idle state between them, the tx_ready signal does not rise after the second data has been transferred in the shifter. this can imply for example that the second data is sent twice. problem fix/workaround none. do not use the combin ation csaat=1 and scbr =1. 639 6062b?atarm?15-nov-05 at91sam9261 42.3.3 lastxfer (last transfer) behavior in fixed mode, with csaat bit set, and in ?pdc mode? the chip select can rise depending on the data written in the spi_tdr when the tx_empty flag is set. for example, if the pdc writes a "1" in bit 24 (lastxfer bit) of the spi_tdr, the chip select rises as soon as the txempty flag is set. problem fix/workaround use the cs in pio mode when ?pdc mode? is required and cs has to be maintained between transfers. 42.4 serial synchronous controller (ssc) 42.4.1 transmitter limitations in slave mode if tk are programmed as input and tf is programmed as output and requested to be set to low/high during data emission, the frame sync hro is generated one bit clock period after the data start, one data bit is lost. this problem does not exist when generating periodic synchro. problem fix/workaround the data need to be delayed for one bit clock period with an external assembly. in the following schematic, td, tk and nrst are at91sam9261 signals, txd is the delayed data to connect to the device. 42.4.2 transmitter limitations in slave mode if tk is programmed as output and tf is programmed as input, it is impossible to emit data when start of edge (rising or falling) of synchro with a start delay equal to zero. problem fix/workaround none. 42.4.3 periodic transmission limitations in master mode if last significant bit is sent first (msbf = 0) the first tag during the frame synchro is not sent. problem fix/workaround 640 6062b?atarm?15-nov-05 at91sam9261 none. 42.5 two-wire interface (twi) 42.5.1 clock divider the value of cldiv x 2 ckdiv must be less than or equal to 8191, the value of chdiv x 2 ckdiv must be less than or equal to 8191 problem fix/workaround none. 42.5.2 behavior of ovre bit in master mode during a read access, if the sequence described as follows occurs: 1. a byte is received but no t read through the twi_rhr. 2. a step command is performed through the twi_cr to end the read access. 3. the last data byte is received. the overrun flag (ovre) does not rise, whereas a data byte has been lost. problem fix/workaround none. 42.6 usart 42.6.1 hardware handshake the hardware handshake does not work at speeds higher than 750 kbauds. problem fix/workaround none. 641 6062b?atarm?15-nov-05 at91sam9261 642 6062b?atarm?15-nov-05 at91sam9261 43. revision history table 43-1. revision history doc. rev. date comments change request ref. 6062a 02-jun-05 first issue. 643 6062b?atarm?15-nov-05 at91sam9261 6062b 14-oct-05 changed spi pin names in figure 2-1, ?at91sam9261 block diagram,? on page 4 , table 3-1, ?signal description by peripheral,? on page 5 , table 10-1, ?multiplexing on pio controller a,? on page 30 , table 10-2, ?multiplexing on pio controller b,? on page 31 and table 10-3, ?multiplexing on pio controller c,? on page 32 . 05-398 corrected ebi/compact flash interface descr iption with updated a22 pin functionality in figure 2-1, ?at91sam9261 block diagram,? on page 4 , figure 20-1, ?organization of the external bus interface,? on page 131 and table 20-6, ?cfce1 and cfce2 truth table,? on page 139 . 05-481 changed value of programmable pull-up resistor in section 6.4 ?pio controller a, b and c lines? on page 12 . 05-496 bus matrix: corrected reset values of slave configuration registers 0, 1 and 2 in table 19-1, ?register mapping,? on page 124 . 05-498 bus matrix: updated bit information in section 19.5.5 ?usb pad pull-up control register? on page 129 . 05-486 smc: corrected reset values of smc_setup, smc_cycle and smc_mode in table 21-9, ?smc register mapping,? on page 181 . 05-499 sdramc: removed hardware interface section from section 22.4 ?application example? on page 188 . 05-468 sdramc: updated figure 22-2, ?sdram device initialization sequence,? on page 191 . 05-479 pmc: updated section 25.8 ?programming sequence? on page 229 . 05-393 pmc: updated figure 25-5, ?change plla programming,? on page 235 and added figure 25-6, ?change pllb programming,? on page 235 . 05-198 pmc: added important note on programming bit 29 of ckgr_pllar in section 25.8 ?programming sequence? on page 229 and in section 25.10.9 ?pmc clock generator pll a register? on page 245 . 05-239 aic: added informat ion on external interrupt sources for bit srctype in section 26.8.3 ?aic source mode register? on page 267 . 05-269 dbgu: updated bit description for sramsiz in section 27.5.10 ?debug unit chip id register? on page 300 . 05-306 pio: removed reference to resistor value in section 28.4.1 ?pull-up resistor control? on page 311 . 05-497 spi: references to mck/32 removed throughout. figure 29-1, ?block diagram,? on page 338 and figure 29-5, ?master mode block diagram,? on page 343 changed. 05-484 spi: section 29.7.5 ?spi status register? on page 356 spi_rcr, spi_rncr, spi_tcr, spi_tncr location defined. 04-183 spi: section 29.7.4 ?spi transmit data register? on page 355 , lastxfer: last transfer text added. 05-434 spi: section 29.7.2 ?spi mode register? on page 352 , pcsdec: chip select decode on changed 05-476 mci: corrected pin names in figure 34-4, ?mmc bus connections (one slot),? on page 498 . 05-308 uhp: added information on memory access errors in ?usb host port (uhp)? on page 522 . 05-240 table 43-1. revision history (continued) doc. rev. date comments change request ref. 644 6062b?atarm?15-nov-05 at91sam9261 6062b 30-aug-05 updated r pullup values in table 38-2, ?dc characteristics,? on page 611 .review corrected backup consumption value in table 38-3, ?power consumption for different modes(1),? on page 613 . 05-332 removed data on usb transceiver switching characteristics at low speed in section 38.6 ?usb transceiver characteristics? on page 616 . review corrected value of r ext in figure 38-2, ?usb data signal rise and fall times,? on page 617 . review removed mtbf data from section 40.1 ?thermal considerations? on page 634 . 05-345 inserted table 40-2, ?soldering information,? on page 635 . 05-347 updated section 41. ?at91sam9261 orde ring information? on page 637 . 05-485 added section 42. ?at91sam9261 errata? on page 638 . table 43-1. revision history (continued) doc. rev. date comments change request ref. 645 6062b?atarm?15-nov-05 at91sam9261 i 6062b?atarm?15-nov-05 at91sam9261 table of contents features .............. ................. ................ ................. .............. ...........1 1 description ........ ................. ................ ................. .............. ...........3 2 block diagram ............... ................ ................. ................ ..............4 3 signal description ........... ................. ................ ................. ...........5 4 package and pinout ............. ................. .............. .............. ...........9 4.1 mechanical overview of the 217-ball lfbga package ............................ 9 4.2 217-ball lfbga package pinout .............................................................. 9 5 power considerations .... ................. ................ .............. ............11 5.1 power supplies ....................................................................................... 11 5.2 power consumption ............................................................................... 11 6 i/o line considerations .. ................. ................ .............. ............11 6.1 jtag port pins ....................................................................................... 11 6.2 test pin .................................................................................................. 12 6.3 reset pin ................................................................................................ 12 6.4 pio controller a, b and c lines ............................................................. 12 6.5 shutdown logic pins .............................................................................. 12 7 processor and architecture .............. .............. .............. ............13 7.1 arm926ej-s processor ......................................................................... 13 7.2 debug and test features ....................................................................... 14 7.3 bus matrix ............................................................................................... 14 7.4 peripheral dma controller ...................................................................... 15 8 memories .............. ................ .............. .............. .............. ............15 8.1 embedded memories ............................................................................. 15 8.2 memory mapping .................................................................................... 15 9 system controller ......... ................ ................. ................ ............21 9.1 block diagram ........................................................................................ 21 9.2 reset controller ...................................................................................... 23 9.3 shutdown controller ............................................................................... 23 9.4 general-purpose backup registers ....................................................... 23 9.5 clock generator ..................................................................................... 23 9.6 power management controller ...............................................................24 ii 6062b?atarm?15-nov-05 at91sam9261 9.7 periodic interval timer ............................................................................24 9.8 watchdog timer ..................................................................................... 24 9.9 real-time timer ...................................................................................... 24 9.10 advanced interrupt controller ...............................................................25 9.11 debug unit ............................................................................................ 25 9.12 pio controllers ..................................................................................... 26 10 peripherals ............ ................ .............. .............. .............. ............27 10.1 peripheral mapping .............................................................................. 27 10.2 peripheral multiplexing on pio lines ................................................... 28 10.3 peripheral identifiers ............................................................................. 33 10.4 external bus interface .......................................................................... 34 10.5 static memory controller ...................................................................... 35 10.6 sdram controller ................................................................................ 35 10.7 serial peripheral interface .................................................................... 36 10.8 two-wire interface ................................................................................ 36 10.9 usart ................................................................................................. 36 10.10 synchronous serial controller ............................................................ 37 10.11 timer counter ..................................................................................... 37 10.12 multimedia card interface .................................................................. 38 10.13 usb .................................................................................................... 38 10.14 lcd controller .................................................................................... 39 11 arm926ej-s processor over view .......... ............ ............ .........40 11.1 overview ............................................................................................... 40 11.2 block diagram ...................................................................................... 41 11.3 arm9ej-s processor ........................................................................... 41 11.4 cp15 coprocessor ............................................................................... 49 11.5 memory management unit (mmu) ....................................................... 52 11.6 caches and write buffer ...................................................................... 53 11.7 tightly-coupled memory interface ....................................................... 55 11.8 bus interface unit ................................................................................. 56 12 at91sam9261 debug and test ............. .............. ............ .........58 12.1 overview ............................................................................................... 58 12.2 block diagram ...................................................................................... 58 12.3 application examples ........................................................................... 59 12.4 debug and test pin description ........................................................... 60 iii 6062b?atarm?15-nov-05 at91sam9261 12.5 functional description .......................................................................... 61 13 at91sam boot program ... ................ .............. .............. ............81 13.1 description ............................................................................................ 81 13.2 flow diagram ....................................................................................... 81 13.3 device initialization ............................................................................... 82 13.4 dataflash boot ..................................................................................... 82 13.5 sam-ba boot ....................................................................................... 85 13.6 hardware and software constraints ..................................................... 89 14 reset controller (rstc) ............... ................. ................ ............90 14.1 description ............................................................................................ 90 14.2 block diagram ...................................................................................... 90 14.3 functional description .......................................................................... 90 14.4 reset controller (rstc) user interface ............................................... 98 15 real-time timer (rtt) .... ............... ................. .............. ............101 15.1 overview ............................................................................................. 101 15.2 block diagram .................................................................................... 101 15.3 functional description ........................................................................ 101 15.4 real-time timer (rtt) user interface ................................................ 103 16 periodic interval timer (pit) ............. .............. .............. ..........106 16.1 overview ............................................................................................. 106 16.2 block diagram .................................................................................... 106 16.3 functional description ........................................................................ 106 16.4 periodic interval timer (pit) user interface ....................................... 108 17 watchdog timer (wdt) ..... .............. .............. .............. ............111 17.1 overview ............................................................................................. 111 17.2 block diagram .................................................................................... 111 17.3 functional description ........................................................................ 112 17.4 watchdog timer (wdt) user interface .............................................. 114 18 shutdown controller (s hdwc) ............ .............. ........... ..........117 18.1 description .......................................................................................... 117 18.2 block diagram .................................................................................... 117 18.3 i/o lines description ..........................................................................117 18.4 product dependencies ....................................................................... 117 18.5 functional description ........................................................................ 117 iv 6062b?atarm?15-nov-05 at91sam9261 18.6 shutdown controller (shdwc) user interface .................................. 119 19 bus matrix ........ ................ ................. .............. .............. ............122 19.1 overview ............................................................................................. 122 19.2 memory mapping ................................................................................ 122 19.3 special bus granting techniques ...................................................... 122 19.4 arbitration ........................................................................................... 123 19.5 bus matrix user interface ................................................................... 124 20 external bus interface (ebi) ......... ................. .............. ............130 20.1 overview ............................................................................................. 130 20.2 block diagram .................................................................................... 131 20.3 i/o lines description ..........................................................................132 20.4 application example ........................................................................... 133 20.5 product dependencies ....................................................................... 136 20.6 functional description ........................................................................ 137 21 static memory controller (smc) .. ................. .............. ............145 21.1 overview ............................................................................................. 145 21.2 block diagram .................................................................................... 145 21.3 i/o lines description ..........................................................................146 21.4 multiplexed signals ............................................................................. 146 21.5 application example ........................................................................... 147 21.6 product dependencies ....................................................................... 147 21.7 external memory mapping .................................................................. 148 21.8 connection to external devices ......................................................... 148 21.9 standard read and write protocols ................................................... 152 21.10 automatic wait states ...................................................................... 161 21.11 data float wait states ...................................................................... 165 21.12 external wait .................................................................................... 169 21.13 slow clock mode .............................................................................. 175 21.14 asynchronous page mode ............................................................... 178 21.15 static memory controller (smc) user interface ............................... 181 22 sdram controller (sdramc) ......... .............. .............. ............187 22.1 description .......................................................................................... 187 22.2 block diagram .................................................................................... 187 22.3 i/o lines description ..........................................................................188 22.4 application example ........................................................................... 188 v 6062b?atarm?15-nov-05 at91sam9261 22.5 product dependencies ....................................................................... 190 22.6 functional description ........................................................................ 192 22.7 sdram controller (sdramc) user interface ................................... 199 23 peripheral dma controll er (pdc) ................. .............. ............209 23.1 description .......................................................................................... 209 23.2 block diagram .................................................................................... 210 23.3 functional description ........................................................................ 211 23.4 peripheral dma controller (pdc) user interface ............................... 214 24 clock generator ............ ................ ................. .............. ............221 24.1 description .......................................................................................... 221 24.2 slow clock crystal oscillator .............................................................. 221 24.3 slow clock rc oscillator .................................................................... 221 24.4 main oscillator .................................................................................... 221 24.5 divider and pll block ........................................................................ 223 25 power management controller (pmc) ................... .................226 25.1 description .......................................................................................... 226 25.2 master clock controller ...................................................................... 226 25.3 processor clock controller ................................................................. 227 25.4 application clock controller ............................................................... 228 25.5 usb clock controller ..........................................................................228 25.6 peripheral clock controller ................................................................. 229 25.7 hclock controller ............................................................................... 230 25.8 programmable clock output controller .............................................. 230 25.9 programming sequence ..................................................................... 230 25.10 clock switching details .................................................................... 237 25.11 power management controller (pmc) user interface ..................... 241 26 advanced interrupt contro ller (aic) ..... ............ ........... ..........259 26.1 description .......................................................................................... 259 26.2 block diagram .................................................................................... 259 26.3 application block diagram .................................................................. 259 26.4 aic detailed block diagram ............................................................... 260 26.5 i/o line description ............................................................................ 260 26.6 product dependencies ....................................................................... 260 26.7 functional description ........................................................................ 261 26.8 advanced interrupt controller (aic) user interface ............................ 272 vi 6062b?atarm?15-nov-05 at91sam9261 27 debug unit (dbgu) ....... ................ ................. .............. ............283 27.1 description .......................................................................................... 283 27.2 block diagram .................................................................................... 284 27.3 product dependencies ....................................................................... 285 27.4 uart operations ............................................................................... 285 27.5 debug unit (dbgu) user interface ................................................... 292 28 parallel input/output (pio) controller ................. ............ .......307 28.1 description .......................................................................................... 307 28.2 block diagram .................................................................................... 308 28.3 product dependencies ....................................................................... 309 28.4 functional description ........................................................................ 310 28.5 i/o lines programming example ........................................................ 315 28.6 parallel input/ouput (pio) controller user interface .......................... 316 29 serial peripheral interf ace (spi) ........ .............. .............. ..........337 29.1 description .......................................................................................... 337 29.2 block diagram .................................................................................... 338 29.3 application block diagram .................................................................. 338 29.4 signal description .............................................................................. 339 29.5 product dependencies ....................................................................... 339 29.6 functional description ........................................................................ 340 29.7 serial peripheral interface (spi) user interface ................................. 350 30 two-wire interface (twi) ............... ................. .............. ............363 30.1 overview ............................................................................................. 363 30.2 block diagram .................................................................................... 363 30.3 application block diagram .................................................................. 363 30.4 product dependencies ....................................................................... 364 30.5 functional description ........................................................................ 365 30.6 two-wire interface (twi) user interface ........................................... 370 31 universal synchronous/asynchr onous receiver/transmitter .. 379 31.1 description .......................................................................................... 379 31.2 block diagram .................................................................................... 380 31.3 application block diagram .................................................................. 381 31.4 i/o lines description ......................................................................... 381 31.5 product dependencies ....................................................................... 382 vii 6062b?atarm?15-nov-05 at91sam9261 31.6 functional description ........................................................................ 383 31.7 usart user interface ....................................................................... 406 32 synchronous serial controller (ssc) ................... .................424 32.1 overview ............................................................................................. 424 32.2 block diagram .................................................................................... 425 32.3 application block diagram .................................................................. 425 32.4 pin name list ..................................................................................... 426 32.5 product dependencies ....................................................................... 426 32.6 functional description ........................................................................ 426 32.7 ssc application examples ................................................................. 437 32.8 synchronous serial controller (ssc) user interface ......................... 439 33 timer/counter (tc) ....... ................ ................. .............. ............461 33.1 overview ............................................................................................. 461 33.2 block diagram .................................................................................... 461 33.3 pin name list ..................................................................................... 462 33.4 product dependencies ....................................................................... 462 33.5 functional description ........................................................................ 463 33.6 timer/counter (tc) user interface ..................................................... 476 34 multimedia card interface (mci) ..... .............. .............. ............495 34.1 overview ............................................................................................. 495 34.2 block diagram .................................................................................... 495 34.3 application block diagram .................................................................. 496 34.4 pin name list .................................................................................... 496 34.5 product dependencies ....................................................................... 497 34.6 bus topology ...................................................................................... 497 34.7 multimedia card operations ............................................................... 499 34.8 sd card operations ........................................................................... 505 34.9 multimedia card interface (mci) user interface ................................. 506 35 usb host port (uhp) .... ................ ................. .............. ............521 35.1 description .......................................................................................... 521 35.2 block diagram .................................................................................... 521 35.3 product dependencies ....................................................................... 522 35.4 functional description ........................................................................ 522 35.5 typical connection ............................................................................. 524 viii 6062b?atarm?15-nov-05 at91sam9261 36 usb device port (udp) ................. ................. .............. ............525 36.1 description .......................................................................................... 525 36.2 block diagram .................................................................................... 526 36.3 product dependencies ....................................................................... 526 36.4 typical connection ............................................................................. 527 36.5 functional description ........................................................................ 528 36.6 usb device port (udp) user interface .............................................. 542 37 lcd controller (lcdc) ... ................. .............. .............. ............559 37.1 description .......................................................................................... 559 37.2 block diagram .................................................................................... 560 37.3 i/o lines description ..........................................................................561 37.4 product dependencies ....................................................................... 561 37.5 functional description ........................................................................ 561 37.6 interrupts ............................................................................................ 581 37.7 configuration sequence ..................................................................... 581 37.8 double-buffer technique .................................................................... 583 37.9 register configuration guide .............................................................584 37.10 lcd controller (lcdc) user interface ............................................. 585 38 at91sam9261 electrical characteristics ......... ........... ..........611 38.1 absolute maximum ratings ................................................................ 611 38.2 dc characteristics .............................................................................. 611 38.3 power consumption ........................................................................... 612 38.4 clock characteristics ..........................................................................614 38.5 crystal oscillator characteristics ........................................................ 615 38.6 usb transceiver characteristics ........................................................ 616 39 at91sam9261 ac character istics ........ ............ ........... ..........618 39.1 applicable conditions and derating data ........................................... 618 39.2 ebi timings ........................................................................................ 621 40 at91sam9261 mechanical characteristi cs ............. ..............634 40.1 thermal considerations ..................................................................... 634 40.2 package drawings .............................................................................. 635 40.3 soldering profile ................................................................................. 636 41 at91sam9261 ordering information .. .............. ........... ..........637 42 at91sam9261 errata ...... ................. .............. .............. ............638 ix 6062b?atarm?15-nov-05 at91sam9261 42.1 boot rom ........................................................................................... 638 42.2 sdram controller .............................................................................. 638 42.3 serial peripheral interface (spi) ......................................................... 638 42.4 serial synchronous controller (ssc) ................................................. 639 42.5 two-wire interface (twi) .................................................................... 640 42.6 usart ............................................................................................... 640 43 revision history ............ ................ ................. .............. ............642 table of contents ............. ................. ................ ................. ............i printed on recycled paper. 6062b?atarm?15-nov-05 disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel? s web site, atmel assumes no liability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to , the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, conseque ntial, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if at mel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the ri ght to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications intended to support or sustain life. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 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